JP6866038B2 - パッケージデバイスの製造方法 - Google Patents

パッケージデバイスの製造方法 Download PDF

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Publication number
JP6866038B2
JP6866038B2 JP2017121277A JP2017121277A JP6866038B2 JP 6866038 B2 JP6866038 B2 JP 6866038B2 JP 2017121277 A JP2017121277 A JP 2017121277A JP 2017121277 A JP2017121277 A JP 2017121277A JP 6866038 B2 JP6866038 B2 JP 6866038B2
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JP
Japan
Prior art keywords
resin
groove
substrate
mold
filler
Prior art date
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Active
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JP2017121277A
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English (en)
Japanese (ja)
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JP2019009176A (ja
Inventor
祐人 伴
祐人 伴
元 青柳
元 青柳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Disco Corp
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Disco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Disco Corp filed Critical Disco Corp
Priority to JP2017121277A priority Critical patent/JP6866038B2/ja
Priority to KR1020180069877A priority patent/KR102418419B1/ko
Publication of JP2019009176A publication Critical patent/JP2019009176A/ja
Application granted granted Critical
Publication of JP6866038B2 publication Critical patent/JP6866038B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/98—Methods for disconnecting semiconductor or solid-state bodies

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Laser Beam Processing (AREA)
  • Dicing (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2017121277A 2017-06-21 2017-06-21 パッケージデバイスの製造方法 Active JP6866038B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2017121277A JP6866038B2 (ja) 2017-06-21 2017-06-21 パッケージデバイスの製造方法
KR1020180069877A KR102418419B1 (ko) 2017-06-21 2018-06-18 패키지 디바이스의 제조 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017121277A JP6866038B2 (ja) 2017-06-21 2017-06-21 パッケージデバイスの製造方法

Publications (2)

Publication Number Publication Date
JP2019009176A JP2019009176A (ja) 2019-01-17
JP6866038B2 true JP6866038B2 (ja) 2021-04-28

Family

ID=64959734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017121277A Active JP6866038B2 (ja) 2017-06-21 2017-06-21 パッケージデバイスの製造方法

Country Status (2)

Country Link
JP (1) JP6866038B2 (ko)
KR (1) KR102418419B1 (ko)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000124164A (ja) * 1998-10-16 2000-04-28 Mitsubishi Electric Corp 半導体装置の製造方法及び実装方法
JP2002100709A (ja) 2000-09-21 2002-04-05 Hitachi Ltd 半導体装置及びその製造方法
JP5659033B2 (ja) * 2011-02-04 2015-01-28 株式会社東芝 半導体装置の製造方法
JP6242776B2 (ja) * 2014-09-26 2017-12-06 富士フイルム株式会社 保護膜組成物、半導体装置の製造方法およびレーザーダイシング方法
JP6512298B2 (ja) * 2015-08-11 2019-05-15 株式会社村田製作所 高周波モジュールおよびその製造方法
JP2017056465A (ja) * 2015-09-14 2017-03-23 株式会社ディスコ パッケージ基板の加工方法

Also Published As

Publication number Publication date
JP2019009176A (ja) 2019-01-17
KR102418419B1 (ko) 2022-07-06
KR20180138532A (ko) 2018-12-31

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