JP6667326B2 - ダイボンダおよびボンディング方法 - Google Patents

ダイボンダおよびボンディング方法 Download PDF

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Publication number
JP6667326B2
JP6667326B2 JP2016053169A JP2016053169A JP6667326B2 JP 6667326 B2 JP6667326 B2 JP 6667326B2 JP 2016053169 A JP2016053169 A JP 2016053169A JP 2016053169 A JP2016053169 A JP 2016053169A JP 6667326 B2 JP6667326 B2 JP 6667326B2
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Japan
Prior art keywords
die
unit
waveform
bonding
imaging
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JP2016053169A
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Japanese (ja)
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JP2017168693A5 (enExample
JP2017168693A (ja
Inventor
牧　浩
浩 牧
高野　隆一
隆一 高野
英晴 小橋
英晴 小橋
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Fasford Technology Co Ltd
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Fasford Technology Co Ltd
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Priority to JP2016053169A priority Critical patent/JP6667326B2/ja
Priority to TW105135965A priority patent/TWI598968B/zh
Priority to KR1020160153596A priority patent/KR101923274B1/ko
Priority to CN201611028983.5A priority patent/CN107204302B/zh
Publication of JP2017168693A publication Critical patent/JP2017168693A/ja
Publication of JP2017168693A5 publication Critical patent/JP2017168693A5/ja
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Publication of JP6667326B2 publication Critical patent/JP6667326B2/ja
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    • H10P72/0446—
    • H10W72/071—
    • H10P72/0616—
    • H10P72/3206—
    • H10P72/50—
    • H10P74/203—
    • H10W72/019—
    • H10W72/90—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Supply And Installment Of Electrical Components (AREA)
JP2016053169A 2016-03-17 2016-03-17 ダイボンダおよびボンディング方法 Active JP6667326B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2016053169A JP6667326B2 (ja) 2016-03-17 2016-03-17 ダイボンダおよびボンディング方法
TW105135965A TWI598968B (zh) 2016-03-17 2016-11-04 Die bonder and bonding methods
KR1020160153596A KR101923274B1 (ko) 2016-03-17 2016-11-17 다이 본더 및 본딩 방법
CN201611028983.5A CN107204302B (zh) 2016-03-17 2016-11-18 芯片贴装机以及芯片贴装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016053169A JP6667326B2 (ja) 2016-03-17 2016-03-17 ダイボンダおよびボンディング方法

Publications (3)

Publication Number Publication Date
JP2017168693A JP2017168693A (ja) 2017-09-21
JP2017168693A5 JP2017168693A5 (enExample) 2019-04-18
JP6667326B2 true JP6667326B2 (ja) 2020-03-18

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ID=59904684

Family Applications (1)

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JP2016053169A Active JP6667326B2 (ja) 2016-03-17 2016-03-17 ダイボンダおよびボンディング方法

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JP (1) JP6667326B2 (enExample)
KR (1) KR101923274B1 (enExample)
CN (1) CN107204302B (enExample)
TW (1) TWI598968B (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7018341B2 (ja) * 2018-03-26 2022-02-10 ファスフォードテクノロジ株式会社 ダイボンディング装置および半導体装置の製造方法
US11069555B2 (en) 2018-09-03 2021-07-20 Assembleon B.V. Die attach systems, and methods of attaching a die to a substrate
JP7291586B2 (ja) * 2019-09-19 2023-06-15 ファスフォードテクノロジ株式会社 ダイボンディング装置および半導体装置の製造方法
KR102377826B1 (ko) * 2020-03-06 2022-03-23 세메스 주식회사 다이 이송 모듈 및 이를 포함하는 다이 본딩 장치
KR102377825B1 (ko) * 2020-03-06 2022-03-23 세메스 주식회사 다이 이송 모듈 및 이를 포함하는 다이 본딩 장치
KR102654727B1 (ko) * 2021-07-21 2024-04-03 세메스 주식회사 다이 본딩 방법 및 다이 본딩 장치
WO2024018937A1 (ja) * 2022-07-21 2024-01-25 ボンドテック株式会社 接合方法および接合装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2635889B2 (ja) * 1992-06-24 1997-07-30 株式会社東芝 ダイボンディング装置
JP2006156550A (ja) * 2004-11-26 2006-06-15 Tsukuba Seiko Co Ltd ダイボンディング装置
JP5150155B2 (ja) * 2007-02-23 2013-02-20 株式会社東芝 リニアアクチュエータおよびリニアアクチュエータを利用した装置
JPWO2009119193A1 (ja) * 2008-03-28 2011-07-21 芝浦メカトロニクス株式会社 電子部品の実装装置及び実装方法
JP2012069733A (ja) 2010-09-24 2012-04-05 Hitachi High-Tech Instruments Co Ltd ダイボンダの治工具管理方法、および、ダイボンダ
JP5666246B2 (ja) * 2010-10-29 2015-02-12 株式会社日立ハイテクインスツルメンツ ダイボンダ装置およびダイボンダ方法
JP5713787B2 (ja) * 2011-04-28 2015-05-07 芝浦メカトロニクス株式会社 電子部品の実装装置
KR101850738B1 (ko) * 2011-05-19 2018-04-24 주식회사 탑 엔지니어링 실시간 동작 데이터의 ｕｉ화면을 구성하는 다이본더
JP5771466B2 (ja) * 2011-07-12 2015-09-02 ファスフォードテクノロジ株式会社 ダイボンダ及びダイボンダの接合材供給方法
JP5989313B2 (ja) 2011-09-15 2016-09-07 ファスフォードテクノロジ株式会社 ダイボンダ及びボンディング方法
JP2014011287A (ja) * 2012-06-29 2014-01-20 Ohashi Seisakusho:Kk 半導体チップの送り装置
JP2015056596A (ja) * 2013-09-13 2015-03-23 株式会社日立ハイテクインスツルメンツ ダイボンダ及びダイボンダの構成方法
JP6324778B2 (ja) * 2014-03-18 2018-05-16 ファスフォードテクノロジ株式会社 ダイボンダの実装位置補正方法並びにダイボンダ及びボンディング方法
JP2015195261A (ja) * 2014-03-31 2015-11-05 ファスフォードテクノロジ株式会社 ダイボンダ及び半導体製造方法

Also Published As

Publication number Publication date
CN107204302B (zh) 2020-06-30
CN107204302A (zh) 2017-09-26
TW201810457A (zh) 2018-03-16
KR101923274B1 (ko) 2018-11-28
KR20170108786A (ko) 2017-09-27
TWI598968B (zh) 2017-09-11
JP2017168693A (ja) 2017-09-21

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