JP6623247B2 - フラッシュメモリおよびその製造方法 - Google Patents
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- JP6623247B2 JP6623247B2 JP2018074365A JP2018074365A JP6623247B2 JP 6623247 B2 JP6623247 B2 JP 6623247B2 JP 2018074365 A JP2018074365 A JP 2018074365A JP 2018074365 A JP2018074365 A JP 2018074365A JP 6623247 B2 JP6623247 B2 JP 6623247B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 239000000758 substrate Substances 0.000 claims description 44
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 36
- 229910052710 silicon Inorganic materials 0.000 claims description 36
- 239000010703 silicon Substances 0.000 claims description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 229920005591 polysilicon Polymers 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 230000006870 function Effects 0.000 claims description 4
- 238000009825 accumulation Methods 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 description 12
- 230000004048 modification Effects 0.000 description 12
- 238000012986 modification Methods 0.000 description 12
- 239000012535 impurity Substances 0.000 description 8
- 239000002784 hot electron Substances 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 238000003491 array Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 101100331289 Aquifex aeolicus (strain VF5) der gene Proteins 0.000 description 2
- 101100225969 Aquifex aeolicus (strain VF5) era gene Proteins 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Description
1つのメモリセルは、1つの記憶トランジスタと1つの選択トランジスタとを含む。
2:選択ゲート線
3:活性領域
4:共通コントロールゲート
5:共通ソース
6、7、8:絶縁層
9:シリコン基板
10:隣接する選択ゲート線の間の空間
12:開口
13:最初の絶縁層
14:2番目の絶縁層
15:3番目の絶縁層
16:最初のポリシリコン層
17:エッチングされた領域
18:2番目のポリシリコン層
19:選択ゲート線の間隔
20:絶縁層
100:pウエル領域またはp型のシリコン基板
101:nウエル領域
110:行選択・駆動回路
120:列選択・駆動回路
200:シリコン基板
202:周辺回路
210:絶縁層
220:導電層
230:メモリセルアレイ
Claims (19)
- 基板と、
前記基板表面または基板上に形成された導電領域と、
前記基板の表面から垂直方向に延在し、かつ活性領域を含む複数の柱状部と、
各柱状部の側部を取り囲むように形成された記憶トランジスタおよび選択トランジスタとを有し、
前記記憶トランジスタのゲートにはコントロールゲートが接続され、前記選択トランジスタのゲートには選択ゲートが接続され、
前記柱状部の一方の端部がビット線に電気的に接続され、前記柱状部の他方の端部が前記導電領域に電気的に接続され、
1つのメモリセルは、1つの記憶トランジスタと1つの選択トランジスタとを含む、NOR型のフラッシュメモリ。 - 前記コントロールゲートと前記柱状部の間に複数の絶縁層が形成され、複数の絶縁層の中央の絶縁層が電荷蓄積層として機能する、請求項1に記載のフラッシュメモリ。
- 前記柱状部はシリコンまたはポリシリコンから構成され、前記柱状部とコントロールゲートの間が複数の絶縁層で囲まれ、中央部の絶縁層がシリコンナイトライド膜から構成され、当該シリコンナイトライド膜に書き込みまたは消去動作で異なる電荷量を蓄積する、請求項1または2に記載のフラッシュメモリ。
- 前記柱状部はシリコンまたはポリシリコンから構成され、前記柱状部とコントロールゲートの間及び前記柱状部と選択ゲートの間が複数の絶縁層で囲まれ、中央部の絶縁層がシリコンナイトライド膜から構成され、当該シリコンナイトライド膜に書き込みまたは消去動作で異なる電荷量を蓄積する、請求項1ないし3いずれか1つに記載のフラッシュメモリ。
- 複数のメモリセルを含むメモリセルアレイが3次元構造を有する、請求項1ないし4いずれか1つに記載のフラッシュメモリ。
- 前記選択ゲートは、前記コントロールゲートよりも上方に位置する、請求項1ないし5いずれか1つに記載のフラッシュメモリ。
- 前記基板は、周辺回路が形成されたシリコン基板を含み、
前記導電領域は、絶縁領域を介して前記シリコン基板上に形成される、請求項1ないし6いずれか1つに記載のフラッシュメモリ。 - 前記コントロールゲートは、メモリセルアレイの全てのメモリセルに対して共通である、請求項1ないし7いずれか1つに記載のフラッシュメモリ。
- 前記導電領域は、メモリセルアレイの全てのメモリセルに対して共通である、請求項1ないし8いずれか1つに記載のフラッシュメモリ。
- 前記導電領域は、複数の導電領域を含む、請求項1ないし7いずれか1つに記載のフラッシュメモリ。
- 前記コントロールゲートは、複数のコントロールゲートを含む、請求項1ないし7いずれか1つに記載のフラッシュメモリ。
- フラッシュメモリはさらに、前記導電領域が複数の導電領域を含むとき、アドレス情報に基づき導電領域を選択する選択手段を含む、請求項10に記載のフラッシュメモリ。
- フラッシュメモリはさらに、前記コントロールゲートが複数のコントロールゲートを含むとき、アドレス情報に基づきコントロールゲートを選択する選択手段を含む、請求項11に記載のフラッシュメモリ。
- フラッシュメモリはさらに、プログラム動作時に、選択メモリセルのコントロールゲートに第1のプログラム電圧を印加し、前記導電領域に第2のプログラム電圧を印加し、前記選択ゲートを介して前記選択トランジスタを導通状態にする制御手段を含む、請求項1ないし13いずれか1つに記載のフラッシュメモリ。
- 前記制御手段はさらに、消去動作時に、選択メモリセルのコントロールゲートに第1の消去電圧を印加し、前記導電領域に第2の消去電圧を印加し、前記選択ゲートおよびビット線をフローティング状態にする、請求項14に記載のフラッシュメモリ。
- NOR型のフラッシュメモリの製造方法であって、
基板表面または基板上に導電領域を形成し、
前記導電領域上に第1の絶縁層を介して第1の導電層を形成し、
第1の導電層上に第2の絶縁層を介して第2の導電層を形成し、
第2の導電層上に第3の絶縁層を形成し、
第3の絶縁層から前記導電領域に至る開口を複数形成し、
電荷蓄積用の絶縁層と柱状構造の活性領域とを各開口内に形成し、
第2の導電層をエッチングして隣接する柱状構造間で第2の導電層を分離させる工程を含み、
前記活性領域の一方の端部が前記開口のコンタクトホールを介して前記導電領域に電気的に接続され、前記活性領域の他方の端部がビット線に電気的に接続され、
第1の導電層および第2の導電層の一方は、記憶トランジスタのゲートであり、他方は、選択トランジスタのゲートであり、1つのメモリセルは、1つの記憶トランジスタと1つの選択トランジスタとを含む、製造方法。 - 製造方法はさらに、前記開口の底部の電荷蓄積用の絶縁層をエッチングすることにより前記導電領域を露出させるコンタクトホールを形成する、請求項16に記載の製造方法。
- 前記電荷蓄積用の絶縁層をエッチングするとき、前記電荷蓄積用の絶縁層上には保護膜が形成されている、請求項17に記載の製造方法。
- 製造方法はさらに、前記基板に周辺回路を形成し、
前記基板上に絶縁層を形成し、
前記絶縁層上に前記導電領域を形成する工程を含む、請求項16ないし18いずれか1つに記載の製造方法。
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