JP6576510B1 - メモリデバイス及びそのテスト読書き方法 - Google Patents
メモリデバイス及びそのテスト読書き方法 Download PDFInfo
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- JP6576510B1 JP6576510B1 JP2018100086A JP2018100086A JP6576510B1 JP 6576510 B1 JP6576510 B1 JP 6576510B1 JP 2018100086 A JP2018100086 A JP 2018100086A JP 2018100086 A JP2018100086 A JP 2018100086A JP 6576510 B1 JP6576510 B1 JP 6576510B1
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2018100086A JP6576510B1 (ja) | 2018-05-25 | 2018-05-25 | メモリデバイス及びそのテスト読書き方法 |
TW107118177A TWI658466B (zh) | 2018-05-25 | 2018-05-28 | 記憶裝置及其測試讀寫方法 |
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JP2018100086A JP6576510B1 (ja) | 2018-05-25 | 2018-05-25 | メモリデバイス及びそのテスト読書き方法 |
Publications (2)
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JP6576510B1 true JP6576510B1 (ja) | 2019-09-18 |
JP2019204568A JP2019204568A (ja) | 2019-11-28 |
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JP2018100086A Active JP6576510B1 (ja) | 2018-05-25 | 2018-05-25 | メモリデバイス及びそのテスト読書き方法 |
Country Status (2)
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JP (1) | JP6576510B1 (zh) |
TW (1) | TWI658466B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10566034B1 (en) * | 2018-07-26 | 2020-02-18 | Winbond Electronics Corp. | Memory device with control and test circuit, and method for test reading and writing using bit line precharge voltage levels |
US11100964B1 (en) * | 2020-02-10 | 2021-08-24 | Taiwan Semiconductor Manufacturing Company Limited | Multi-stage bit line pre-charge |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2001057875A1 (fr) * | 2000-02-04 | 2001-08-09 | Hitachi, Ltd. | Dispositif semi-conducteur |
FR2974666B1 (fr) * | 2011-04-26 | 2013-05-17 | Soitec Silicon On Insulator | Amplificateur de detection differentiel sans transistor de precharge dedie |
KR102215359B1 (ko) * | 2014-08-01 | 2021-02-15 | 삼성전자주식회사 | 비휘발성 메모리 장치와 그 센싱 방법 |
KR102432868B1 (ko) * | 2015-07-17 | 2022-08-17 | 에스케이하이닉스 주식회사 | 비트라인 센스앰프 및 이를 이용하는 메모리 장치 |
KR102408572B1 (ko) * | 2015-08-18 | 2022-06-13 | 삼성전자주식회사 | 반도체 메모리 장치 |
KR102514045B1 (ko) * | 2016-04-21 | 2023-03-24 | 삼성전자주식회사 | 저항성 메모리 장치 및 이를 포함하는 메모리 시스템 |
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2018
- 2018-05-25 JP JP2018100086A patent/JP6576510B1/ja active Active
- 2018-05-28 TW TW107118177A patent/TWI658466B/zh active
Also Published As
Publication number | Publication date |
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JP2019204568A (ja) | 2019-11-28 |
TW202004768A (zh) | 2020-01-16 |
TWI658466B (zh) | 2019-05-01 |
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