JP6576510B1 - メモリデバイス及びそのテスト読書き方法 - Google Patents

メモリデバイス及びそのテスト読書き方法 Download PDF

Info

Publication number
JP6576510B1
JP6576510B1 JP2018100086A JP2018100086A JP6576510B1 JP 6576510 B1 JP6576510 B1 JP 6576510B1 JP 2018100086 A JP2018100086 A JP 2018100086A JP 2018100086 A JP2018100086 A JP 2018100086A JP 6576510 B1 JP6576510 B1 JP 6576510B1
Authority
JP
Japan
Prior art keywords
voltage
precharge
test
bit line
enable signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018100086A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019204568A (ja
Inventor
裕司 中岡
裕司 中岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Winbond Electronics Corp
Original Assignee
Winbond Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Winbond Electronics Corp filed Critical Winbond Electronics Corp
Priority to JP2018100086A priority Critical patent/JP6576510B1/ja
Priority to TW107118177A priority patent/TWI658466B/zh
Application granted granted Critical
Publication of JP6576510B1 publication Critical patent/JP6576510B1/ja
Publication of JP2019204568A publication Critical patent/JP2019204568A/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP2018100086A 2018-05-25 2018-05-25 メモリデバイス及びそのテスト読書き方法 Active JP6576510B1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2018100086A JP6576510B1 (ja) 2018-05-25 2018-05-25 メモリデバイス及びそのテスト読書き方法
TW107118177A TWI658466B (zh) 2018-05-25 2018-05-28 記憶裝置及其測試讀寫方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018100086A JP6576510B1 (ja) 2018-05-25 2018-05-25 メモリデバイス及びそのテスト読書き方法

Publications (2)

Publication Number Publication Date
JP6576510B1 true JP6576510B1 (ja) 2019-09-18
JP2019204568A JP2019204568A (ja) 2019-11-28

Family

ID=67347901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018100086A Active JP6576510B1 (ja) 2018-05-25 2018-05-25 メモリデバイス及びそのテスト読書き方法

Country Status (2)

Country Link
JP (1) JP6576510B1 (zh)
TW (1) TWI658466B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10566034B1 (en) * 2018-07-26 2020-02-18 Winbond Electronics Corp. Memory device with control and test circuit, and method for test reading and writing using bit line precharge voltage levels
US11100964B1 (en) * 2020-02-10 2021-08-24 Taiwan Semiconductor Manufacturing Company Limited Multi-stage bit line pre-charge

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001057875A1 (fr) * 2000-02-04 2001-08-09 Hitachi, Ltd. Dispositif semi-conducteur
FR2974666B1 (fr) * 2011-04-26 2013-05-17 Soitec Silicon On Insulator Amplificateur de detection differentiel sans transistor de precharge dedie
KR102215359B1 (ko) * 2014-08-01 2021-02-15 삼성전자주식회사 비휘발성 메모리 장치와 그 센싱 방법
KR102432868B1 (ko) * 2015-07-17 2022-08-17 에스케이하이닉스 주식회사 비트라인 센스앰프 및 이를 이용하는 메모리 장치
KR102408572B1 (ko) * 2015-08-18 2022-06-13 삼성전자주식회사 반도체 메모리 장치
KR102514045B1 (ko) * 2016-04-21 2023-03-24 삼성전자주식회사 저항성 메모리 장치 및 이를 포함하는 메모리 시스템

Also Published As

Publication number Publication date
JP2019204568A (ja) 2019-11-28
TW202004768A (zh) 2020-01-16
TWI658466B (zh) 2019-05-01

Similar Documents

Publication Publication Date Title
CN108766493B (zh) 一种应用于sram的可调节wlud读写辅助电路
US10622085B2 (en) Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor
JP2008521157A (ja) 静的ランダムアクセスメモリ用のワード線ドライバ回路
JP2006338793A (ja) 半導体記憶装置
US10566034B1 (en) Memory device with control and test circuit, and method for test reading and writing using bit line precharge voltage levels
KR100656432B1 (ko) 반도체 메모리의 컬럼 선택신호 제어장치 및 방법
JP2006127728A (ja) 低電圧用半導体メモリ装置
JPH10289586A (ja) メモリ・セルのセンス方法およびビット線等化回路
JP6576510B1 (ja) メモリデバイス及びそのテスト読書き方法
KR102167831B1 (ko) 메모리 디바이스 및 그의 테스트 읽기 쓰기 방법
US9013914B2 (en) Semiconductor memory device and method for controlling semiconductor memory device
KR100383007B1 (ko) 반도체 기억 장치
CN110619903B (zh) 存储装置及其测试读写方法
KR100780633B1 (ko) 반도체 메모리 소자의 오버 드라이버 제어신호 생성회로
JP2011159332A (ja) 半導体記憶装置
JP2010102790A (ja) 半導体装置
US11862233B2 (en) System and method for detecting mismatch of sense amplifier
WO2022104704A1 (zh) 一种存储数据读取电路及存储器
JP5436294B2 (ja) 半導体記憶装置及びその負荷テスト方法
US10916299B2 (en) Semiconductor storage device and operation method thereof
CN114121084B (zh) 存储装置、侦测方法以及装置、存储介质
KR19990016994A (ko) 반도체 메모리장치
JP2008117492A (ja) 半導体装置
JP2011227969A (ja) 半導体集積回路及び不良ビットセル検出方法
JP2003051192A (ja) 半導体記憶装置

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180525

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190409

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190705

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20190723

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20190820

R150 Certificate of patent or registration of utility model

Ref document number: 6576510

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250