WO2022104704A1 - 一种存储数据读取电路及存储器 - Google Patents

一种存储数据读取电路及存储器 Download PDF

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Publication number
WO2022104704A1
WO2022104704A1 PCT/CN2020/130442 CN2020130442W WO2022104704A1 WO 2022104704 A1 WO2022104704 A1 WO 2022104704A1 CN 2020130442 W CN2020130442 W CN 2020130442W WO 2022104704 A1 WO2022104704 A1 WO 2022104704A1
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Prior art keywords
terminal
transistor
output
data reading
voltage
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PCT/CN2020/130442
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English (en)
French (fr)
Inventor
蔡江铮
布明恩
欧阳晟
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华为技术有限公司
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Priority to EP20961995.6A priority Critical patent/EP4231299A4/en
Priority to PCT/CN2020/130442 priority patent/WO2022104704A1/zh
Priority to CN202080103124.6A priority patent/CN115867969A/zh
Publication of WO2022104704A1 publication Critical patent/WO2022104704A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2273—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0061—Timing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0045—Read using current through the cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell

Definitions

  • the present application relates to the technical field of integrated circuits, and in particular, to a storage data reading circuit and a memory.
  • the structure of the storage data reading circuit (usually using a sense amplifier (SA)) in a non-volatile memory (NVM) is shown in FIG. 1, including a first-stage amplifier 10 and a first-stage amplifier 10
  • the second stage amplifier 20 the first stage amplifier 10 includes transistors MP0, MP1, MN0, MN1, MN2 and MN3, wherein MP1, MN1, MN3 are connected in series between the power supply VDD and ground GND in sequence, and MP0, MN0 and MN2 are connected in series with the power supply in sequence Between VDD and ground GND.
  • the control end of MP1 is connected to the control end of MP0, MN0 and MP0 are connected to node F, and the control end of MP0 is connected to node F.
  • Both MN0 and MN1 are switching transistors, the control terminal of MN1 is connected to the control line Ydec, the voltage provided by the control line Ydec is used to control the on and off of MN1, and MN1 is used to control the first input terminal A of the first stage amplifier 10 On and off the first output terminal B; the control terminal of MN0 is connected to the control line Ydummy, the voltage provided by the control line Ydummy is used to control the on and off of MN0, and MN0 is used to control the first stage amplifier 10. The turn-on and turn-off of the second input terminal C to the second output terminal F.
  • the control terminals of MN2 and MN3 are both connected to the bias voltage terminal, and the bias voltage terminal provides a bias voltage Vbais to the control terminals of MN2 and MN3.
  • MN2 is used to adjust the magnitude of the reference current Iref
  • MN3 is used to adjust the magnitude of the current Icell flowing from the first input end A to the first output end B.
  • the first input end A of the first-stage amplifier 10 is connected with the data reading end of the memory cell (memory cell) through the bit line BL, and the memory cell is also connected with the word line WL.
  • the memory cell After the memory cell is gated by the word line WL, the memory cell is The current Icell flowing through the memory cell provided by the data read terminal of the 10000 is input to the first input terminal A of the first-stage amplifier 10, and the first-stage amplifier 10 converts the current Icell input from the first input terminal A into a voltage signal Vcell, and output from the first output terminal B of the first stage amplifier 10, the first stage amplifier 10 also converts the reference current Iref input from the second output terminal C into a voltage signal Vref, and outputs from the second output terminal of the first stage amplifier 10 Terminal F output.
  • the first output terminal B and the second output terminal F of the first-stage amplifier 10 are respectively connected to the two input terminals of the second-stage amplifier 20 .
  • the output voltage of the output terminal E of the second-stage amplifier 20 is a low level (for example, 0)
  • the voltage Vcell of the first output end B of the first stage amplifier 10 is greater than the reference voltage Vref of the second output end F, then the output end of the second stage amplifier 20 If the voltage output by E is a high level (eg, the voltage of the power supply VDD), it can be determined that the data stored in the memory cell is "0".
  • the real read window may be smaller than the ideal read window, if the difference between the voltage Vcell of the first output terminal B and the reference voltage Vref is smaller than the sensitivity of the second-stage amplifier 20, or the memory cell
  • the voltage Vcell of the first output terminal B is less than the reference voltage Vref, and the output terminal E of the second stage amplifier 20 may output an incorrect value; on the other hand, the process deviation will cause the reference voltage Vref to fluctuate.
  • Embodiments of the present application provide a stored data reading circuit and a memory, which can improve the problem of inaccurate data read by the stored data reading circuit.
  • a circuit for reading stored data includes a first current mirror, a first resistor and a voltage amplifier; the input end of the first current mirror is connected to the first data reading end of the storage unit, and the output end of the first current mirror is connected through the first resistor to the ground terminal; the first current mirror is used to amplify the current mirror output from the first data read terminal of the storage unit into the first mirror current, and output the first mirror current to the output terminal of the first current mirror; The first input terminal is connected to the output terminal of the first current mirror, the second input terminal of the voltage amplifier is used for receiving the reference voltage; the output terminal of the voltage amplifier is connected to the output terminal of the storage data reading circuit.
  • the first current mirror Since the first current mirror mirrors and amplifies the current Icell output by the first data read end of the memory cell into the first mirror current IR0, and outputs the first mirror current IR0 to the output end b of the first current mirror, the first current
  • the voltage Vdata at the output end b of the mirror (that is, at the node D) is equal to the product of the first mirror current IR0 and the first resistance, so when the memory cell stores "1" or "0", it can be adjusted by adjusting the voltage of the first mirror current IR0.
  • the size (the size of the first mirror current IR0 can be realized by adjusting the aspect ratio of the transistors in the first current mirror 301) and the size of the first resistor make the voltage Vdata at the node D increase, thereby increasing the memory cell storage "
  • the window between 1" and "0" that is, the difference between the voltage Vdata1 at node D when the memory cell stores "1” and the voltage Vdata0 at node D when the memory cell stores "0" is increased. In this way, even if the window when the memory cell stores "1" and "0" is reduced due to process variation, or the reference voltage Vref fluctuates, the memory cell stores "1" or "0” after passing through the first amplifier.
  • the window has been enlarged, and can be enlarged to the rail-to-rail level, that is, the voltage Vdata at node D can reach the power supply voltage at the maximum, so the voltage amplifier can accurately judge Vdata and the reference voltage Vref, which is conducive to distinguishing Whether the data stored in the memory unit is "0" or "1", thus ensuring that the memory can correctly read the data.
  • the stored data reading circuit further includes a first inverter and a first selector; the input end of the first inverter is connected to the output end of the first current mirror, and the first inverter
  • the output end of the first selector is connected to the first input end of the first selector, the output end of the voltage amplifier is connected to the second input end of the first selector; the output end of the first selector is connected to the output end of the stored data reading circuit;
  • the voltage amplifier is used for inverting the difference between the voltage input at the first input terminal and the voltage input at the second input terminal.
  • the first selector can selectively output a signal output from the output terminal of the first inverter or a signal output from the output terminal of the voltage amplifier.
  • the output end of the first selector can select the signal output by the output end of the fast output voltage amplifier; since the voltage input at the first input end of the voltage amplifier in the first stage and the voltage received at the second input end The difference between the reference voltages may not reach a particularly ideal range, there is a certain probability of misreading, and the threshold voltage of the first inverter is generally large, so in the second stage, the output of the first selector can select the output The signal output at the output of the first inverter; under relatively poor process deviations or in extreme cases, the signal output at the output of the first selector in the second stage may also be wrong, due to the third stage, the window The full amplification has been done, so in the third stage, the output of the first selector can select the signal output
  • the stored data reading circuit further includes a reference current source; the second input terminal of the voltage amplifier is connected to the reference current source, and the reference current source provides a reference voltage.
  • the size of the reference voltage can be adjusted by adjusting the size of the reference current source.
  • the structure of the storage data reading circuit can be simplified.
  • the stored data reading circuit further includes a reference current generating circuit; the second input end of the voltage amplifier is connected to the output end of the reference current generating circuit; the reference current generating circuit includes a second current mirror and a second resistor; the input end of the second current mirror is connected to the second data read end of the parallel first reference memory unit and the second reference memory unit; the output end of the second current mirror is connected to the ground end through the second resistor, and the third The output terminals of the two current mirrors are also connected to the second input terminal of the voltage amplifier; the second current mirror is used to mirror the total current output from the second data read terminal to a second mirror current, and output the second mirror current to The output end of the second current mirror; wherein, the storage states of the first reference storage unit and the second reference storage unit are different.
  • the second input terminal of the voltage amplifier is connected to the output terminal of the reference current generating circuit, in this way, a reference voltage can be provided for the second input terminal of the voltage amplifier through the reference current generating circuit.
  • the reference current generation circuit is connected to the second data read terminals of the first reference memory cell and the second reference memory cell in parallel, the output of the second data read terminals of the first reference memory cell and the second reference memory cell
  • the total current is the sum of the current output by the first reference memory cell and the current output by the second reference memory cell, and the storage states of the first reference memory cell and the second reference memory cell are opposite, so the output terminal of the reference current generation circuit can be guaranteed.
  • the reference voltage is provided as an intermediate value between the voltage when the memory cell stores "1" and the voltage when "0" is stored, which improves the accuracy of the reference voltage and further ensures that the stored data reading circuit can correctly read data.
  • the enable signal terminal of the voltage amplifier is connected to the enable signal control circuit.
  • An enable signal is provided to the enable signal terminal through the enable signal control circuit.
  • the storage data reading circuit further includes a second selector; the enable signal terminal of the voltage amplifier is connected to the output terminal of the second selector, and the enable signal control circuit is connected to the first selector of the second selector.
  • An input terminal is connected, and the output terminal of the reference current generating circuit is connected with the second input terminal of the second selector.
  • the enable signal end of the voltage amplifier is connected to the output end of the second selector, and the second input end of the second selector is connected to the output end of the reference current generating circuit, because the input end of the second current mirror in the reference current generating circuit is connected to the
  • the first reference memory cell and the second reference memory cell connected in parallel have their second data read terminals connected, and the first reference memory cell and the second reference memory cell are known reference cells, so the second output terminal of the voltage amplifier is at It can be judged whether the correct reference voltage is received within the predetermined time, so that the reference current generating circuit can provide the correct reference voltage while providing the signal to the second input terminal of the second selector, and provide the signal to the second input terminal of the second selector.
  • the enable signal terminal of the voltage amplifier is connected to the output end of the second selector, and the second input end of the second selector is connected to the output end of the reference current generating circuit, because the input end of the second current mirror in the reference current generating circuit is connected to the
  • the enable signal terminal of the voltage amplifier provides the enable signal to the voltage amplifier to enable the voltage amplifier.
  • the voltage amplifier is based on the reference voltage input from the first input terminal and the voltage input from the second input terminal.
  • the difference value of the voltage amplifier outputs a signal from the output terminal of the voltage amplifier.
  • the voltage received by the first input terminal of the voltage amplifier is stable, thus improving the stability of the signal output by the output terminal of the voltage amplifier.
  • the stored data reading circuit further includes an error detection circuit, and the control terminal of the first selector is electrically connected to the error detection circuit; the error detection circuit is connected to the output terminal of the first inverter and the output terminal of the voltage amplifier. The output end is connected, and the error detection circuit is used for outputting an error detection signal according to the signal output by the output end of the first inverter and the signal output by the output end of the voltage amplifier; the first selector determines the output of the first selector according to the error detection signal The terminal outputs the signal output from the output terminal of the first inverter or the signal output from the output terminal of the voltage amplifier. In this way, it can be ensured that the output terminal of the first selector accurately outputs a signal.
  • the storage data reading circuit further includes a first switch unit; the input end of the first current mirror is connected to the data read end of the storage unit through the first switch unit.
  • the first switch unit can control the input end of the first current mirror to be turned on or off from the data read end of the memory cell
  • the reference current generating circuit further includes a second switch unit; the input terminal of the second current mirror is connected to the second data read terminal through the second switch unit.
  • the second switch unit can control the input terminal of the second current mirror to be turned on or off from the second data read terminal
  • the first current mirror includes a first transistor and a second transistor; the first end of the first transistor and the first end of the second transistor are both connected to the first voltage end, and the first end of the first transistor is connected to the first voltage end.
  • the two terminals are connected to the first data reading terminal, the second terminal of the second transistor is connected to the first resistor; the control terminal of the first transistor is connected to the control terminal of the second transistor, and the control terminal of the first transistor is connected to the first transistor the second end of the connection.
  • the first switch unit includes a third transistor; the control end of the third transistor is connected to the first control line, the first end is connected to the input end of the first current mirror, and the second end is connected to the first control line. Data read end connection.
  • the first resistor includes a fourth transistor, the control terminal of the fourth transistor is connected to the first terminal, the second terminal of the fourth transistor is grounded, and the first terminal of the fourth transistor is connected to the first current mirror output connection.
  • the second current mirror includes a fifth transistor and a sixth transistor; the first terminal of the fifth transistor and the first terminal of the sixth transistor are both connected to the second voltage terminal, and the first terminal of the fifth transistor is connected to the second voltage terminal.
  • the two terminals are connected to the second data reading terminal, the second terminal of the sixth transistor is connected to the second input terminal of the voltage amplifier; the control terminal of the fifth transistor is connected to the control terminal of the sixth transistor, and the control terminal of the fifth transistor connected to the second terminal of the fifth transistor.
  • the second switch unit includes a seventh transistor; the control end of the seventh transistor is connected to the second control line, the first end is connected to the input end of the second current mirror, and the second end is connected to the second control line. Data read end connection.
  • the second resistor includes an eighth transistor, the control terminal of the eighth transistor is connected to the first terminal, the second terminal of the eighth transistor is grounded, and the first terminal of the eighth transistor is connected to the first terminal of the voltage amplifier. Two input terminals are connected.
  • a circuit for reading stored data includes a first current mirror, a first resistor and a first inverter; the input end of the first current mirror is connected with the first data reading end of the storage unit, and the output end of the first current mirror passes through the A resistor is connected to the ground terminal; the first current mirror is used to amplify the current mirror output from the first data read terminal of the storage unit into the first mirror current, and output the first mirror current to the output terminal of the first current mirror; The input end of the first inverter is connected to the output end of the first current mirror; the output end of the first inverter is connected to the output end of the storage data reading circuit.
  • the voltage Vdata at the node D is equal to the product of the first mirror current IR0 and the first resistance, so when the memory cell stores "1" or "0", the first mirror current IR0 and the first resistance can be adjusted so that the node D
  • the voltage Vdata at the node D increases, thereby increasing the window when the memory cell stores "1" and "0", that is, the voltage Vdata1 at node D when the memory cell stores "1” and the memory cell when the memory cell stores "0" is increased.
  • the first inverter when the voltage Vdata of the output terminal of the first current mirror is greater than the threshold voltage of the first inverter, the output voltage of the output terminal of the first inverter is a low level; When the voltage Vdata of the output terminal of the current mirror is smaller than the threshold voltage of the first inverter, the output voltage of the output terminal of the first inverter is a high level, so the first inverter can accurately judge the Vdata, which is conducive to distinguishing Whether the data stored in the memory unit is "0" or "1", thus ensuring that the memory can correctly read the data.
  • the storage data reading circuit further includes a first switch unit; the input end of the first current mirror is connected to the data read end of the storage unit through the first switch unit.
  • the first switch unit can control the input end of the first current mirror to be turned on or off from the data read end of the memory cell
  • the first current mirror includes a first transistor and a second transistor; the first end of the first transistor and the first end of the second transistor are both connected to the first voltage end, and the first end of the first transistor is connected to the first voltage end.
  • the two terminals are connected to the first data reading terminal, the second terminal of the second transistor is connected to the first resistor; the control terminal of the first transistor is connected to the control terminal of the second transistor, and the control terminal of the first transistor is connected to the first transistor the second end of the connection.
  • the first switch unit includes a third transistor; the control end of the third transistor is connected to the first control line, the first end is connected to the input end of the first current mirror, and the second end is connected to the first control line. Data read end connection.
  • the first resistor includes a fourth transistor, the control terminal of the fourth transistor is connected to the first terminal, the second terminal of the fourth transistor is grounded, and the first terminal of the fourth transistor is connected to the first current mirror output connection.
  • a memory is provided.
  • the memory includes a plurality of memory cells distributed in an array and at least one of the above-mentioned storage data reading circuits. The memory has the same technical effects as the foregoing embodiments, which are not repeated here.
  • a method for controlling a storage data reading circuit includes: in the first stage, the first switch unit is in an on state, after the memory unit is gated by the word line, the first data read end of the memory unit outputs a current to the input end of the first current mirror, and the first current
  • the mirror amplifies the current mirror output from the first data read terminal of the storage unit into a first mirror current, and outputs the first mirror current to the output terminal of the first current mirror;
  • the voltage amplifier is based on the input value of the first input terminal of the voltage amplifier.
  • the voltage and the reference voltage received by the second input terminal output a signal to the output terminal of the voltage amplifier.
  • the storage data reading circuit further includes a first inverter and a first selector; in the first stage, the first selector outputs the signal output by the voltage amplifier; after the first stage, the above-mentioned
  • the control method further includes: in the second stage, the voltage amplifier is not enabled; if the signal output by the first inverter is the same as the signal output by the first selector in the first stage, the first selector keeps outputting the output of the voltage amplifier in the first stage If the signal output by the first inverter is different from the signal output by the first selector in the first stage, the first selector is controlled to select and output the signal output by the first inverter.
  • the output terminal of the first selector quickly outputs a signal in a very short period of time.
  • the difference between the voltage input at the first input terminal of the voltage amplifier and the reference voltage input at the second input terminal may not be To achieve a particularly ideal range, there is a certain probability of misreading.
  • the threshold voltage of the first inverter is generally larger.
  • the reading time of the second stage is later than the reading time of the first stage, so the signal output by the first inverter is highly likely to be accurate , so in the second stage, when the signal output by the first inverter is different from the signal output by the voltage amplifier in the first stage, the signal output by the output terminal of the first selector selects the signal output by the first inverter.
  • the above control method further includes: in the third stage, the enable signal terminal of the voltage amplifier provides an enable signal to the voltage amplifier to enable the voltage amplifier; if the signal output by the voltage amplifier If the signal output by the first selector in the second stage is the same as the signal output by the first selector in the second stage, the first selector keeps outputting the signal output by the first selector in the second stage; if the signal output by the voltage amplifier is different from the signal output by the first selector in the second stage , the first selector is controlled to select the signal output by the output voltage amplifier.
  • the signal output at the output of the first selector of the second stage may also be erroneous under relatively severe process deviations or in extreme cases. Since the window has been fully amplified in the third stage, the voltage amplifier can perform correct amplification even under relatively severe process deviations or in extreme cases, ensuring the correctness of the output signal at the output of the voltage amplifier.
  • FIG. 1 is a schematic structural diagram of a storage data reading circuit provided by the prior art
  • Fig. 2 is the contrast schematic diagram of a kind of real reading window and ideal reading window that the prior art provides;
  • FIG. 3 is a schematic structural diagram of a memory according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a storage data reading circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a storage data reading circuit according to another embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a storage data reading circuit according to another embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a storage data reading circuit according to yet another embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a storage data reading circuit provided by another embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a storage data reading circuit provided by another embodiment of the present application.
  • FIG. 10 is a timing chart for driving each control signal of the stored data read circuit shown in FIG. 9;
  • FIG. 11 is a waveform diagram of several control signals in a stored data reading circuit provided by an embodiment of the application.
  • FIG. 13 is a waveform diagram of several control signals in a stored data reading circuit provided by another embodiment of the application.
  • FIG. 14 is a waveform diagram of several control signals in a stored data reading circuit according to yet another embodiment of the present application.
  • 01-stored data reading circuit 10-first stage amplifier; 20-second stage amplifier; 30-first amplifier; 40-voltage amplifier; 50-reference current generation circuit; 60-first selector; 70-make 80-second selector; 90-error detection circuit; 301-first current mirror; 302-first switch unit; 303-first resistor; 501-second current mirror; 502-second switch unit; 503 - the second resistor.
  • first”, second, etc. are only used for convenience of description, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as “first”, “second”, etc., may expressly or implicitly include one or more of that feature.
  • electrical connection may be a direct electrical connection or an indirect electrical connection through an intermediate medium.
  • Memory is an important part of the integrated circuit industry and is widely used in key fields such as computing, communications, and defense. Designing highly reliable, high-performance, large-capacity and low-cost memories has become the goal pursued by the integrated circuit industry. Among them, the high reliability of the memory is one of the most basic and critical indicators. Only when the data is stored and read correctly can the normal operation of the entire system be guaranteed.
  • An embodiment of the present application provides a memory.
  • the structure of the memory is shown in FIG. 3 and includes a memory cell array, a row decoding circuit, a column decoding circuit, a global clock/sequence control circuit, a read and write control circuit, an input and output drive circuit, and At least one stored data read circuit.
  • the memory cell array includes a plurality of memory cells distributed in the array.
  • the global clock/sequence control circuit is respectively connected with the row decoding circuit, the column decoding circuit, the memory cell array, the read and write control circuit and the input and output driving circuit, and is used for timing control.
  • the row decoding circuit is connected to the memory cell array, and the memory cells of the corresponding row are gated according to the row address to select the memory cells of the corresponding row.
  • the column decoding circuit is connected to the memory cell array. After the strobe, the column decoding circuit selects the memory cells of the corresponding column according to the column address, so as to select the memory cells to be read or written.
  • the read-write control circuit is connected with the memory cell array, and is used for controlling the read operation or the write operation to the memory cell array.
  • the sensitive storage data reading circuit is a data reading module, which is used for data reading.
  • the input and output driving circuits are respectively connected with the sensitive memory data reading circuit and the memory cell array for performing corresponding input or output processing.
  • the memory includes m stored data read circuits, one stored data read circuit connected to n memory cells.
  • m, n are both positive integers, m ⁇ 2, n ⁇ 2.
  • an embodiment of the present application further provides a circuit for reading stored data, which can be applied to the above-mentioned memory.
  • the above-mentioned stored data reading circuit 01 includes a first current mirror 301 , a first resistor 303 and a voltage amplifier 40 .
  • the first current mirror 301 and the first resistor 303 constitute the first amplifier 30 .
  • the input terminal a of the first current mirror 301 is connected to the first data reading terminal p of the memory cell, and the output terminal b of the first current mirror 301 is connected to the ground terminal GND through the first resistor 303; the first current mirror 301 is also connected to the power supply A voltage (eg, the first voltage terminal VDD1 ) is connected.
  • the memory cells are connected to word lines WL, bit lines BL, and source lines SL.
  • the source line SL may be connected to the third voltage terminal VSS1, or may be connected to the ground terminal.
  • the first data read terminal p of the memory cell After the memory cell is gated by the word line WL, the first data read terminal p of the memory cell outputs the current Icell to the input terminal a of the first current mirror 301; the first current mirror 301 is used to read the first data of the memory cell
  • the current Icell output by the terminal p is mirror-amplified into the first mirror current IR0 , and the first mirror current IR0 is output to the output terminal b of the first current mirror 301 .
  • the voltage amplifier 40 may be a sense amplifier.
  • the first current mirror 301 mirrors and amplifies the current Icell output by the first data read terminal p of the memory cell into the first mirror current IR0.
  • the magnification of the mirror image is related to the structure of the first current mirror 301, and can be adjusted by adjusting the first mirror current IR0.
  • the structure of a current mirror 301 is used to adjust the magnification of the mirror image of the first current mirror 301 , that is, to adjust the magnitude of the first mirror current IR0 .
  • the first current mirror 301 includes a transistor
  • the mirror magnification of the first current mirror 301 can be adjusted by adjusting the width to length ratio of the transistor, that is, the magnitude of the first mirror current IR0 can be adjusted.
  • the first input terminal c of the voltage amplifier 40 is connected to the output terminal b of the first current mirror 301, the second input terminal d of the voltage amplifier 40 is used for receiving and the reference voltage Vref; the output terminal e of the voltage amplifier 40 is connected to the storage data read Take the output of circuit 01.
  • the first input terminal c of the voltage amplifier 40 is connected to the output terminal b of the first current mirror 301 , the first input terminal c of the voltage amplifier 40 receives the voltage Vdata at the node data(D), and the voltage of the voltage amplifier 40
  • the second input terminal d receives the reference voltage Vref. Based on this, in some embodiments, when Vdata is greater than Vref, the voltage output by the output terminal e of the voltage amplifier 40 is a high level, such as the voltage VDD1 of the first voltage terminal; when Vdata is less than Vref, the output of the voltage amplifier 40 The voltage output by the terminal e is a low level such as 0.
  • the voltage amplifier 40 when the voltage amplifier 40 includes an inverter, or the voltage amplifier 40 is an amplifier with a special structure (for example, the voltage amplifier 40 is a differential amplifier), in other embodiments, when Vdata is greater than Vref, the output of the voltage amplifier 40 The voltage output by the terminal e is a low level such as 0; when Vdata is less than Vref, the voltage output by the output terminal e of the voltage amplifier 40 is a high level such as the voltage VDD1 of the first voltage terminal.
  • the voltage Vdata at the node D is equal to the product of the first mirror current IR0 and the first resistor 303 .
  • Vdata can be adjusted by adjusting the magnitude of the first mirror current IR0 and the magnitude of the first resistor 303 . That is to say, the first mirror current IR0 output by the first current mirror 301 can be increased, and the first resistance 303 can be increased, so that the voltage Vdata received by the first input terminal c of the voltage amplifier 40 can be significantly increased.
  • the storage data reading circuit 01 includes a first current mirror 301, a first resistor 303 and a voltage amplifier 40.
  • the input terminal a of the first current mirror 301 is connected to the first data reading terminal p of the memory cell
  • the output terminal b of the first current mirror 301 is connected to the ground terminal through the first resistor 303
  • the first input terminal c of the voltage amplifier 40 is connected to the output terminal b of the first current mirror 301
  • the second input terminal d of the voltage amplifier 40 is used for For receiving the reference voltage Vref;
  • the output terminal e of the voltage amplifier 40 is connected to the output terminal of the storage data reading circuit 01 .
  • the voltage Vdata at the output terminal b of the first current mirror 301 (that is, at the node D) is equal to the product of the first mirror current IR0 and the first resistor 303, so when the memory cell stores "1" or "0", it can be adjusted by adjusting the The size of a mirror current IR0 (the size of the first mirror current IR0 can be achieved by adjusting the aspect ratio of the transistors in the first current mirror 301 ) and the size of the first resistor 303, so that the voltage Vdata at the node D increases, thereby increasing
  • the window when the memory cell stores "1" and "0” is enlarged, that is, the difference between the voltage Vdata1 at node D when the memory cell stores "1" and the voltage Vdata0 at node D when
  • the memory cell stores "1" or "0” after passing through the first amplifier 30.
  • the window at 0” has been enlarged, and it can be enlarged to the rail-to-rail level at the maximum, that is, the voltage Vdata at the node D can reach the power supply voltage at the maximum, so the voltage amplifier 40 can compare Vdata and the reference voltage Vref. Accurate judgment is helpful to distinguish whether the data stored in the storage unit is "0" or "1", thereby ensuring that the memory can correctly read the data.
  • the above-mentioned stored data reading circuit 01 (or the first amplifier 30 ) further includes a first switch unit 302 ; the input terminal a of the first current mirror 301 passes through the first switch unit 302 It is connected to the first data read end p of the storage unit.
  • the first switch unit 302 is used to control the input terminal a of the first current mirror 301 to be turned on or off from the data read terminal p of the memory cell.
  • the stored data reading circuit 01 further includes a reference current source Iref; the second input terminal d of the voltage amplifier 40 is connected to the reference current source Iref, and the reference current The source Iref provides the aforementioned reference voltage Vref. The other end of the reference current source Iref is grounded. Since the reference voltage Vref is provided to the second input terminal d of the voltage amplifier 40 through the reference current source Iref, the size of the reference voltage Vref can be adjusted by adjusting the size of the reference current source Iref.
  • the stored data reading circuit 01 further includes a reference current generating circuit 50 ; the second input terminal d of the voltage amplifier 40 is connected to the output terminal f of the reference current generating circuit 50 .
  • the reference current generating circuit 50 includes a second current mirror 501 and a second resistor 503 .
  • the first current mirror 301 , the first switching unit 302 , the first resistor 303 , the second current mirror 501 , the second resistor 503 , and the like constitute the first amplifier 30 .
  • the first amplifier 30 is not shown in FIG. 5 .
  • the input terminal g of the second current mirror 501 is connected to the second data read terminal q of the first reference memory cell and the second reference memory cell connected in parallel; the storage states of the first reference memory cell and the second reference memory cell are different.
  • the output terminal f of the second current mirror 501 is connected to the ground terminal through the second resistor 503, and the output terminal f of the second current mirror 501 is also connected to the second input terminal d of the voltage amplifier 40; the first reference storage unit and the second After the reference memory cell is gated by the reference word line WL-ref, the second data read terminal q of the parallel first reference memory cell and the second reference memory cell outputs current to the input terminal g of the second current mirror 501;
  • the current mirror 501 is used to mirror and amplify the total current Irefcell output by the second data reading terminal q into the second mirror current IR1, and output the second mirror current IR1 to the output terminal f of the second current mirror 501; the second current mirror 501 is also connected to a power supply voltage
  • first voltage terminal VDD1 and the second voltage terminal VDD2 may be the same or different.
  • the second current mirror 501 mirrors and amplifies the total current Irefcell output by the second data read terminal q of the first reference memory cell and the second reference memory cell in parallel to the second mirror current IR1, which is a multiple of the mirror amplification.
  • the magnification of the mirror image of the second current mirror 501 can be adjusted by adjusting the structure of the second current mirror 501 , that is, the magnitude of the second mirror current IR1 can be adjusted.
  • the second current mirror 501 includes a transistor
  • the mirror magnification of the second current mirror 501 can be adjusted by adjusting the width to length ratio of the transistor, that is, the magnitude of the second mirror current IR1 can be adjusted.
  • the received reference voltage Vref is equal to the product of the second mirror current IR1 and the second resistor 503 . Based on this, the reference voltage Vref can be adjusted by adjusting the size of the second mirror current IR1 (the size of the second mirror current IR1 can be realized by adjusting the length ratio of the transistors in the second current mirror 501) and the size of the second resistor 503.
  • the selected reference voltage Vref is an intermediate value between Vdata1 when the memory cell stores "1" and Vdata0 when the memory cell stores "0".
  • the storage states of the first reference storage unit and the second reference storage unit are different.
  • the first reference storage unit may store “1” and the second reference storage unit may store “0"; it may also be that the first reference storage unit stores “1". 0", the second reference storage unit stores "1".
  • the parallel first reference memory cell and the second reference memory cell are connected to the reference word line WL-ref, the reference bit line BL-ref and the reference source line SL-ref.
  • the reference source line SL may be connected to the fourth voltage terminal VSS2, or may be grounded.
  • the third voltage terminal VSS1 and the fourth voltage terminal VSS2 may be the same or different.
  • the first reference memory cell and the second reference memory cell may be reference cells in the memory cell array of the memory for performing read operations and write operations, for example, when the word line selects any one of the memory cell arrays A storage unit, when a read operation is performed on the storage unit, the two storage units in the storage unit array that have not been read can be used as the first reference storage unit and the second reference storage unit, and the storage units of these two storage units Status is different.
  • the reference word line WL-ref is the word line WL in the memory cell array
  • the reference bit line BL-ref is the bit line BL in the memory cell array
  • the reference source line SL-ref is the memory cell array. source line SL.
  • first reference memory cell and the second reference memory cell may also be separately produced independently of the memory cell array.
  • the reference word line WL-ref, the reference bit line BL-ref and the reference source line SL-ref can also be fabricated separately.
  • the above-mentioned reference current generation circuit 50 further includes a second switch unit 502 ; the input terminal g of the second current mirror 501 passes through the second switch unit 502 and the second data read terminal q connect.
  • the second switch unit 502 is used to control the conduction or disconnection of the input terminal g of the second current mirror 501 and the second data read terminal q.
  • the second input terminal d of the voltage amplifier 40 is connected to the output terminal f of the reference current generating circuit 50 , and the reference current generating circuit 50 provides the second input terminal d of the voltage amplifier 40 with the reference voltage Vref.
  • the output terminal f provides the reference voltage Vref, which is the intermediate value of the voltage when the memory cell stores "1" and the voltage when "0" is stored, which improves the accuracy of the reference voltage Vref and further ensures that the stored data reading circuit 01 can correctly read out data.
  • the first current mirror 301 includes a first transistor MP0 and a second transistor MP1 .
  • the first terminal of the first transistor MP0 and the first terminal of the second transistor MP1 are both connected to the first voltage terminal VDD1, the second terminal of the first transistor MP0 is connected to the first data reading terminal p, and the second terminal of the second transistor MP1 is connected to the first voltage terminal VDD1.
  • the two terminals are connected to the first resistor 303; the control terminal of the first transistor MP0 is connected to the control terminal of the second transistor MP1, and the control terminal of the first transistor MP0 is connected to the second terminal of the first transistor MP0.
  • the mirror magnification of the first current mirror 301 can be adjusted by adjusting the width to length ratio of the first transistor MP0 and the second transistor MP1.
  • the first switch unit 302 includes a third transistor MN0 ; the control terminal of the third transistor MN0 is connected to the first control line Ysel1 , and the first terminal is connected to the input terminal of the first current mirror 301 a is connected (ie, connected to the second terminal of the first transistor MP0), and the second terminal is connected to the first data read terminal p of the memory cell.
  • the first control line Ysel1 is used to control whether the third transistor MN0 is gated or not.
  • the above-mentioned first resistor 303 is a variable resistor (also referred to as a potentiometer).
  • the first resistor 303 includes a fourth transistor MN1, the control terminal of the fourth transistor MN1 is connected to the first terminal, the second terminal of the fourth transistor MN1 is grounded, and the fourth transistor MN1 The first terminal of is connected to the output terminal b of the first current mirror 301 (ie, connected to the second terminal of the second transistor MP1).
  • the size of the first resistor 303 can be adjusted by adjusting the size of the fourth transistor MN1 (eg, the aspect ratio).
  • the second current mirror 501 includes a fifth transistor MP4 and a sixth transistor MP3; the first terminal of the fifth transistor MP4 and the first terminal of the sixth transistor MP3 are both connected to the second voltage
  • the terminal VDD2 is connected
  • the second terminal of the fifth transistor MP4 is connected to the second data reading terminal q
  • the second terminal of the sixth transistor MP3 is connected to the second input terminal d of the voltage amplifier 40
  • the control terminal of the fifth transistor MP4 and The control terminal of the sixth transistor MP3 is connected
  • the control terminal of the fifth transistor MP4 is connected to the second terminal of the fifth transistor MP4.
  • the mirror magnification of the second current mirror 501 can be adjusted by adjusting the dimensions (eg, the aspect ratio) of the fifth transistor MP4 and the sixth transistor MP3.
  • the second switch unit 502 includes a seventh transistor MN2 ; the control terminal of the seventh transistor MN2 is connected to the second control line Ysel2 , and the first terminal is connected to the input terminal of the second current mirror 501 g is connected (ie, connected to the second terminal of the fifth transistor MP4), and the second terminal is connected to the second data reading terminal q.
  • the second control line Ysel2 is used to control the gating of the seventh transistor MN2.
  • first control line Ysel1 and the second control line Ysel2 may be the same or different.
  • the above-mentioned second resistor 503 is a variable resistor.
  • the second resistor 503 includes an eighth transistor MN3, the control terminal of the eighth transistor MN3 is connected to the first terminal, the second terminal of the eighth transistor MN3 is grounded, and the eighth transistor MN3 The first terminal of is connected to the second input terminal d of the voltage amplifier 40 (ie, to the second terminal of the sixth transistor MP3).
  • the size of the second resistor 503 can be adjusted by adjusting the size (eg, the aspect ratio) of the eighth transistor MN3.
  • first transistor MP0, second transistor MP1, third transistor MN0, fourth transistor MN1, fifth transistor MP4, sixth transistor MP3, seventh transistor MN2 and eighth transistor MN3 can be It is a P-type transistor or an N-type transistor.
  • the types of the first transistor MP0, the second transistor MP1, the third transistor MN0, the fourth transistor MN1, the fifth transistor MP4, the sixth transistor MP3, the seventh transistor MN2 and the eighth transistor MN3 may or may not be the same.
  • the first transistor MP0, the second transistor MP1, the fifth transistor MP4 and the sixth transistor MP3 are P-type transistors
  • the third transistor MN0, the fourth transistor MN1, the seventh transistor MN2 and the eighth transistor MN3 are N-type transistor.
  • an embodiment of the present application further provides a control method for a stored data reading circuit, which is used to control the storage data reading circuit provided by the first embodiment.
  • the control method of the stored data reading circuit includes:
  • the first switch unit 302 is in the on state, after the memory cell is gated by the word line WL, the first data read terminal p of the memory cell outputs the current Icell to the input terminal a of the first current mirror 301, and the first current mirror 301 Mirror amplifies the current Icell output by the first data read terminal p of the memory cell into a first mirror current IR0, and outputs the first mirror current IR0 to the output terminal b of the first current mirror, the first input of the voltage amplifier 40
  • the terminal c is connected to the output terminal b of the first current mirror 301; the voltage amplifier 40 sends the output terminal of the voltage amplifier 40 to the output terminal of the voltage amplifier 40 according to the voltage Vdata input by the first input terminal c of the voltage amplifier 40 and the reference voltage Vref received by the second input terminal d. output signal.
  • the voltage output by the output terminal e of the voltage amplifier 40 is a high level, such as the voltage VDD1 of the first voltage terminal; when Vdata is less than Vref, then the voltage amplifier 40 The output voltage of the output terminal e is a low level such as 0.
  • the voltage amplifier 40 when the voltage amplifier 40 includes an inverter, or the voltage amplifier 40 is an amplifier with a special structure (for example, the voltage amplifier 40 is a differential amplifier), in other embodiments, when Vdata is greater than Vref, the output of the voltage amplifier 40 The voltage output by the terminal e is a low level such as 0; when Vdata is less than Vref, the voltage output by the output terminal e of the voltage amplifier 40 is a high level such as the voltage VDD1 of the first voltage terminal.
  • the above-mentioned storage data reading circuit 01 includes a first current mirror 301 , a first resistor 303 and a first inverter inverter0 (inv0).
  • the input terminal a of the first current mirror 301 is connected to the first data reading terminal p of the memory cell, and the output terminal b of the first current mirror 301 is connected to the ground terminal through the first resistor 303; the first current mirror 301 is also connected to the power supply voltage (eg, the first voltage terminal VDD1) is connected.
  • the memory cells are connected to word lines WL, bit lines BL, and source lines SL.
  • the source line SL may be connected to the third voltage terminal VSS1, or may be grounded.
  • the first data read terminal p of the memory cell After the memory cell is gated by the word line WL, the first data read terminal p of the memory cell outputs the current Icell to the input terminal a of the first current mirror 301; the first current mirror 301 is used to read the first data of the memory cell
  • the current Icell output by the terminal p is mirror-amplified into the first mirror current IR0 , and the first mirror current IR0 is output to the output terminal b of the first current mirror 301 .
  • the input terminal h of the first inverter inv0 is connected to the output terminal b of the first current mirror 301 ; the output terminal i of the first inverter inv0 is connected to the output terminal of the stored data reading circuit 01 .
  • the voltage Vdata at the output terminal b of the first current mirror 301 (that is, at the node D) is greater than the threshold voltage of the first inverter inv0, the voltage output by the output terminal i of the first inverter inv0 is low
  • the level is 0, for example; when the voltage Vdata of the output terminal b of the first current mirror 301 is smaller than the threshold voltage of the first inverter inv0, the output voltage of the output terminal i of the first inverter inv0 is a high level, such as the first The voltage of the voltage terminal VDD1.
  • the first current mirror 301 since the first current mirror 301 mirrors and amplifies the current Icell output by the first data read terminal p of the memory cell into the first mirror current IR0, and outputs the first mirror current IR0 to the first current mirror 301 , and the voltage Vdata at the output b of the first current mirror 301 (that is, at the node D) is equal to the product of the first mirror current IR0 and the first resistor 303, so when the memory cell stores "1" or "0” , by adjusting the size of the first mirror current IR0 (the size of the first mirror current IR0 can be achieved by adjusting the aspect ratio of the transistors in the first current mirror 301 ) and the size of the first resistor 303 , so that the voltage at the node D Vdata increases, thereby increasing the window when the memory cell stores "1" and "0", that is, increasing the voltage Vdata1 at node D when the memory cell stores "1" and the voltage Vdata1 at node D when the memory cell stores "0
  • the window when the memory cell stores "1" and "0" is reduced due to process variation, or the reference voltage Vref fluctuates, the window when the memory cell stores "1" or "0” has already been reduced.
  • the first inverter inv0 when the voltage Vdata of the output terminal b of the first current mirror 301 is greater than the threshold voltage of the first inverter inv0, the output voltage of the output terminal i of the first inverter inv0 is low level; when the voltage Vdata of the output terminal b of the first current mirror 301 is less than the threshold voltage of the first inverter inv0, the output terminal i of the first inverter inv0 outputs a high level voltage, so the first The inverter inv0 can accurately judge the Vdata, which is beneficial to distinguish whether the data stored in the storage unit is "0" or "1", thereby ensuring that the memory can correctly read the data.
  • the above-mentioned storage data reading circuit 01 further includes a first switching unit 302 ; the input terminal a of the first current mirror 301 passes through the first switching unit 302 and the data reading terminal of the storage unit. p connection.
  • the first switch unit 302 is used to control the input terminal a of the first current mirror 301 to be turned on or off from the data read terminal p of the memory cell.
  • an embodiment of the present application further provides a control method for the stored data reading circuit, which is used to control the stored data provided in the second embodiment above.
  • the control method of the stored data reading circuit includes:
  • the first switch unit 302 is in the on state, after the memory cell is gated by the word line WL, the first data read terminal p of the memory cell outputs the current Icell to the input terminal a of the first current mirror 301, and the first current mirror 301 Mirror amplifies the current Icell output by the memory cell into a first mirror current IR0, and outputs the first mirror current IR0 to the output terminal b of the first current mirror, the input terminal h of the first inverter inv0 and the first current mirror.
  • the output terminal b of 301 is connected; the first inverter inv0 outputs a signal to the output terminal i of the first inverter inv0 according to the voltage input by the input terminal h of the first inverter inv0.
  • the first inverter inv0 outputs a signal to the output terminal i of the first inverter inv0 according to the voltage input from the input terminal h of the first inverter inv0 .
  • the above description please refer to the above description, which will not be repeated here.
  • the above-mentioned stored data reading circuit 01 includes a first current mirror 301 , a first resistor 303 , a voltage amplifier 40 , a first inverter inv0 and a first multiplexer (MUX) 60 .
  • the input terminal a of the first current mirror 301 is connected to the first data reading terminal p of the memory cell, and the output terminal b of the first current mirror 301 is connected to the ground terminal through the first resistor 303; the first current mirror 301 is also connected to the power supply voltage (eg, the first voltage terminal VDD1) is connected.
  • the memory cells are connected to word lines WL, bit lines BL, and source lines SL.
  • the source line SL may be connected to the third voltage terminal VSS1, or may be grounded.
  • the first data read terminal p of the memory cell After the memory cell is gated by the word line WL, the first data read terminal p of the memory cell outputs the current Icell to the input terminal a of the first current mirror 301; the first current mirror 301 is used to read the first data of the memory cell
  • the current Icell output by the terminal p is mirror-amplified into the first mirror current IR0 , and the first mirror current IR0 is output to the output terminal b of the first current mirror 301 .
  • the first input terminal c of the voltage amplifier 40 is connected to the output terminal b of the first current mirror 301 , and the second input terminal d of the voltage amplifier 40 is used for receiving the reference voltage Vref.
  • the voltage amplifier 40 is used for inverting and outputting the difference between the voltage Vdata input at the first input terminal c and the voltage Vref input at the second input terminal d, that is, the voltage amplifier 40 is used for converting the output terminal b of the first current mirror 301
  • the difference between the output voltage Vdata and the reference voltage Vref received by the second input terminal d of the voltage amplifier 40 is inverted and output.
  • the input terminal h of the first inverter inv0 is connected to the output terminal b of the first current mirror 301; the output terminal i of the first inverter inv0 is connected to the first input terminal of the first selector 60, and the output terminal of the voltage amplifier 40
  • the terminal e is connected to the second input terminal of the first selector 60 ; the output terminal j of the first selector 60 is connected to the output terminal of the storage data reading circuit 01 .
  • the above-mentioned storage data reading circuit 01 further includes a first switching unit 302 ; the input terminal a of the first current mirror 301 passes through the first switching unit 302 and the data reading terminal of the storage unit. p connection.
  • the first switch unit 302 is used to control the input terminal a of the first current mirror 301 to be turned on or off from the data read terminal p of the memory cell. It should be noted that, for the first current mirror 301 , the first switch unit 302 , the first resistor 303 and the first inverter inv0 , reference may be made to the explanations of the above embodiments, and details are not repeated here.
  • the second input terminal d of the voltage amplifier 40 can be connected to the reference current source Iref, and the reference current source Iref provides the second input terminal d of the voltage amplifier 40 with the reference voltage Vref; it can also be connected to the output terminal of the reference current generating circuit 50 f is connected, and the reference voltage Vref is provided to the second input terminal d of the voltage amplifier 40 through the reference current generating circuit 50 .
  • the reference current source Iref and the reference current generating circuit 50 reference may be made to the above-mentioned first embodiment, which will not be repeated here.
  • the voltage amplifier 40 since the voltage amplifier 40 is used to invert and output the difference between the voltage Vdata input at the first input terminal c and the voltage Vref input at the second input terminal d, when Vdata is greater than Vref, the voltage amplifier The voltage output by the output terminal e of the voltage amplifier 40 is a low level such as 0; when Vdata is less than Vref, the voltage output by the output terminal e of the voltage amplifier 40 is a high level such as the voltage VDD1 of the first voltage terminal.
  • the voltage amplifier 40 provided in this embodiment includes an inverter.
  • the voltage amplifier 40 is a special structure amplifier, for example, the voltage amplifier 40 is a differential amplifier.
  • the output terminal j of the first selector 60 selects one of its first input terminal and the second input terminal for output.
  • the stored data reading circuit 01 further includes an error detection circuit 90 ; the control terminal of the first selector 60 is electrically connected to the error detection circuit 90 , and the error detection circuit 90 is inverted to the first
  • the output terminal i of the inverter inv0 is connected to the output terminal e of the voltage amplifier 40, and the error detection circuit 90 is used for the signal Q-first (Q-1st) output by the output terminal i of the first inverter inv0 and the output of the voltage amplifier 40.
  • the signal Q-second (Q-2nd) output from the terminal e outputs an error detection signal error-detect (er-det).
  • the first selector 60 determines, according to the error detection signal er-det, that the signal Q-final (Q-f) output by the output terminal j of the first selector 60 is the signal Q-1st or the voltage output by the output terminal i of the first inverter inv0
  • the output terminal e of the amplifier 40 outputs the signal Q-2nd. Exemplarily, if Q-1st and Q-2nd are the same, the first selector 60 selects to output Q-1st or Q-2nd; if Q-1st and Q-2nd are different, the first selector 60 selects to output Q- 1st.
  • the error detection circuit 90 can be implemented by logic operation gates.
  • the error detection circuit 90 includes an exclusive OR gate, wherein one input terminal of the exclusive OR gate is connected to the output terminal i of the first inverter inv0, and the other input terminal is connected to the output terminal e of the voltage amplifier 40.
  • the exclusive OR gate The output terminal of , is connected to the control terminal of the first selector 60 .
  • the enable signal terminal SAE (sense amplifier enable) of the voltage amplifier 40 is connected to the enable signal control circuit 70 .
  • An enable signal is provided to the enable signal terminal SAE of the voltage amplifier 40 through the enable signal control circuit 70 to enable the voltage amplifier 40 .
  • the stored data reading circuit 01 further includes a second selector 80
  • the enable signal terminal SAE of the voltage amplifier 40 is connected to the output terminal of the second selector 80
  • the enable signal control circuit 70 is connected to the first input terminal m of the second selector 80
  • the output terminal of the reference current generation circuit 50 is connected to the first input terminal m of the second selector 80.
  • the second input terminal n of the second selector 80 is connected.
  • the voltage amplifier 40 compares the voltage input from the first input terminal c and the voltage input from the second input terminal d, and obtains the signal from the voltage amplifier 40.
  • the output terminal e of the voltage amplifier 40 outputs a signal, and the voltage amplifier 40 is active high at this time.
  • the enable signal terminal SAE provides a low-level signal
  • the voltage amplifier 40 compares the voltage input from the first input terminal c and the voltage input from the second input terminal d, and obtains the output from the voltage amplifier 40 .
  • the terminal e outputs a signal, and the voltage amplifier 40 is active low at this time.
  • the output terminal of the reference current generating circuit 50 is connected to the second input terminal n of the second selector 80 through the second inverter1 (inv1).
  • the input terminal of the second inverter inv1 is connected to the output terminal of the reference current generating circuit 50
  • the output terminal of the second inverter inv1 is connected to the second input terminal n of the second selector 80 .
  • the second selector 80 can select the enable signal control circuit 70 to be the enable signal terminal SAE of the voltage amplifier 40
  • the enable signal is provided, and the signal output by the second inverter inv1 may also be selected to provide the enable signal to the enable signal terminal SAE of the voltage amplifier 40 .
  • the voltage at the node D increases gradually, if the first input terminal c of the voltage amplifier 40 obtains the voltage Vdata at the node D too early, the voltage Vdata received by the first input terminal c of the voltage amplifier 40 may be inaccurate , so the value output by the voltage amplifier 40 may be wrong.
  • the enable signal terminal SAE of the voltage amplifier 40 is connected to the output terminal of the second selector 80, and the second input terminal n of the second selector 80 is connected to the output terminal of the reference current generating circuit 50, because The input terminal g of the second current mirror 501 in the reference current generating circuit 50 is connected to the second data reading terminal a of the parallel first reference storage unit and the second reference storage unit, and the first reference storage unit and the second reference storage unit
  • the unit is a known reference unit, so it can be determined whether the second output terminal d of the voltage amplifier 40 receives the correct reference voltage Vref within a predetermined time, so that the reference current generating circuit 50 can provide the correct reference voltage Vref At the same time, the reference voltage Vref provides a signal to the second input terminal n of the second selector 80, and provides the signal to the enable signal terminal SAE of the voltage amplifier 40.
  • the enable signal terminal SAE of the voltage amplifier 40 is only sent to the voltage amplifier.
  • 40 provides an enable signal to enable the voltage amplifier 40, and the voltage amplifier 40 outputs a signal from the output terminal e of the voltage amplifier 40 according to the difference between the reference voltage Vref input from the first input terminal c and the voltage Vdata input from the second input terminal d.
  • the stability of the signal output by the output terminal of the voltage amplifier 40 is improved.
  • the memory cell is further connected to the control terminal of the ninth transistor MP5 , the first terminal of the ninth transistor MP5 is connected to the bit line BL, and the second terminal is connected to the bit line BL through The diode L is connected to the source line SL.
  • the ninth transistor MP5 may be a P-type transistor or an N-type transistor.
  • an embodiment of the present application further provides a control method for the stored data reading circuit 01, which is used to control the storage data reading circuit 01 provided in the third embodiment.
  • the stored data read circuit 01. Referring to the timing diagram shown in FIG.
  • the timing diagram respectively provides the timing curve of the read enable signal REN; the timing curve of the read clock signal CLK; the timing curve of the signal output by the word line WL; the enable signal terminal of the voltage amplifier 40
  • the timing curve of the enable signal output by SAE; the timing curve of the signal Q-1st output by the output terminal i of the first inverter inv0; the timing curve of the signal Q-2nd output by the output terminal e of the voltage amplifier 40; the first selection The timing curve of the signal Q-f output by the output terminal j of the device 60; the timing curve of the error detection signal er-det.
  • control method of the stored data reading circuit 01 includes:
  • the first switch unit 302 is in an on state, and after the memory cell is gated by the word line WL, the first data read terminal p of the memory cell outputs the current Icell to the input terminal a of the first current mirror 301,
  • the first current mirror 301 mirrors and amplifies the current Icell output by the first data read terminal p of the memory cell into the first mirror current IR0, and outputs the first mirror current IR0 to the output terminal b of the first current mirror 301, and the voltage amplifier
  • the first input terminal c of 40 is connected to the output terminal b of the first current mirror 301;
  • the enable signal terminal SAE of the voltage amplifier 40 provides the enable signal to the voltage amplifier 40 to enable the voltage amplifier 40;
  • the voltage Vdata input from the first input terminal c and the reference voltage Vref input from the second input terminal d output signals to the output terminal e of the voltage amplifier 40, and the output terminal j of the first selector 60 selects the output terminal e of the output voltage amplifier 40.
  • the stored data read circuit 01 starts a read operation.
  • the signal provided by the word line WL gates the memory cell to be read, and within a small fixed delay after the rising edge of the read clock signal CLK, the enable signal terminal SAE of the voltage amplifier 40 provides an enable signal, and the voltage amplifier 40 according to the voltage
  • the voltage Vdata input from the first input terminal c of the amplifier 40 and the reference voltage Vref input from the second input terminal d output the signal Q-2nd to the output terminal e of the voltage amplifier 40 .
  • the output terminal j of the first selector 60 selects the signal Q-2nd output by the output terminal e of the output voltage amplifier 40 .
  • an enable signal may be provided to the enable signal terminal SAE of the voltage amplifier 40 through the enable signal control circuit 70 .
  • the output terminal j of the first selector 60 can quickly output the signal Q-f, and at this time Q-f1 is Q-2nd. Since this mode is relatively aggressive, this phase can also be referred to as an aggressive speculative read.
  • the voltage amplifier 40 is not enabled by the enable signal terminal SAE of the voltage amplifier 40 (the voltage amplifier 40 does not output a signal); if the signal Q-1st output by the first inverter inv0 is the same as the first stage
  • the signal Q-2nd output by the selector 60 (the signal output by the first selector 60 in the first stage is the signal Q-2nd output by the voltage amplifier 40) is the same, then the first selector 60 keeps outputting the signal output by the voltage amplifier 40 in the first stage.
  • the first selector 60 can be controlled to select and output the signal Q-1st output by the first inverter inv0 through the error detection signal er-det output by the error detection circuit 90 .
  • the error detection circuit 90 For details of the error detection circuit 90, reference may be made to the above-mentioned embodiments, which will not be repeated here.
  • the output terminal j of the first selector 60 quickly outputs the signal Q-f in a very short period of time.
  • the voltage Vdata input to the first input terminal c of the voltage amplifier 40 and the second input The difference between the reference voltage Vref input from the terminal d may not reach a particularly ideal magnitude.
  • the difference between the voltage Vdata input from the first input terminal c of the voltage amplifier 40 and the reference voltage Vref input from the second input terminal d may be less than Due to the sensitivity of the voltage amplifier 40, under the influence of factors such as process variation, the difference between Vdata and Vref may not be enough to make the voltage amplifier 40 work 100% correctly, and there is a certain probability of misreading.
  • the threshold voltage of the first inverter inv0 is generally larger.
  • the reading time of the second stage is later than the reading time of the first stage, so the signal Q-1st output by the first inverter inv0 The high probability is accurate, so in the second stage, when the signal Q-1st output by the first inverter inv0 is different from the signal Q-2nd output by the voltage amplifier 40 in the first stage, the output terminal of the first selector 60
  • the signal Q-f output by j selects the signal Q-1st output by the first inverter inv0.
  • the voltage output by the output terminal i of the first inverter inv0 is low level;
  • the voltage output by the output terminal i of the first inverter inv0 is a high level. Since the voltage Vdata received by the input terminal h of the first inverter inv0 has been amplified when the memory cell stores "1" and "0", it can be amplified up to the rail-to-rail level, that is, the voltage at the node D.
  • the maximum voltage Vdata can reach the power supply voltage, so the accuracy of the signal Q-1st output by the output terminal i of the first inverter inv0 can be ensured.
  • this phase may also be referred to as a stable speculative read operation.
  • the enable signal terminal SAE of the voltage amplifier 40 provides the enable signal to the voltage amplifier 40 to enable the voltage amplifier 40, and the output terminal e of the voltage amplifier 40 outputs the signal Q-2nd.
  • -2nd is the same as the signal Q-1st output by the first selector 60 in the second stage (the signal output by the first selector 60 in the second stage is the signal Q-1st output by the first inverter inv0), then the first selector 60 keeps outputting the signal Q-1st output by the first selector 60 in the second stage; if the signal Q-2nd output by the voltage amplifier 40 is not the same as the signal Q-1st output by the first selector 60 in the second stage, control the first The selector 60 selects the signal Q-2nd output by the output voltage amplifier 40 .
  • the first switch unit 302 is still in the ON state, and the memory cell is gated by the word line WL.
  • the voltage Vdata input to the first input terminal c of the voltage amplifier 40 has enough time to amplify, and the voltage Vdata input to the first input terminal c and the reference voltage Vref have formed enough The voltage difference, therefore, in the third stage window has been fully amplified.
  • the enable signal provided by the enable signal terminal SAE of the voltage amplifier 40 may be provided by the enable signal control circuit 70 or by the reference current generating circuit 50 .
  • the enable signal provided by the enable signal terminal SAE is provided by the reference current generating circuit 50 , it can further ensure that the window is fully amplified.
  • the signal Q-1st output at the output terminal j of the first selector 60 in the second stage may also be in error under relatively severe process variations or in extreme cases. Since the window has been fully amplified in the third stage, the voltage amplifier 40 can perform correct amplification even under relatively severe process deviations or in extreme cases, ensuring the correctness of the output signal at the output terminal e of the voltage amplifier 40 . Based on this, this stage can also be referred to as a corrective read operation.
  • step S32 is an optional step, for example, it may be omitted in some embodiments.
  • the data read out by the corrective read operation can be used to update the data read out by the stable read operation.
  • the specific process is as follows: the enable signal terminal SAE of the voltage amplifier 40 provides the enable signal to the voltage amplifier 40 to enable the voltage amplifier 40 , and the voltage amplifier 40 compares the voltage Vdata at D with the reference voltage Vref to obtain an output of the voltage amplifier 40 The terminal e outputs the signal Q-2nd. Under the above-mentioned high temperature and high leakage condition, the final signal Q-f output by the first selector 60 is the output signal Q-2nd of the output terminal e of the voltage amplifier 40 . Referring to FIG.
  • the total window processed by the second stage amplifier 20 in FIG. 13 is about 140mV (100mV+40mV), and the minimum window is 40mV.
  • the total window processed by the voltage amplifier 40 is 800mV (460mV+340mV), and the minimum window is 340mV.
  • the waveform diagrams of radical speculative readout, stable speculative readout, and corrective readout are provided.
  • the readout speed of the circuit 01 is used to evaluate the performance of the stored data readout circuit 01.
  • the embodiments of the present application can improve performance through aggressive readout and stable readout. The time required for aggressive speculative readout, stable speculative readout, and corrective readout was tested, as shown in Table 1.
  • the time required for aggressive speculative readout is 36ns
  • the time required for stable speculative readout is 42ns
  • the time required for corrective readout is 62ns.
  • the embodiments of the present application can effectively enlarge the window, and avoid misreading caused by process deviation and characteristics of new memory cells.
  • corrective readout can ensure that the stored data readout circuit 01 can correctly read out data under the condition of process variation.
  • the performance of the stored data read circuit 01 can also be improved through aggressive speculative readout and stable speculative readout.

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Abstract

一种存储数据读取电路及存储器，涉及集成电路技术领域，可以改善存储数据读取电路读取数据不准确的问题。该存储数据读取电路（01）包括第一电流镜（301）、第一电阻（303）和电压放大器（40）；所述第一电流镜（301）的输入端（a）与存储单元的第一数据读取端（p）连接，所述第一电流镜（301）的输出端（b）通过所述第一电阻（303）连接至接地端；所述第一电流镜（301）用于将所述存储单元的第一数据读取端（p）输出的电流镜像放大为第一镜像电流（IRO），并将所述第一镜像电流（IRO）输出至所述第一电流镜（301）的输出端（b）；所述电压放大器（40）的第一输入端（c）与所述第一电流镜（301）的输出端（b）连接，所述电压放大器（40）的第二输入端（d）用于接收参考电压（Iref）；所述电压放大器（40）的输出端（e）连接至所述存储数据读取电路（01）的输出端。

Description

一种存储数据读取电路及存储器 技术领域
本申请涉及集成电路技术领域，尤其涉及一种存储数据读取电路及存储器。
背景技术
目前，非易失性存储器(non-volatile memory，NVM)中的存储数据读取电路(通常采用灵敏放大器(sense amplifier,SA))的结构如图1所示，包括第一级放大器10和第二级放大器20，第一级放大器10包括晶体管MP0、MP1、MN0、MN1、MN2和MN3，其中MP1、MN1、MN3依次串联于电源VDD和地GND之间，MP0、MN0以及MN2依次串联于电源VDD和地GND之间。MP1的控制端与MP0的控制端连接,MN0与MP0连接于节点F，MP0的控制端与节点F连接。MN0和MN1均为开关晶体管，MN1的控制端与控制线Ydec连接，控制线Ydec提供的电压用于控制MN1的导通与断开，MN1用于控制第一级放大器10的第一输入端A到第一输出端B的导通与断开；MN0的控制端与控制线Ydummy连接，控制线Ydummy提供的电压用于控制MN0的导通与断开，MN0用于控制第一级放大器10的第二输入端C到第二输出端F的导通与断开。MN2和MN3的控制端均与偏置电压端连接，偏置电压端向MN2和MN3的控制端提供偏置电压Vbais。MN2用于对参考电流Iref的大小进行调节，MN3用于对从第一输入端A流向第一输出端B的电流Icell的大小进行调节。第一级放大器10的第一输入端A通过位线BL与存储单元(memory cell)的数据读取端连接，存储单元还与字线WL连接，存储单元被字线WL选通后，存储单元的数据读取端提供的流过存储单元的电流Icell输入至第一级放大器10的第一输入端A，第一级放大器10将从第一输入端A输入的电流Icell转化成电压信号Vcell，并从第一级放大器10的第一输出端B输出，第一级放大器10还将从第二输出端C输入的参考电流Iref转化成电压信号Vref，并从第一级放大器10的第二输出端F输出。
第一级放大器10的第一输出端B和第二输出端F分别与第二级放大器20的两个输入端连接。当第一级放大器10的第一输出端B的电压Vcell l小于第二输出端F的参考电压Vref时，则第二级放大器20的输出端E输出的电压为低电平(例如0)，即可判断出存储单元存储的数据是“1”；当第一级放大器10的第一输出端B的电压Vcell大于第二输出端F的参考电压Vref时，则第二级放大器20的输出端E输出的电压为高电平(例如电源VDD的电压)，即可判断出存储单元存储的数据是“0”。
如图2所示，只有当存储单元存“1”和“0”时具有较大的窗口(即存储单元存“1”时第一级放大器10的第一输出端B的电压Vcell 1和存储单元存“0”时第一级放大器10的第一输出端B的电压Vcell 0的差值较大)时，才可能找到中间的参考电压Vref，通过将第一输出端B的电压Vcell与第二输出端F的参考电压Vref比较，分辨出“0”和“1”。然而，由于存在工艺偏差，因此一方面，真实读窗口可能会小于理想读窗口，若第一输出端B的电压Vcell和参考电压Vref的差值小于第二级放大器20的灵敏度，或者，存储单元存“0”时，第一输出端B的电压Vcell小于参考电 压Vref，则第二级放大器20的输出端E输出的值可能有误；另一方面，工艺偏差会导致参考电压Vref有波动，这样一来，第一输出端B的电压Vcell与参考电压Vref比较时，第二级放大器20的输出端E输出的值也可能有误，从而导致对“0”和“1”的分辨变难，进而导致存储器很难读出正确的数据。
发明内容
本申请实施例提供一种存储数据读取电路及存储器，可以改善存储数据读取电路读取数据不准确的问题。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种存储数据读取电路。该存储数据读取电路包括第一电流镜、第一电阻和电压放大器；第一电流镜的输入端与存储单元的第一数据读取端连接，第一电流镜的输出端通过第一电阻连接至接地端；第一电流镜用于将存储单元的第一数据读取端输出的电流镜像放大为第一镜像电流，并将第一镜像电流输出至第一电流镜的输出端；电压放大器的第一输入端与第一电流镜的输出端连接，电压放大器的第二输入端用于接收参考电压；电压放大器的输出端连接至存储数据读取电路的输出端。由于第一电流镜将存储单元的第一数据读取端输出的电流Icell镜像放大为第一镜像电流IR0，并将第一镜像电流IR0输出至第一电流镜的输出端b，而第一电流镜的输出端b(即节点D处)的电压Vdata等于第一镜像电流IR0与第一电阻的乘积，因而当存储单元存储“1”或“0”时，可以通过调整第一镜像电流IR0的大小(第一镜像电流IR0的大小可以通过调整第一电流镜301中晶体管的长宽比实现)与第一电阻的大小，使得节点D处的电压Vdata增大，从而增大了存储单元存储“1”和“0”时的窗口，即增大了存储单元存储“1”时节点D处的电压Vdata1与存储单元存储“0”时节点D处的电压Vdata0的差值。这样一来，即使由于工艺偏差导致存储单元存储“1”和“0”时的窗口减小，或者，参考电压Vref有波动，但是由于经过第一放大器后，存储单元存储“1”或“0”时的窗口已经被放大，最大可以被放大到轨到轨的电平，即节点D处的电压Vdata最大可以达到电源电压，因而电压放大器可以对Vdata和参考电压Vref进行准确判断，有利于分辨出存储单元存储的数据是“0”还是“1”，进而确保了存储器能正确读出数据。
在一种可能的实施方式中，存储数据读取电路还包括第一反相器和第一选择器；第一反相器的输入端与第一电流镜的输出端连接，第一反相器的输出端与第一选择器的第一输入端连接，电压放大器的输出端与第一选择器的第二输入端连接；第一选择器的输出端连接至存储数据读取电路的输出端；电压放大器用于将其第一输入端输入的电压和第二输入端输入的电压的差值进行反相输出。由于存储数据读取电路包括电压放大器、第一反相器和第一选择器，因而第一选择器可以选择输出第一反相器的输出端输出的信号或电压放大器的输出端输出的信号。具体的，在第一阶段，第一选择器的输出端可以选择快速输出电压放大器的输出端输出的信号；由于在第一阶段电压放大器的第一输入端输入的电压和第二输入端接收的参考电压的差值可能并未达到特别理想的幅度，存在一定的误读概率，而第一反相器的阈值电压一般较大，因而在第二阶段，第一选择器的输出端可以选择输出第一反相器的输出端输出的信号；在相对恶劣的工艺偏差下或在极端情况下，在第二阶段第一选择器的输出端输出的信号也可 能会出错，由于第三阶段，窗口已经进行了完全放大，因此在第三阶段，第一选择器的输出端可以选择输出电压放大器的输出端输出的信号。在一种可能的实施方式中，存储数据读取电路还包括参考电流源；电压放大器的第二输入端与参考电流源连接，通过参考电流源提供参考电压。可以通过调整参考电流源的大小来调整参考电压的大小。此外，利用参考电流源为电压放大器的第二输入端提供参考电压，可以简化存储数据读取电路的结构。
在一种可能的实施方式中，存储数据读取电路还包括参考电流产生电路；电压放大器的第二输入端与参考电流产生电路的输出端连接；参考电流产生电路包括第二电流镜和第二电阻；第二电流镜的输入端与并联的第一参考存储单元和第二参考存储单元的第二数据读取端连接；第二电流镜的输出端通过第二电阻连接至接地端，且第二电流镜的输出端还与电压放大器的第二输入端连接；第二电流镜用于将第二数据读取端输出的总电流镜像放大为第二镜像电流，并将第二镜像电流输出至第二电流镜的输出端；其中，第一参考存储单元和第二参考存储单元的存储状态不同。由于电压放大器的第二输入端与参考电流产生电路的输出端连接，这样一来，可以通过参考电流产生电路为电压放大器的第二输入端提供参考电压。此外，由于参考电流产生电路与并联的第一参考存储单元和第二参考存储单元的第二数据读取端连接，第一参考存储单元和第二参考存储单元的第二数据读取端输出的总电流为第一参考存储单元输出的电流和第二参考存储单元输出的电流之和，而第一参考存储单元和第二参考存储单元的存储状态相反，因此可以确保参考电流产生电路的输出端提供参考电压为存储单元存“1”时的电压和“0”时的电压的中间值，提高了参考电压的准确性，进一步确保了存储数据读取电路能够正确读出数据。
在一种可能的实施方式中，电压放大器的使能信号端与使能信号控制电路连接。通过使能信号控制电路给使能信号端提供使能信号。
在一种可能的实施方式中，存储数据读取电路还包括第二选择器；电压放大器的使能信号端与第二选择器的输出端连接，使能信号控制电路与第二选择器的第一输入端连接，参考电流产生电路的输出端与第二选择器的第二输入端连接。电压放大器的使能信号端与第二选择器的输出端，而第二选择器的第二输入端与参考电流产生电路的输出端连接，由于参考电流产生电路中第二电流镜的输入端与并联的第一参考存储单元和第二参考存储单元的第二数据读取端连接，而第一参考存储单元和第二参考存储单元是已知的参考单元，因此电压放大器的第二输出端在预定的时间内是否接收到正确的参考电压是可以判断出来的，这样一来，可以在参考电流产生电路提供正确的参考电压的同时给第二选择器的第二输入端提供信号，并提供给电压放大器的使能信号端，此时，电压放大器的使能信号端才向电压放大器提供使能信号使能电压放大器，电压放大器根据第一输入端输入的参考电压和第二输入端输入的电压的差值从电压放大器的输出端输出信号，这时电压放大器的第一输入端接收的电压是稳定的，因此提高了电压放大器输出端输出的信号的稳定性。
在一种可能的实施方式中，存储数据读取电路还包括错误检测电路，第一选择器的控制端与错误检测电路电连接；错误检测电路与第一反相器的输出端和电压放大器的输出端连接，错误检测电路用于根据第一反相器的输出端输出的信号和电压放大器 的输出端输出的信号输出错误检测信号；第一选择器根据错误检测信号确定第一选择器的输出端输出第一反相器的输出端输出的信号或电压放大器的输出端输出的信号。这样一来，可以确保第一选择器的输出端准确输出信号。
在一种可能的实施方式中，存储数据读取电路还包括第一开关单元；第一电流镜的输入端通过第一开关单元与存储单元的数据读取端连接。第一开关单元可以控制第一电流镜的输入端与存储单元的数据读取端导通或断开
在一种可能的实施方式中，参考电流产生电路还包括第二开关单元；第二电流镜的输入端通过第二开关单元与第二数据读取端连接。第二开关单元可以控制第二电流镜的输入端与第二数据读取端导通或断开
在一种可能的实施方式中，第一电流镜包括第一晶体管和第二晶体管；第一晶体管的第一端和第二晶体管的第一端均与第一电压端连接，第一晶体管的第二端与第一数据读取端连接，第二晶体管的第二端与第一电阻连接；第一晶体管的控制端和第二晶体管的控制端连接，且第一晶体管的控制端与第一晶体管的第二端连接。
在一种可能的实施方式中，第一开关单元包括第三晶体管；第三晶体管的控制端与第一控制线连接，第一端与第一电流镜的输入端连接，第二端与第一数据读取端连接。
在一种可能的实施方式中，第一电阻包括第四晶体管，第四晶体管的控制端与第一端连接，第四晶体管的第二端接地，第四晶体管的第一端与第一电流镜的输出端连接。
在一种可能的实施方式中，第二电流镜包括第五晶体管和第六晶体管；第五晶体管的第一端和第六晶体管的第一端均与第二电压端连接，第五晶体管的第二端与第二数据读取端连接，第六晶体管的第二端与电压放大器的第二输入端连接；第五晶体管的控制端和第六晶体管的控制端连接，且第五晶体管的控制端与第五晶体管的第二端连接。
在一种可能的实施方式中，第二开关单元包括第七晶体管；第七晶体管的控制端与第二控制线连接，第一端与第二电流镜的输入端连接，第二端与第二数据读取端连接。
在一种可能的实施方式中，第二电阻包括第八晶体管，第八晶体管的控制端与第一端连接，第八晶体管的第二端接地，第八晶体管的第一端与电压放大器的第二输入端连接。
第二方面，提供一种存储数据读取电路。该存储数据读取电路包括第一电流镜、第一电阻和第一反相器；第一电流镜的输入端与存储单元的第一数据读取端连接，第一电流镜的输出端通过第一电阻连接至接地端；第一电流镜用于将存储单元的第一数据读取端输出的电流镜像放大为第一镜像电流，并将第一镜像电流输出至第一电流镜的输出端；第一反相器的输入端与第一电流镜的输出端连接；第一反相器的输出端连接至存储数据读取电路的输出端。由于第一电流镜将存储单元输出的电流Icell镜像放大为第一镜像电流IR0，并将第一镜像电流IR0输出至第一电流镜的输出端b，而第一电流镜的输出端b(即节点D处)的电压Vdata等于第一镜像电流IR0与第一电阻的乘积，因而当存储单元存储“1”或“0”时，可以通过调整第一镜像电流IR0与第 一电阻，使得节点D处的电压Vdata增大，从而增大了存储单元存储“1”和“0”时的窗口，即增大了存储单元存储“1”时节点D处的电压Vdata1与存储单元存储“0”时节点D处的电压Vdata0的差值。这样一来，即使由于工艺偏差导致存储单元存储“1”和“0”时的窗口减小，或者，参考电压Vref有波动，但是由于存储单元存储“1”或“0”时的窗口已经被放大，而对于第一反相器，当第一电流镜的输出端的电压Vdata大于第一反相器的阈值电压时，第一反相器的输出端输出的电压为低电平；当第一电流镜的输出端的电压Vdata小于第一反相器的阈值电压时，第一反相器的输出端输出的电压为高电平，因而第一反相器可以对Vdata进行准确判断，有利于分辨出存储单元存储的数据是“0”还是“1”，进而确保了存储器能正确读出数据。
在一种可能的实施方式中，存储数据读取电路还包括第一开关单元；第一电流镜的输入端通过第一开关单元与存储单元的数据读取端连接。第一开关单元可以控制第一电流镜的输入端与存储单元的数据读取端导通或断开
在一种可能的实施方式中，第一电流镜包括第一晶体管和第二晶体管；第一晶体管的第一端和第二晶体管的第一端均与第一电压端连接，第一晶体管的第二端与第一数据读取端连接，第二晶体管的第二端与第一电阻连接；第一晶体管的控制端和第二晶体管的控制端连接，且第一晶体管的控制端与第一晶体管的第二端连接。
在一种可能的实施方式中，第一开关单元包括第三晶体管；第三晶体管的控制端与第一控制线连接，第一端与第一电流镜的输入端连接，第二端与第一数据读取端连接。
在一种可能的实施方式中，第一电阻包括第四晶体管，第四晶体管的控制端与第一端连接，第四晶体管的第二端接地，第四晶体管的第一端与第一电流镜的输出端连接。第三方面，提供一种存储器。该存储器包括阵列分布的多个存储单元以及至少一个上述的存储数据读取电路。该存储器具有与前述实施例相同的技术效果，此处不再赘述。
第四方面，提供一种存储数据读取电路的控制方法。该控制方法包括：第一阶段，第一开关单元处于导通状态，存储单元被字线选通后，存储单元的第一数据读取端向第一电流镜的输入端输出电流，第一电流镜将存储单元的第一数据读取端输出的电流镜像放大为第一镜像电流，并将第一镜像电流输出至第一电流镜的输出端；电压放大器根据电压放大器的第一输入端输入的电压和第二输入端接收的参考电压，向电压放大器的输出端输出信号。该存储数据读取电路的控制方法具有与前述实施例相同的技术效果，此处不再赘述。
在一种可能的实施方式中，存储数据读取电路还包括第一反相器和第一选择器；在第一阶段，第一选择器输出电压放大器输出的信号；在第一阶段之后，上述控制方法还包括：第二阶段，电压放大器未使能；若第一反相器输出的信号与第一阶段第一选择器输出的信号相同，则第一选择器保持输出第一阶段电压放大器输出的信号；若第一反相器输出的信号与第一阶段第一选择器输出的信号不相同，则控制第一选择器选择输出第一反相器输出的信号。由于第一阶段，第一选择器的输出端在很短的时间内快速输出信号，此时，电压放大器的第一输入端输入的电压和第二输入端输入的参考电压的差值可能并未达到特别理想的幅度，存在一定的误读概率。而一方面，第一 反相器的阈值电压一般较大，另一方面，第二阶段读取时间晚于第一阶段读取的时间，因而第一反相器输出的信号大概率是准确的，因此在第二阶段，当第一反相器输出的信号与第一阶段电压放大器输出的信号不相同时，第一选择器的输出端输出的信号选择第一反相器输出的信号。
在一种可能的实施方式中，在第二阶段之后，上述控制方法还包括：第三阶段，电压放大器的使能信号端向电压放大器提供使能信号使能电压放大器；若电压放大器输出的信号与第二阶段第一选择器输出的信号相同，则第一选择器保持输出第二阶段第一选择器输出的信号；若电压放大器输出的信号与第二阶段第一选择器输出的信号不相同，则控制第一选择器选择输出电压放大器输出的信号。在相对恶劣的工艺偏差下或在极端情况下，在第二阶段第一选择器的输出端输出的信号也可能会出错。由于第三阶段，窗口已经进行了完全放大，因此电压放大器即使在相对恶劣的工艺偏差下或在极端情况下也能进行正确的放大，确保了电压放大器的输出端输出信号的正确性。
附图说明
图1为现有技术提供的一种存储数据读取电路的结构示意图；
图2为现有技术提供的一种真实读窗口和理想读窗口的对比示意图；
图3为本申请实施例提供的一种存储器的结构示意图；
图4为本申请实施例提供的一种存储数据读取电路的结构示意图；
图5为本申请的另一实施例提供的一种存储数据读取电路的结构示意图；
图6为本申请的又一实施例提供的一种存储数据读取电路的结构示意图；
图7为本申请的再一实施例提供的一种存储数据读取电路的结构示意图；
图8为本申请的另一实施例提供的一种存储数据读取电路的结构示意图；
图9为本申请的又一实施例提供的一种存储数据读取电路的结构示意图；
图10为用于驱动图9所示的存储数据读取电路的各个控制信号的时序图；
图11为本申请实施例提供的一种存储数据读取电路中几种控制信号的波形图；
图12为本申请的另一实施例提供的一种存储数据读取电路中几种控制信号的波形图；
图13为本申请的又一实施例提供的一种存储数据读取电路中几种控制信号的波形图；
图14为本申请的再一实施例提供的一种存储数据读取电路中几种控制信号的波形图。
附图标记：
01-存储数据读取电路；10-第一级放大器；20-第二级放大器；30-第一放大器；40-电压放大器；50-参考电流产生电路；60-第一选择器；70-使能信号控制电路；80-第二选择器；90-错误检测电路；301-第一电流镜；302-第一开关单元；303-第一电阻；501-第二电流镜；502-第二开关单元；503-第二电阻。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
除非另有定义，否则本文所用的所有科技术语都具有与本领域普通技术人员公知 的含义相同的含义。
以下，术语“第一”、“第二”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。此外，术语“电连接”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
存储器是集成电路产业的重要组成部分，广泛应用于计算、通信和国防等关键领域。设计高可靠、高性能、大容量以及低成本的存储器已成为集成电路产业界追求的目标。其中，存储器高可靠性是最基础也是最关键的指标之一，只有数据正确存储及读出，才能保证整个系统的正常运行。
本申请实施例提供一种存储器，存储器的结构如图3所示，包括存储单元阵列、行译码电路、列译码电路、全局时钟/时序控制电路、读写控制电路、输入输出驱动电路以及至少一个存储数据读取电路。存储单元阵列包括阵列分布的多个存储单元。其中，全局时钟/时序控制电路分别与行译码电路、列译码电路、存储单元阵列、读写控制电路以及输入输出驱动电路连接，用于进行时序控制。行译码电路与存储单元阵列连接，根据行地址对相应行的存储单元进行选通，以对相应行的存储单元进行选址，列译码电路与存储单元阵列连接，在相应行的存储单元选通后，列译码电路根据列地址对相应列的存储单元进行选址，从而选中所要读操作或写操作的存储单元。读写控制电路与存储单元阵列连接，用于控制对存储单元阵列进行读操作或者写操作。灵敏存储数据读取电路是数据读出模块，用于进行数据读出。输入输出驱动电路分别与灵敏存储数据读取电路和存储单元阵列连接，用于执行相应的输入或输出处理。
在一些实施例中，存储器包括m个存储数据读取电路，一个存储数据读取电路与n个存储单元连接。其中，m，n均为正整数，m≥2，n≥2。
随着工艺尺寸缩小以及各类新型存储单元的诞生，工艺偏差以及存储单元的新特性对存储器可靠性所产生的影响越来越大。其中，存储数据读取电路对存储单元新特性以及工艺偏差最为敏感，因此在日益严重的工艺偏差以及新工艺下，保证存储器中的灵敏存储数据读取电路正确工作成为关键问题。基于此，本申请实施例还提供一种存储数据读取电路，该存储数据读取电路可以应用于上述的存储器中。
以下提供三个具体的实施例，对存储数据读取电路的结构进行示例性介绍。
实施例一
如图4所示，上述存储数据读取电路01包括第一电流镜301、第一电阻303和电压放大器40。其中，第一电流镜301和第一电阻303等构成第一放大器30。
第一电流镜301的输入端a与存储单元的第一数据读取端p连接，第一电流镜301的输出端b通过第一电阻303连接至接地端GND；第一电流镜301还与电源电压(例如第一电压端VDD1)连接。存储单元与字线WL、位线BL以及源极线SL连接。此处，源极线SL可以与第三电压端VSS1连接，也可以连接至接地端。存储单元被字线WL 选通后，存储单元的第一数据读取端p向第一电流镜301的输入端a输出电流Icell；第一电流镜301用于将存储单元的第一数据读取端p输出的电流Icell镜像放大为第一镜像电流IR0，并将第一镜像电流IR0输出至第一电流镜301的输出端b。
需要说明的是，在本申请的一些实施例中，电压放大器40可以是灵敏放大器。
此处，第一电流镜301将存储单元的第一数据读取端p输出的电流Icell镜像放大为第一镜像电流IR0，镜像放大的倍数与第一电流镜301的结构有关，可以通过调整第一电流镜301的结构来调整第一电流镜301镜像放大的倍数，即，调整第一镜像电流IR0的大小。具体的，在第一电流镜301包括晶体管的情况下，可以通过调节晶体管的宽长比来调整第一电流镜301镜像放大的倍数，即，调整第一镜像电流IR0的大小。电压放大器40的第一输入端c与第一电流镜301的输出端b连接，电压放大器40的第二输入端d用于接收与参考电压Vref；电压放大器40的输出端e连接至存储数据读取电路01的输出端。
需要说明的是，电压放大器40的第一输入端c与第一电流镜301的输出端b连接，电压放大器40的第一输入端c接收节点data(D)处的电压Vdata，电压放大器40的第二输入端d接收参考电压Vref。基于此，在一些实施例中，当Vdata大于Vref时，则电压放大器40的输出端e输出的电压为高电平例如第一电压端的电压VDD1；当Vdata小于Vref时，则电压放大器40的输出端e输出的电压为低电平例如0。在电压放大器40包括反相器，或者，电压放大器40为特殊结构的放大器(例如电压放大器40为差分放大器)的情况下，在另一些实施例中，当Vdata大于Vref时，电压放大器40的输出端e输出的电压为低电平例如0；当Vdata小于Vref时，则电压放大器40的输出端e输出的电压为高电平例如第一电压端的电压VDD1。
另外，上述节点D处的电压Vdata等于第一镜像电流IR0与第一电阻303的乘积。基于此，可以通过调整第一镜像电流IR0的大小和第一电阻303的大小，来调整Vdata。也就是说，可以增大第一电流镜301输出的第一镜像电流IR0，以及增大第一电阻303来使得电压放大器40的第一输入端c接收的电压Vdata被明显增大。
本申请实施例中，存储数据读取电路01包括第一电流镜301、第一电阻303和电压放大器40，第一电流镜301的输入端a与存储单元的第一数据读取端p连接，第一电流镜301的输出端b通过第一电阻303连接至接地端，电压放大器40的第一输入端c与第一电流镜301的输出端b连接，电压放大器40的第二输入端d用于接收参考电压Vref；电压放大器40的输出端e连接至存储数据读取电路01的输出端。由于第一电流镜301将存储单元的第一数据读取端p输出的电流Icell镜像放大为第一镜像电流IR0，并将第一镜像电流IR0输出至第一电流镜301的输出端b，而第一电流镜301的输出端b(即节点D处)的电压Vdata等于第一镜像电流IR0与第一电阻303的乘积，因而当存储单元存储“1”或“0”时，可以通过调整第一镜像电流IR0的大小(第一镜像电流IR0的大小可以通过调整第一电流镜301中晶体管的长宽比实现)与第一电阻303的大小，使得节点D处的电压Vdata增大，从而增大了存储单元存储“1”和“0”时的窗口，即增大了存储单元存储“1”时节点D处的电压Vdata1与存储单元存储“0”时节点D处的电压Vdata0的差值。这样一来，即使由于工艺偏差导致存储单元存储“1”和“0”时的窗口减小，或者，参考电压Vref有波动，但是由于经过第一 放大器30后，存储单元存储“1”或“0”时的窗口已经被放大，最大可以被放大到轨到轨(rail to rail)的电平，即节点D处的电压Vdata最大可以达到电源电压，因而电压放大器40可以对Vdata和参考电压Vref进行准确判断，有利于分辨出存储单元存储的数据是“0”还是“1”，进而确保了存储器能正确读出数据。
在一些实施例中，如图4所示，上述存储数据读取电路01(或者，第一放大器30)还包括第一开关单元302；第一电流镜301的输入端a通过第一开关单元302与存储单元的第一数据读取端p连接。
此处，第一开关单元302用于控制第一电流镜301的输入端a与存储单元的数据读取端p导通或断开。
对于上述的参考电压Vref，在一些示例中，如图4所示，存储数据读取电路01还包括参考电流源Iref；电压放大器40的第二输入端d与参考电流源Iref连接，通过参考电流源Iref提供上述的参考电压Vref。参考电流源Iref的另一端接地。由于通过参考电流源Iref给电压放大器40的第二输入端d提供参考电压Vref，因此可以通过调整参考电流源Iref的大小来调整参考电压Vref的大小。
在另一些示例中，如图5所示，存储数据读取电路01还包括参考电流产生电路50；电压放大器40的第二输入端d与参考电流产生电路50的输出端f连接。参考电流产生电路50包括第二电流镜501和第二电阻503。在此情况下，第一电流镜301、第一开关单元302、第一电阻303、第二电流镜501和第二电阻503等构成第一放大器30。附图5中未标示出第一放大器30。
第二电流镜501的输入端g与并联的第一参考存储单元和第二参考存储单元的第二数据读取端q连接；第一参考存储单元和第二参考存储单元的存储状态不同。第二电流镜501的输出端f通过第二电阻503连接至接地端，且第二电流镜501的输出端f还与电压放大器40的第二输入端d连接；第一参考存储单元和第二参考存储单元被参考字线WL-ref选通后，并联的第一参考存储单元和第二参考存储单元的第二数据读取端q向第二电流镜501的输入端g输出电流；第二电流镜501用于将第二数据读取端q输出的总电流Irefcell镜像放大为第二镜像电流IR1，并将第二镜像电流IR1输出至第二电流镜501的输出端f；第二电流镜501还与电源电压(例如第二电压端VDD2)连接。
此处，第一电压端VDD1和第二电压端VDD2可以相同，也可以不相同。
可以理解的是，第二电流镜501将并联的第一参考存储单元和第二参考存储单元的第二数据读取端q输出的总电流Irefcell镜像放大为第二镜像电流IR1，镜像放大的倍数与第二电流镜501的结构有关，可以通过调整第二电流镜501的结构来调整第二电流镜501镜像放大的倍数，即，调整第二镜像电流IR1的大小。具体的，在第二电流镜501包括晶体管的情况下，可以通过调节晶体管的宽长比来调整第二电流镜501镜像放大的倍数，即，调整第二镜像电流IR1的大小。由于第二电流镜501的输出端f与电压放大器40的第二输入端d连接，且第二电流镜501的输出端f还与第二电阻503连接，因而电压放大器40的第二输入端d接收的参考电压Vref等于第二镜像电流IR1与第二电阻503的乘积。基于此，可以通过调整第二镜像电流IR1的大小(第二镜像电流IR1的大小可以通过调整第二电流镜501中晶体管的长度比实现)和第二 电阻503的大小，来调整参考电压Vref。一般地，选取的参考电压Vref为存储单元存“1”时Vdata1和存储单元存“0”时Vdata0之间的中间值。
另外，第一参考存储单元和第二参考存储单元的存储状态不同，可以是第一参考存储单元存储“1”，第二参考存储单元存储“0”；也可以是第一参考存储单元存储“0”，第二参考存储单元存储“1”。
在此基础上，并联的第一参考存储单元和第二参考存储单元与参考字线WL-ref、参考位线BL-ref以及参考源极线SL-ref连接。此处，参考源极线SL可以与第四电压端VSS2连接，也可以接地。第三电压端VSS1和第四电压端VSS2可以相同，也可以不相同。
需要说明的是，第一参考存储单元和第二参考存储单元可以是存储器的存储单元阵列中用于进行读操作和写操作的参考单元，例如，当字线选通存储单元阵列中的任一存储单元，对该存储单元进行读操作时，此时可以将存储单元阵列中未进行读操作的两个存储单元作为第一参考存储单元和第二参考存储单元，且这两个存储单元的存储状态不同。在此情况下，参考字线WL-ref即存储单元阵列中的字线WL，参考位线BL-ref即存储单元阵列中的位线BL，参考源极线SL-ref即存储单元阵列中的源极线SL。当然，第一参考存储单元和第二参考存储单元也可以是独立于存储单元阵列，额外单独制作的。在此情况下，参考字线WL-ref、参考位线BL-ref和参考源极线SL-ref也可以单独制作。
在一些实施例中，如图5所示，上述的参考电流产生电路50还包括第二开关单元502；第二电流镜501的输入端g通过第二开关单元502与第二数据读取端q连接。
此处，第二开关单元502用于控制第二电流镜501的输入端g与第二数据读取端q的导通或断开。
本申请实施例中，电压放大器40的第二输入端d与参考电流产生电路50的输出端f连接，通过参考电流产生电路50为电压放大器40的第二输入端d提供参考电压Vref。由于参考电流产生电路50与并联的第一参考存储单元和第二参考存储单元的第二数据读取端q连接，第一参考存储单元和第二参考存储单元的第二数据读取端q输出的总电流Irefcell为第一参考存储单元输出的电流和第二参考存储单元输出的电流之和，而第一参考存储单元和第二参考存储单元的存储状态相反，因此可以确保参考电流产生电路50的输出端f提供参考电压Vref为存储单元存“1”时的电压和“0”时的电压的中间值，提高了参考电压Vref的准确性，进一步确保了存储数据读取电路01能够正确读出数据。
在一些实施例中，如图6所示，第一电流镜301包括第一晶体管MP0和第二晶体管MP1。第一晶体管MP0的第一端和第二晶体管MP1的第一端均与第一电压端VDD1连接，第一晶体管MP0的第二端与第一数据读取端p连接，第二晶体管MP1的第二端与第一电阻303连接；第一晶体管MP0的控制端和第二晶体管MP1的控制端连接，且第一晶体管MP0的控制端与第一晶体管MP0的第二端连接。
需要说明的是，可以通过调整第一晶体管MP0和第二晶体管MP1的宽长比，来调整第一电流镜301的镜像放大倍数。
在一些实施例中，如图6所示，第一开关单元302包括第三晶体管MN0；第三晶 体管MN0的控制端与第一控制线Ysel1连接，第一端与第一电流镜301的输入端a连接(即与第一晶体管MP0的第二端连接)，第二端与存储单元的第一数据读取端p连接。
此处，第一控制线Ysel1用于控制第三晶体管MN0的选通与否。
在一些实施例中，上述的第一电阻303为可变电阻器(也可以称为电位器)。在另一些实施例中，如图6所示，第一电阻303包括第四晶体管MN1，第四晶体管MN1的控制端与第一端连接，第四晶体管MN1的第二端接地，第四晶体管MN1的第一端与第一电流镜301的输出端b连接(即与第二晶体管MP1的第二端连接)。在此情况下，可以通过调整第四晶体管MN1的尺寸(例如宽长比)来调整第一电阻303的大小。
在一些实施例中，如图6所示，第二电流镜501包括第五晶体管MP4和第六晶体管MP3；第五晶体管MP4的第一端和第六晶体管MP3的第一端均与第二电压端VDD2连接，第五晶体管MP4的第二端与第二数据读取端q连接，第六晶体管MP3的第二端与电压放大器40的第二输入端d连接；第五晶体管MP4的控制端和第六晶体管MP3的控制端连接，且第五晶体管MP4的控制端与第五晶体管MP4的第二端连接。
需要说明的是，可以通过调整第五晶体管MP4和第六晶体管MP3的尺寸(例如宽长比)，来调整第二电流镜501的镜像放大倍数。
在一些实施例中，如图6所示，第二开关单元502包括第七晶体管MN2；第七晶体管MN2的控制端与第二控制线Ysel2连接，第一端与第二电流镜501的输入端g连接(即与第五晶体管MP4的第二端连接)，第二端与第二数据读取端q连接。
此处，第二控制线Ysel2用于控制第七晶体管MN2的选通与否。
此外，第一控制线Ysel1和第二控制线Ysel2可以相同，也可以不相同。
在一些实施例中，上述的第二电阻503为可变电阻器。在另一些实施例中，如图6所示，第二电阻503包括第八晶体管MN3，第八晶体管MN3的控制端与第一端连接，第八晶体管MN3的第二端接地，第八晶体管MN3的第一端与电压放大器40的第二输入端d连接(即与第六晶体管MP3的第二端)。在此情况下，可以通过调整第八晶体管MN3的尺寸(例如宽长比)来调整第二电阻503的大小。
基于上述，需要说明的是，上述的第一晶体管MP0、第二晶体管MP1、第三晶体管MN0、第四晶体管MN1、第五晶体管MP4、第六晶体管MP3、第七晶体管MN2和第八晶体管MN3可以是P型晶体管，也可以是N型晶体管。第一晶体管MP0、第二晶体管MP1、第三晶体管MN0、第四晶体管MN1、第五晶体管MP4、第六晶体管MP3、第七晶体管MN2和第八晶体管MN3的类型可以相同，也可以不完全相同。在一些实施例中，第一晶体管MP0、第二晶体管MP1、第五晶体管MP4和第六晶体管MP3为P型晶体管，第三晶体管MN0、第四晶体管MN1、第七晶体管MN2和第八晶体管MN3为N型晶体管。
基于上述实施例一提供的如图5和图6所示的存储数据读取电路01的结构，本申请实施例还提供一种存储数据读取电路的控制方法，用于控制上述实施例一提供的存储数据读取电路01。该存储数据读取电路的控制方法包括：
S10、第一开关单元302处于导通状态，存储单元被字线WL选通后，存储单元的第一数据读取端p向第一电流镜301的输入端a输出电流Icell，第一电流镜301将存储单元的第一数据读取端p输出的电流Icell镜像放大为第一镜像电流IR0，并将 第一镜像电流IR0输出至第一电流镜的输出端b，电压放大器40的第一输入端c与第一电流镜301的输出端b连接；电压放大器40根据电压放大器40的第一输入端c输入的电压Vdata和第二输入端d接收的参考电压Vref，向电压放大器40的输出端输出信号。
需要说明的是，在一些实施例中，当Vdata大于Vref时，则电压放大器40的输出端e输出的电压为高电平例如第一电压端的电压VDD1；当Vdata小于Vref时，则电压放大器40的输出端e输出的电压为低电平例如0。在电压放大器40包括反相器，或者，电压放大器40为特殊结构的放大器(例如电压放大器40为差分放大器)的情况下，在另一些实施例中，当Vdata大于Vref时，电压放大器40的输出端e输出的电压为低电平例如0；当Vdata小于Vref时，则电压放大器40的输出端e输出的电压为高电平例如第一电压端的电压VDD1。
实施例二
如图7所示，上述存储数据读取电路01包括第一电流镜301、第一电阻303和第一反相器inverter0(inv0)。
第一电流镜301的输入端a与存储单元的第一数据读取端p连接，第一电流镜301的输出端b通过第一电阻303连接至接地端；第一电流镜301还与电源电压(例如第一电压端VDD1)连接。存储单元与字线WL、位线BL以及源极线SL连接。此处，源极线SL可以与第三电压端VSS1连接，也可以接地。存储单元被字线WL选通后，存储单元的第一数据读取端p向第一电流镜301的输入端a输出电流Icell；第一电流镜301用于将存储单元的第一数据读取端p输出的电流Icell镜像放大为第一镜像电流IR0，并将第一镜像电流IR0输出至第一电流镜301的输出端b。
第一反相器inv0的输入端h与第一电流镜301的输出端b连接；第一反相器inv0的输出端i连接至存储数据读取电路01的输出端。
应当理解到，当第一电流镜301的输出端b(即节点D处)的电压Vdata大于第一反相器inv0的阈值电压时，第一反相器inv0的输出端i输出的电压为低电平例如0；当第一电流镜301的输出端b的电压Vdata小于第一反相器inv0的阈值电压时，第一反相器inv0的输出端i输出的电压为高电平例如第一电压端的电压VDD1。
本申请实施例中，由于第一电流镜301将存储单元的第一数据读取端p输出的电流Icell镜像放大为第一镜像电流IR0，并将第一镜像电流IR0输出至第一电流镜301的输出端b，而第一电流镜301的输出端b(即节点D处)的电压Vdata等于第一镜像电流IR0与第一电阻303的乘积，因而当存储单元存储“1”或“0”时，可以通过调整第一镜像电流IR0的大小(第一镜像电流IR0的大小可以通过调整第一电流镜301中晶体管的长宽比实现)与第一电阻303的大小，使得节点D处的电压Vdata增大，从而增大了存储单元存储“1”和“0”时的窗口，即增大了存储单元存储“1”时节点D处的电压Vdata1与存储单元存储“0”时节点D处的电压Vdata0的差值。这样一来，即使由于工艺偏差导致存储单元存储“1”和“0”时的窗口减小，或者，参考电压Vref有波动，但是由于存储单元存储“1”或“0”时的窗口已经被放大，而对于第一反相器inv0，当第一电流镜301的输出端b的电压Vdata大于第一反相器inv0的阈值电压时，第一反相器inv0的输出端i输出的电压为低电平；当第一电流镜301的输出端 b的电压Vdata小于第一反相器inv0的阈值电压时，第一反相器inv0的输出端i输出的电压为高电平，因而第一反相器inv0可以对Vdata进行准确判断，有利于分辨出存储单元存储的数据是“0”还是“1”，进而确保了存储器能正确读出数据。
在一些实施例中，如图7所示，上述存储数据读取电路01还包括第一开关单元302；第一电流镜301的输入端a通过第一开关单元302与存储单元的数据读取端p连接。
此处，第一开关单元302用于控制第一电流镜301的输入端a与存储单元的数据读取端p导通或断开。
需要说明的是，第一电流镜301、第一开关单元302和第一电阻303可以参考上述实施例的解释说明，此处不再赘述。
基于上述实施例二提供的如图7所示的存储数据读取电路01的结构，本申请实施例还提供一种存储数据读取电路的控制方法，用于控制上述实施例二提供的存储数据读取电路01。该存储数据读取电路的控制方法包括：
S20、第一开关单元302处于导通状态，存储单元被字线WL选通后，存储单元的第一数据读取端p向第一电流镜301的输入端a输出电流Icell，第一电流镜301将存储单元输出的电流Icell镜像放大为第一镜像电流IR0，并将第一镜像电流IR0输出至第一电流镜的输出端b，第一反相器inv0的输入端h与第一电流镜301的输出端b连接；第一反相器inv0根据第一反相器inv0的输入端h输入的电压，向第一反相器inv0的输出端i输出信号。
此处，第一反相器inv0根据第一反相器inv0的输入端h输入的电压，向第一反相器inv0的输出端i输出信号，具体可以参考上述描述，此处不再赘述。
实施例三
如图8所示，上述存储数据读取电路01包括第一电流镜301、第一电阻303、电压放大器40、第一反相器inv0和第一选择器(multiplexer，MUX)60。
第一电流镜301的输入端a与存储单元的第一数据读取端p连接，第一电流镜301的输出端b通过第一电阻303连接至接地端；第一电流镜301还与电源电压(例如第一电压端VDD1)连接。存储单元与字线WL、位线BL以及源极线SL连接。此处，源极线SL可以与第三电压端VSS1连接，也可以接地。存储单元被字线WL选通后，存储单元的第一数据读取端p向第一电流镜301的输入端a输出电流Icell；第一电流镜301用于将存储单元的第一数据读取端p输出的电流Icell镜像放大为第一镜像电流IR0，并将第一镜像电流IR0输出至第一电流镜301的输出端b。
电压放大器40的第一输入端c与第一电流镜301的输出端b连接，电压放大器40的第二输入端d用于接收参考电压Vref。电压放大器40用于将其第一输入端c输入的电压Vdata和第二输入端d输入的电压Vref的差值进行反相输出，即电压放大器40用于将第一电流镜301的输出端b输出的电压Vdata与电压放大器40的第二输入端d接收的参考电压Vref之差进行反相输出。
第一反相器inv0的输入端h与第一电流镜301的输出端b连接；第一反相器inv0的输出端i与第一选择器60的第一输入端连接，电压放大器40的输出端e与第一选择器60的第二输入端连接；第一选择器60的输出端j连接至存储数据读取电路01 的输出端。
在一些实施例中，如图8所示，上述存储数据读取电路01还包括第一开关单元302；第一电流镜301的输入端a通过第一开关单元302与存储单元的数据读取端p连接。
此处，第一开关单元302用于控制第一电流镜301的输入端a与存储单元的数据读取端p导通或断开。需要说明的是，第一电流镜301、第一开关单元302和第一电阻303和第一反相器inv0均可以参考上述实施例的解释说明，此处不再赘述。
此外，电压放大器40的第二输入端d可以与参考电流源Iref连接，通过参考电流源Iref为电压放大器40的第二输入端d提供参考电压Vref；也可以与参考电流产生电路50的输出端f连接，通过参考电流产生电路50为电压放大器40的第二输入端d提供参考电压Vref。参考电流源Iref和参考电流产生电路50具体可以参考上述实施例一，此处不再赘述。
在此基础上，由于电压放大器40用于将其第一输入端c输入的电压Vdata和第二输入端d输入的电压Vref的差值进行反相输出，因此当Vdata大于Vref时，则电压放大器40的输出端e输出的电压为低电平例如0；当Vdata小于Vref时，则电压放大器40的输出端e输出的电压为高电平例如第一电压端的电压VDD1。基于此，在一些实施例中，本实施例提供的电压放大器40包括反相器。在另一些实施例中，电压放大器40为特殊结构的放大器例如电压放大器40为差分放大器。
此处，第一选择器60的输出端j选择其第一输入端和第二输入端中的一个进行输出。在一些实施例中，如图8所示，存储数据读取电路01还包括错误检测电路90；第一选择器60的控制端与错误检测电路90电连接，错误检测电路90与第一反相器inv0的输出端i和电压放大器40的输出端e连接，错误检测电路90用于根据第一反相器inv0的输出端i输出的信号Q-first(Q-1st)和电压放大器40的输出端e输出的信号Q-second(Q-2nd)输出错误检测信号error-detect(er-det)。第一选择器60根据错误检测信号er-det确定第一选择器60的输出端j输出的信号Q-final(Q-f)为第一反相器inv0的输出端i输出的信号Q-1st或电压放大器40的输出端e输出的信号Q-2nd。示例的，若Q-1st和Q-2nd相同，则第一选择器60选择输出Q-1st或Q-2nd；若Q-1st和Q-2nd不相同，则第一选择器60选择输出Q-1st。
需要说明的是，错误检测电路90可以通过逻辑运算门实现。例如，错误检测电路90包括异或门，其中，异或门的一个输入端与第一反相器inv0的输出端i连接，另一个输入端与电压放大器40的输出端e连接，异或门的输出端与第一选择器60的控制端连接。
在一些实施例中，如图8所示，上述电压放大器40的使能信号端SAE(sense amplifier enable)与使能信号控制电路70连接。通过使能信号控制电路70给电压放大器40的使能信号端SAE提供使能信号，以使能电压放大器40。
在另一些实施例中，在电压放大器40的第二输入端d与参考电流产生电路50的输出端连接的情况下，如图9所示，存储数据读取电路01还包括第二选择器80；电压放大器40的使能信号端SAE与第二选择器80的输出端连接，使能信号控制电路70与第二选择器80的第一输入端m连接，参考电流产生电路50的输出端与第二选择器 80的第二输入端n连接。
考虑到在一些示例中，电压放大器40的使能信号端SAE提供高电平信号时，电压放大器40将其第一输入端c输入的电压和第二输入端d输入的电压进行比较，并从电压放大器40的输出端e输出信号，此时电压放大器40高有效。在另一些示例中，使能信号端SAE提供低电平信号时，电压放大器40将其第一输入端c输入的电压和第二输入端d输入的电压进行比较，并从电压放大器40的输出端e输出信号，此时电压放大器40低有效。在此情况下，参考电流产生电路50的输出端通过第二反相器inverter1(inv1)与第二选择器80的第二输入端n连接。具体的，第二反相器inv1的输入端与参考电流产生电路50的输出端连接，第二反相器inv1的输出端与第二选择器80的第二输入端n连接。
需要说明的是，当电压放大器40的使能信号端SAE与第二选择器80的输出端连接时，第二选择器80可以选择使能信号控制电路70为电压放大器40的使能信号端SAE提供使能信号，也可以选择第二反相器inv1输出的信号为电压放大器40的使能信号端SAE提供使能信号。
由于节点D处的电压是逐渐增大的，若电压放大器40的第一输入端c获取节点D处的电压Vdata时间过早，则电压放大器40的第一输入端c接收的电压Vdata可能不准，这样电压放大器40输出的值就有可能有误。本申请实施例中，由于电压放大器40的使能信号端SAE与第二选择器80的输出端，而第二选择器80的第二输入端n与参考电流产生电路50的输出端连接，由于参考电流产生电路50中第二电流镜501的输入端g与并联的第一参考存储单元和第二参考存储单元的第二数据读取端a连接，而第一参考存储单元和第二参考存储单元是已知的参考单元，因此电压放大器40的第二输出端d在预定的时间内是否接收到正确的参考电压Vref是可以判断出来的，这样一来，可以在参考电流产生电路50提供正确的参考电压Vref的同时给第二选择器80的第二输入端n提供信号，并提供给电压放大器40的使能信号端SAE，此时，电压放大器40的使能信号端SAE才向电压放大器40提供使能信号使能电压放大器40，电压放大器40根据第一输入端c输入的参考电压Vref和第二输入端d输入的电压Vdata的差值从电压放大器40的输出端e输出信号，这时电压放大器40的第一输入端c接收的电压Vdata是稳定的，因此提高了电压放大器40输出端输出的信号的稳定性。
基于上述，在一些实施例中，如图8和如图9所示，存储单元还与第九晶体管MP5的控制端连接，第九晶体管MP5的第一端与位线BL连接，第二端通过二极管L与源极线SL连接。此外，第九晶体管MP5可以是P型晶体管，也可以是N型晶体管。
基于上述实施例三提供的如图8和图9所示的存储数据读取电路01的结构，本申请实施例还提供一种存储数据读取电路01的控制方法，用于控制上述实施三提供的存储数据读取电路01。参考图10所示的时序图，该时序图分别提供了读使能信号REN的时序曲线；读时钟信号CLK的时序曲线；字线WL输出的信号的时序曲线；电压放大器40的使能信号端SAE输出的使能信号的时序曲线；第一反相器inv0的输出端i输出的信号Q-1st的时序曲线；电压放大器40的输出端e输出的信号Q-2nd的时序曲线；第一选择器60的输出端j输出的信号Q-f的时序曲线；错误检测信号er-det的时序曲线。
结合图10所示的时序图，该存储数据读取电路01的控制方法包括：
S30、第一阶段，第一开关单元302处于导通状态，存储单元被字线WL选通后，存储单元的第一数据读取端p向第一电流镜301的输入端a输出电流Icell，第一电流镜301将存储单元的第一数据读取端p输出的电流Icell镜像放大为第一镜像电流IR0，并将第一镜像电流IR0输出至第一电流镜301的输出端b，电压放大器40的第一输入端c与第一电流镜301的输出端b连接；电压放大器40的使能信号端SAE向电压放大器40提供使能信号使能电压放大器40；电压放大器40根据电压放大器40的第一输入端c输入的电压Vdata和第二输入端d输入的参考电压Vref，向电压放大器40的输出端e输出信号，第一选择器60的输出端j选择输出电压放大器40的输出端e输出的信号Q-2nd。
此处，参考图10，当提供读使能信号REN时，存储数据读取电路01开始读操作。字线WL提供的信号选通待读取的存储单元，在读时钟信号CLK上升沿来临后的一小段固定延时内，电压放大器40的使能信号端SAE提供使能信号，电压放大器40根据电压放大器40的第一输入端c输入的电压Vdata和第二输入端d输入的参考电压Vref，向电压放大器40的输出端e输出信号Q-2nd。在此阶段，第一选择器60的输出端j选择输出电压放大器40的输出端e输出的信号Q-2nd。
此外，在第一阶段，可以通过使能信号控制电路70给电压放大器40的使能信号端SAE提供使能信号。
需要说明的是，由于固定延时一般设置的很小，因此在第一阶段，第一选择器60的输出端j可以快速输出信号Q-f，此时Q-fl为Q-2nd。由于该模式相对激进，因而也可以将该阶段称为激进型推测读操作。
S31、第二阶段，电压放大器40未被电压放大器40的使能信号端SAE使能(电压放大器40未输出信号)；若第一反相器inv0输出的信号Q-1st与第一阶段第一选择器60输出的信号Q-2nd(第一阶段第一选择器60输出的信号为电压放大器40输出的信号Q-2nd)相同，则第一选择器60保持输出第一阶段电压放大器40输出的信号Q-2nd；若第一反相器inv0输出的信号Q-1st与第一阶段第一选择器60输出的信号Q-2nd不相同，则控制第一选择器60选择输出第一反相器inv0输出的信号Q-1st。
此处，在第二阶段，可以通过错误检测电路90输出的错误检测信号er-det控制第一选择器60选择输出第一反相器inv0输出的信号Q-1st。错误检测电路90具体可以参考上述实施例，此处不再赘述。
需要说明的是，由于第一阶段，第一选择器60的输出端j在很短的时间内快速输出信号Q-f，此时，电压放大器40的第一输入端c输入的电压Vdata和第二输入端d输入的参考电压Vref的差值可能并未达到特别理想的幅度，例如，电压放大器40的第一输入端c输入的电压Vdata和第二输入端d输入的参考电压Vref的差值可能小于电压放大器40的灵敏度，在工艺偏差等因素的影响下，Vdata和Vref的差值可能不足以使电压放大器40百分百正确工作，存在一定的误读概率。而一方面，第一反相器inv0的阈值电压一般较大，另一方面，第二阶段读取时间晚于第一阶段读取的时间，因而第一反相器inv0输出的信号Q-1st大概率是准确的，因此在第二阶段，当第一反相器inv0输出的信号Q-1st与第一阶段电压放大器40输出的信号Q-2nd不相同时， 第一选择器60的输出端j输出的信号Q-f选择第一反相器inv0输出的信号Q-1st。
当第一反相器inv0的输入端h接收的电压Vdata大于第一反相器inv0的阈值电压时，第一反相器inv0的输出端i输出的电压为低电平；当第一反相器inv0的输入端h接收的电压Vdata小于第一反相器inv0的阈值电压时，第一反相器inv0的输出端i输出的电压为高电平。由于第一反相器inv0的输入端h接收的电压Vdata在存储单元存储“1”和“0”时已经被进行了放大，最大可以被放大到轨到轨的电平，即节点D处的电压Vdata最大可以达到电源电压，因而可以确保第一反相器inv0的输出端i输出的信号Q-1st的准确性。此外，也可以将该阶段称为稳定型推测读操作。
S32、第三阶段，电压放大器40的使能信号端SAE向电压放大器40提供使能信号使能电压放大器40，电压放大器40的输出端e输出信号Q-2nd，若电压放大器40输出的信号Q-2nd与第二阶段第一选择器60输出的信号Q-1st(第二阶段第一选择器60输出的信号为第一反相器inv0输出的信号Q-1st)相同，则第一选择器60保持输出第二阶段第一选择器60输出的信号Q-1st；若电压放大器40输出的信号Q-2nd与第二阶段第一选择器60输出的信号Q-1st不相同，则控制第一选择器60选择输出电压放大器40输出的信号Q-2nd。
应当理解到，在第二阶段和第三阶段，第一开关单元302仍处于导通状态，且存储单元被字线WL选通。
此处，经过了第一阶段和第二阶段，电压放大器40的第一输入端c输入的电压Vdata已经有足够的时间去放大，第一输入端c输入的电压Vdata和参考电压Vref已经形成足够的电压差，因此，在第三阶段窗口已经进行了完全放大。
此外，在第三阶段，电压放大器40的使能信号端SAE提供的使能信号可以由使能信号控制电路70提供，也可以由参考电流产生电路50提供。在使能信号端SAE提供的使能信号由参考电流产生电路50提供时，可以进一步确保窗口被完全进行放大，具体原因参考上述实施例，此处不再赘述。
在相对恶劣的工艺偏差下或在极端情况下，在第二阶段第一选择器60的输出端j输出的信号Q-1st也可能会出错。由于第三阶段，窗口已经进行了完全放大，因此电压放大器40即使在相对恶劣的工艺偏差下或在极端情况下也能进行正确的放大，确保了电压放大器40的输出端e输出信号的正确性。基于此，也可以将该阶段称为纠正读操作。
需要说明的是，步骤S32为可选的步骤，例如在一些实施例中也可以省略。
以下提供具体的实施例，对上述存储数据读取电路达到的效果进行分析。
在理想条件下，即典型的工艺角(typical corner)，温度为25℃，电源电压1.2V时，若以第一选择器60输出的信号Q-f为第一反相器inv0输出的信号Q-1st进行读“0”和读“1”操作，如图11所示，可以看到根据第一选择器60的输出端j输出的信号Q-f可以正确读出了“1”和“0”。由于D处的电压经过放大后，存储单元的窗口变大为1050mV,几乎为逻辑高电平，因此Q可以被正确识别。
然而，在高温高漏电条件下，即快工艺角(fast corner)，温度为125℃，电源电压1.32V时，如果只将第一反相器inv0输出的信号Q-1st作为第一选择器60输出的信号Q-f，在该高温高漏电条件下，当时钟周期变长，读“1”会出现错误。参考图 12，可以看到，在高温高漏电条件下，在读“1”时，D处的电压增大，这样经过第一反相器inv0输出的信号Q-1st就会为低电平信号，从而会误读为“0”，因此在极端情况下，将第一反相器inv0输出的信号Q-1st作为第一选择器60输出的信号Q-f，会出现误读的情况，即稳定性读操作出错。
在稳定型读操作出错后，可以用纠正型读操作读出的数据对稳定型读操作读出的数据进行更新。具体过程为：电压放大器40的使能信号端SAE向电压放大器40提供使能信号使能电压放大器40，电压放大器40对D处的电压Vdata和参考电压Vref进行比较，以在电压放大器40的输出端e输出信号Q-2nd。在上述高温高漏电条件下，最终第一选择器60输出的信号Q-f为电压放大器40的输出端e输出信号Q-2nd。参考图13，虽然第一反相器inv0输出的信号Q-1st直接读出出错，但是通过电压放大器40进行修正后，最终第一选择器60输出的信号Q-f为Q-2nd时，可以实现正确读出“1”和“0”。
在此基础上，参考图13，现有技术中图13中第二级放大器20处理的总窗口为140mV(100mV+40mV)左右，最小窗口为40mV。而本申请实施例中，电压放大器40处理的总窗口为800mV(460mV+340mV)，最小窗口为340mV，本申请实施例相对于现有技术总窗口提升471％((800-140)/140＝471％)，最小窗口提升750％((340-40)/40＝750％)。根据测试结果可以看出，在工艺偏差条件下，本申请实施例有效提升了存储数据读取电路01数据读出的准确性。
如图14所示，以存储数据读取电路读“0”为例，提供了激进型推测读出、稳定型推测读出、纠正型读出的波形图,本申请实施例以存储数据读取电路01的读出速度来评价存储数据读取电路01的性能。为了确保存储数据读取电路01读出数据的正确性，因此会利用纠正型读出对存储单元存储的数据进行读出，但是根据图14可以看出，纠正型读出在性能上不具有优势，本申请实施例可以通过激进型读出和稳定型读出对性能进行提升。对激进型推测读出、稳定型推测读出和纠正型读出所需的时间进行检测，如表1所示。
表1
  激进型推测读出 稳定型推测读出 纠正型读出 优化比例
时间(ns) 36 42 62 32.25％-41.9％
参考表1，激进型推测读出所需的时间为36ns，稳定型推测读出所需的时间为42ns，纠正型读出所需的时间为62ns。激进型推测读出相对于纠正型读出提升性能41.9％((62-36)/62＝41.9％)，稳定型推测读出相对于纠正型读出提升性能32.25％((62-42)/62＝32.25％)。
基于上述，本申请实施例可以有效地放大窗口，避免了工艺偏差以及新型存储单元特性造成的误读。此外，通过纠正型读出可以确保在工艺偏差条件下存储数据读取电路01能够正确读出数据。在此基础上，还可以通过激进型推测读出和稳定型推测读出提升存储数据读取电路01的性能。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保 护范围为准。

Claims (21)

  1. 一种存储数据读取电路，其特征在于，包括第一电流镜、第一电阻和电压放大器；
    所述第一电流镜的输入端与存储单元的第一数据读取端连接，所述第一电流镜的输出端通过所述第一电阻连接至接地端；所述第一电流镜用于将所述存储单元的第一数据读取端输出的电流镜像放大为第一镜像电流，并将所述第一镜像电流输出至所述第一电流镜的输出端；
    所述电压放大器的第一输入端与所述第一电流镜的输出端连接，所述电压放大器的第二输入端用于接收参考电压；所述电压放大器的输出端连接至所述存储数据读取电路的输出端。
  2. 根据权利要求1所述的存储数据读取电路，其特征在于，所述存储数据读取电路还包括第一反相器和第一选择器；所述电压放大器的输出端通过所述第一选择器连接至所述存储数据读取电路的输出端；
    所述第一反相器的输入端与所述第一电流镜的输出端连接，所述第一反相器的输出端与所述第一选择器的第一输入端连接，所述电压放大器的输出端与所述第一选择器的第二输入端连接；
    所述第一选择器的输出端连接至所述存储数据读取电路的输出端；
    所述电压放大器用于将其所述第一输入端输入的电压和所述第二输入端输入的电压的差值进行反相输出。
  3. 根据权利要求1或2所述的存储数据读取电路，其特征在于，所述存储数据读取电路还包括参考电流源；所述电压放大器的第二输入端与所述参考电流源连接，通过所述参考电流源提供所述参考电压。
  4. 根据权利要求1或2所述的存储数据读取电路，其特征在于，所述存储数据读取电路还包括参考电流产生电路；所述电压放大器的第二输入端与参考电流产生电路的输出端连接；
    所述参考电流产生电路包括第二电流镜和第二电阻；
    所述第二电流镜的输入端与并联的第一参考存储单元和第二参考存储单元的第二数据读取端连接；所述第二电流镜的输出端通过所述第二电阻连接至接地端，且所述第二电流镜的输出端还与所述电压放大器的第二输入端连接；所述第二电流镜用于将所述第二数据读取端输出的总电流镜像放大为第二镜像电流，并将所述第二镜像电流输出至所述第二电流镜的输出端；
    其中，所述第一参考存储单元和所述第二参考存储单元的存储状态不同。
  5. 根据权利要求1-4任一项所述的存储数据读取电路，其特征在于，所述电压放大器的使能信号端与使能信号控制电路连接。
  6. 根据权利要求4所述的存储数据读取电路，其特征在于，所述存储数据读取电路还包括第二选择器；所述电压放大器的使能信号端与所述第二选择器的输出端连接，使能信号控制电路与所述第二选择器的第一输入端连接，所述参考电流产生电路的输出端与所述第二选择器的第二输入端连接。
  7. 根据权利要求2所述的存储数据读取电路，其特征在于，所述存储数据读取电 路还包括错误检测电路，所述第一选择器的控制端与所述错误检测电路电连接；
    所述错误检测电路与所述第一反相器的输出端和所述电压放大器的输出端连接，所述错误检测电路用于根据所述第一反相器的输出端输出的信号和所述电压放大器的输出端输出的信号输出错误检测信号；
    所述第一选择器根据所述错误检测信号确定所述第一选择器的输出端输出所述第一反相器的输出端输出的信号或所述电压放大器的输出端输出的信号。
  8. 根据权利要求1所述的存储数据读取电路，其特征在于，所述存储数据读取电路还包括第一开关单元；
    所述第一电流镜的输入端通过所述第一开关单元与所述存储单元的第一数据读取端连接。
  9. 根据权利要求4所述的存储数据读取电路，其特征在于，所述参考电流产生电路还包括第二开关单元；
    所述第二电流镜的输入端通过所述第二开关单元与所述第二数据读取端连接。
  10. 根据权利要求1-9任一项所述的存储数据读取电路，其特征在于，所述第一电流镜包括第一晶体管和第二晶体管；
    所述第一晶体管的第一端和所述第二晶体管的第一端均与第一电压端连接，所述第一晶体管的第二端与所述第一数据读取端连接，所述第二晶体管的第二端与所述第一电阻连接；所述第一晶体管的控制端和所述第二晶体管的控制端连接，且所述第一晶体管的控制端与所述第一晶体管的第二端连接。
  11. 根据权利要求1-10任一项所述的存储数据读取电路，其特征在于，所述第一电阻包括第四晶体管，所述第四晶体管的控制端与第一端连接，所述第四晶体管的第二端接地，所述第四晶体管的第一端与所述第一电流镜的输出端连接。
  12. 根据权利要求4所述的存储数据读取电路，其特征在于，所述第二电流镜包括第五晶体管和第六晶体管；
    所述第五晶体管的第一端和所述第六晶体管的第一端均与第二电压端连接，所述第五晶体管的第二端与所述第二数据读取端连接，所述第六晶体管的第二端与所述电压放大器的第二输入端连接；所述第五晶体管的控制端和所述第六晶体管的控制端连接，且所述第五晶体管的控制端与所述第五晶体管的第二端连接。
  13. 根据权利要求4或12所述的存储数据读取电路，其特征在于，所述第二电阻包括第八晶体管，所述第八晶体管的控制端与第一端连接，所述第八晶体管的第二端接地，所述第八晶体管的第一端与所述电压放大器的第二输入端连接。
  14. 根据权利要求8所述的存储数据读取电路，其特征在于，所述第一开关单元包括第三晶体管；所述第三晶体管的控制端与第一控制线连接，第一端与所述第一电流镜的输入端连接，第二端与所述第一数据读取端连接。
  15. 根据权利要求9所述的存储数据读取电路，其特征在于，所述第二开关单元包括第七晶体管；所述第七晶体管的控制端与第二控制线连接，第一端与所述第二电流镜的输入端连接，第二端与所述第二数据读取端连接。
  16. 一种存储数据读取电路，其特征在于，包括第一电流镜、第一电阻和第一反相器；
    所述第一电流镜的输入端与存储单元的第一数据读取端连接，所述第一电流镜的输出端通过所述第一电阻连接至接地端；所述第一电流镜用于将所述存储单元的第一数据读取端输出的电流镜像放大为第一镜像电流，并将所述第一镜像电流输出至所述第一电流镜的输出端；
    所述第一反相器的输入端与所述第一电流镜的输出端连接；所述第一反相器的输出端连接至所述存储数据读取电路的输出端。
  17. 根据权利要求16所述的存储数据读取电路，其特征在于，所述存储数据读取电路还包括第一开关单元；
    所述第一电流镜的输入端通过所述第一开关单元与所述存储单元的数据读取端连接。
  18. 根据权利要求16所述的存储数据读取电路，其特征在于，所述第一电流镜包括第一晶体管和第二晶体管；
    所述第一晶体管的第一端和所述第二晶体管的第一端均与第一电压端连接，所述第一晶体管的第二端与所述第一数据读取端连接，所述第二晶体管的第二端与所述第一电阻连接；所述第一晶体管的控制端和所述第二晶体管的控制端连接，且所述第一晶体管的控制端与所述第一晶体管的第二端连接。
  19. 根据权利要求16所述的存储数据读取电路，其特征在于，所述第一电阻包括第四晶体管，所述第四晶体管的控制端与第一端连接，所述第四晶体管的第二端接地，所述第四晶体管的第一端与所述第一电流镜的输出端连接。
  20. 根据权利要求17所述的存储数据读取电路，其特征在于，所述第一开关单元包括第三晶体管；所述第三晶体管的控制端与第一控制线连接，第一端与所述第一电流镜的输入端连接，第二端与所述第一数据读取端连接。
  21. 一种存储器，其特征在于，包括阵列分布的多个存储单元以及至少一个如权利要求1-20任一项所述的存储数据读取电路。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1845253A (zh) * 2006-04-28 2006-10-11 清华大学 一种应用于快闪存储器的灵敏放大器电路
CN103077745A (zh) * 2012-12-24 2013-05-01 上海宏力半导体制造有限公司 存储单元的读取电路和存储器
CN104252879A (zh) * 2014-09-26 2014-12-31 中国科学院微电子研究所 一种阻变存储器读出电路
US20190108890A1 (en) * 2016-10-26 2019-04-11 Mediatek Inc. Sense amplifier

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002230989A (ja) * 2001-01-31 2002-08-16 Mitsubishi Electric Corp 不揮発性半導体記憶装置
US7483306B2 (en) * 2007-02-02 2009-01-27 Macronix International Co., Ltd. Fast and accurate sensing amplifier for low voltage semiconductor memory
US7813166B2 (en) * 2008-06-30 2010-10-12 Qualcomm Incorporated Controlled value reference signal of resistance based memory circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1845253A (zh) * 2006-04-28 2006-10-11 清华大学 一种应用于快闪存储器的灵敏放大器电路
CN103077745A (zh) * 2012-12-24 2013-05-01 上海宏力半导体制造有限公司 存储单元的读取电路和存储器
CN104252879A (zh) * 2014-09-26 2014-12-31 中国科学院微电子研究所 一种阻变存储器读出电路
US20190108890A1 (en) * 2016-10-26 2019-04-11 Mediatek Inc. Sense amplifier

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
See also references of EP4231299A4 *
XIN JING, LU HONG: "Comparative Study on Characteristics of Two Kinds of Read Circuit in EEPROM Memory", WEICHULIJI = MICROPROCESSORS, DIANZI GONGYEBU, DONGBEI WEIDIANZI YANJIUSUO, CN, no. 6, 1 December 2015 (2015-12-01), CN , pages 22 - 25, XP055932957, ISSN: 1002-2279, DOI: 10.3969/j.issn.1002-2279.2015.06.006 *

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