JP6576510B1 - Memory device and test read / write method thereof - Google Patents

Abstract

A memory device capable of selecting a plurality of sense amplifiers in a word line within a single cycle and performing a parallel test mode and a test read / write method thereof are provided. A precharge voltage control circuit generates a first precharge voltage HFVT and a second precharge voltage HFVN, and supplies a first precharge voltage HFVT and a second precharge voltage HFVN to a bit line BLT and a complementary bit line BLN. The precharge voltage HFVN is received. During the precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are the same. In the test write detection period and the test read detection period after the precharge operation, the precharge voltage control circuit operates the bit line. The voltage levels of the first precharge voltage HFVT and the second precharge voltage HFVN provided to the BLT and the complementary bit line BLN are different. [Selection] Figure 1

Description

  The present invention relates to a semiconductor memory technology, and more particularly to a memory device that can read and write all sense circuits on a selected word line at a time in a parallel test mode and a test read / write method thereof.

  In a general semiconductor memory device, for example, a sense amplifier is configured in a DRAM, which is connected to a bit line of a memory unit array, accesses data from a selected memory unit, and amplifies the data.

  In a conventional technique, when testing a memory device, for example, in a parallel test mode, a plurality of amplifiers that normally read and write are selected at one time, but more memory units than the number of data lines (Data lines) It is not possible to select a single test at a time, and how to select a plurality of sense amplifiers in a word line and perform a parallel test mode within one cycle is currently desired to be solved. It is one of the rare issues.

  An object of the present invention is to provide a memory device capable of selecting a plurality of sense amplifiers of a word line within one cycle and performing a parallel test mode, and a test read / write method thereof.

  The present invention is coupled between a precharge voltage control circuit that generates a first precharge voltage and a second precharge voltage based on a precharge reference voltage, and a bit line and a complementary bit line, and is coupled to the bit line. Sense amplifier coupled to a precharge voltage control circuit and receiving a first precharge voltage and a second precharge voltage on a bit line and a complementary bit line, respectively. The voltage levels of the first precharge voltage and the second precharge voltage are the same during the precharge operation, and the precharge operation and the test read detection period after the precharge operation A first precharge voltage and a second precharge voltage provided to the bit line and the complementary bit line by the charge voltage control circuit. The voltage levels to provide different memory devices.

A read / write method for a memory device used for performing a test write operation and a test read operation on a memory unit, wherein a first precharge voltage and a second precharge voltage are based on a precharge reference voltage. Generating
Causing the bit line and the complementary bit line to receive a first precharge voltage and a second precharge voltage, respectively,
During the precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are the same, and the precharge voltage control circuit operates in the test write detection period and the test read detection period after the precharge operation. The voltage levels of the first precharge voltage and the second precharge voltage provided to the line and the complementary bit line provide different read / write methods.

  Based on the above, it is possible to provide a memory device that can implement a parallel test mode by selecting a plurality of sense amplifiers in a word line within one cycle, and a test read / write method thereof.

  In order to further clarify the above-described features and advantages of the present invention, detailed contents will be described below with reference to the accompanying drawings.

1 is a schematic diagram illustrating a memory device according to an embodiment of the present invention. FIG. 3 is a schematic diagram illustrating an array structure of a memory device according to an embodiment of the present invention. FIG. 3 is a block schematic diagram illustrating a control test circuit according to an embodiment of the present invention. FIG. 3 is a circuit schematic diagram illustrating a sense control circuit according to an embodiment of the present invention. 1 is a circuit schematic diagram illustrating a test read / write circuit according to an embodiment of the present invention. FIG. FIG. 5 is a waveform diagram illustrating a logic “0” and a logic “1” test write operation of a memory device according to an embodiment of the present invention. FIG. 5 is a waveform diagram illustrating a logic “0” and a logic “1” test write operation of a memory device according to an embodiment of the present invention. FIG. 5 is a waveform diagram illustrating a logic “0” and a logic “1” test write operation of a memory device according to an embodiment of the present invention. FIG. 5 is a waveform diagram illustrating a test read operation of a memory device according to an embodiment of the present invention. FIG. 5 is a waveform diagram illustrating a test read operation of a memory device according to an embodiment of the present invention. FIG. 5 is a waveform diagram illustrating a test read operation of a memory device according to an embodiment of the present invention. FIG. 6 is an operational waveform diagram illustrating a test write of logic “0” to all memory units by a memory device according to another embodiment of the present invention.

  Referring to FIG. 1, FIG. 1 is a schematic diagram illustrating a memory device according to an embodiment of the present invention. The memory circuit 100 includes a word line WL, a bit line BLT, a complementary bit line BLN, a memory unit MC, a sense amplifier circuit 110, and a control test circuit 120. The control test circuit 120 is coupled to the sense amplifier circuit 110 and provides a plurality of control signals.

  The memory unit MC includes, for example, a memory capacitor used to store a data level and a metal oxide semiconductor transistor (MOSFET) (not shown) as a switch. The first end of the MOS transistor is coupled to the capacitor, the second end is coupled to the bit line BLT, and the gate is coupled to the word line WL. Here, the plurality of memory units MC form an array array in the direction of the plurality of word lines WL, the plurality of bit lines BLT, and the plurality of complementary bit lines BLN to form the memory array 130. Further, the word line signals WLn and WLm shown in FIG. 1 represent signals on different word lines WL.

  The sense amplifier circuit 110 is used to detect data in the memory unit MC by being coupled to a pair of bit lines, that is, the bit line BLT and the complementary bit line BLN. A test write operation or a test read operation can be performed.

  The sense amplifier circuit 110 receives the first precharge voltage HFVT, the second precharge voltage HFVN, the first precharge enable signal BLP1, and the second precharge enable signal BLP2 from the control test circuit 120. The sense amplifier circuit 110 applies a first precharge voltage HFVT and a second precharge to the bit line BLT and the complementary bit line BLN, respectively, based on the first precharge enable signal BLP1 and the second precharge enable signal BLP2. The voltage level of the first precharge voltage HFVT and the second precharge voltage HFVN is the same during the precharge operation, so that the bit line BLT and the complementary bit line BLN are received. Are provided with the same voltage level, but the voltage of the first precharge voltage HFVT and the second precharge voltage HFVN provided by the control test circuit 120 in the test write detection period and the test read detection period after the precharge operation. The level is different and the first precharge enable Since the timing of switching the voltage level is different in the test write detection period and the test read detection period, the signal BLP1 differs between the bit line BLT and the complementary bit line BLN in the detection process, unlike a general memory device. The voltage difference is mainly influenced by the data emitted from the memory unit MC, and the voltage difference between the bit line BLT and the complementary bit line BLN in this embodiment is the first precharge voltage HFVT and the second precharge. Associated with the voltage difference between the voltages HFVN. The following examples are described in more detail.

  The sense amplifier circuit 110 includes a first switch T1, a second switch T2, a third switch T3, and a sense circuit SA, and includes a first switch T1, a second switch T2, and a second switch T2. Here, the third switch T3 is an n-channel transistor, but is not limited thereto. The first end (drain) of the first switch T1 receives the first precharge voltage HFVT, the second end (source) is coupled to the bit line BLT, and the gate end is the first precharge enable. A signal BLP1 is received to determine whether to conduct. The first end (drain) of the second switch T2 receives the second precharge voltage HFVN, the second end (source) is coupled to the complementary bit line BLN, and the gate end is similarly the first The precharge enable signal BLP1 is received to determine whether or not to conduct. The third switch T3 is coupled between the bit line BLT and the complementary bit line BLN, and the gate terminal receives the second precharge enable signal BLP2.

  Sense circuit SA is coupled between bit line BLT and complementary bit line BLN, and is connected between bit line BLT and complementary bit line BLN based on p-channel control voltage SAP and n-channel control voltage SAN received from sense amplifier circuit 120. It is used to increase the voltage difference of. In the present embodiment, the sense circuit SA is implemented so as to be connected to the flip-flop of the positive feedback path by a CMOS inverter including two MOS transistors Q1 and Q2 and a CMOS inverter including two MOS transistors Q3 and Q4.

  The first ends (here, the sources) of the transistors Q1 and Q3 of the sense circuit SA are coupled to the first intermediate node N1, which receives the p-channel control voltage SAP, The second ends of Q2 and Q4 (here the source) are coupled to a second intermediate node N2, which receives the n-channel control voltage SAN. The other ends (here, drains) of the transistors Q1 and Q2 of the sense circuit SA and the gates of the transistors Q3, Q4 are coupled to the bit line BLT, and the other ends (here, drains) of the transistors Q3 and Q4 and the transistors The gates of Q1 and Q2 are coupled to the complementary bit line BLN, so that the voltage levels of the bit line BLT and the complementary bit line BLN are raised due to the influence of the p-channel control voltage SAP and the n-channel control voltage SAN. (Pull up) or pulled down (pulled down) to represent a logical “1” or a logical “0”.

  FIG. 2 is a schematic diagram illustrating an array structure of a memory device according to an embodiment of the present invention. The embodiment of FIG. 2 can be applied to the memory device 100 of FIG. Referring to FIG. 2, the memory array 130 includes memory units MC at connection points of a plurality of word lines WL and a plurality of bit lines BLT. The X decoder block (XDEC) 140 and the Y decoder block (YDEC) 150 are memory Coupled to the array 130, it is used to select which memory unit MC to access data. The memory array 130 is coupled to a sense amplifier block 160. The sense amplifier block 160 is coupled to a control test circuit 120. The sense amplifier block 160 includes a plurality of the sense amplifier circuits 110, and the control test circuit 120 and the sense amplifier. The arrangement relation between the block 160 and the sense amplifier circuit 110 can be referred to the disclosed contents of FIG.

  FIG. 3 is a schematic block diagram illustrating a control test circuit according to an embodiment of the present invention. Referring to FIG. 3, the control test circuit 120 includes a sense control circuit 200 and a test read / write circuit 300 disposed in the vicinity of the sense control circuit 200. The sense control circuit 200 and the test read / write circuit 300 are both coupled to the sense amplifier circuit 110, and the first precharge enable signal BLP1, the second precharge enable signal BLP2, the p channel control voltage SAP, and the n channel control, respectively. A voltage SAN, a first precharge voltage HFVT, and a second precharge voltage HFVN are provided. In the test mode, the test read / write circuit 300 generates a test result TFAIL based on a comparison result between one of the first precharge voltage HFVT and the second precharge voltage HFVN and the test reference voltage TMREF, It is determined whether or not the memory unit MC has a defect. The following example describes in detail a mechanism for determining whether a memory unit MC is defective.

  FIG. 4 is a schematic circuit diagram illustrating a sense control circuit according to an embodiment of the present invention. Referring to FIG. 4, in this embodiment, the sense control circuit 200 includes a precharge enable control circuit 210 and a sense amplification voltage control circuit 220. The precharge enable control circuit 210 is formed by connecting inverters INV21 to INV26 and a NAND gate NA21, for example.

  Specifically, the input terminal of the inverter INV21 receives the precharge enable signal BLPE1, and the precharge enable signal BLPE1 is used to determine when to precharge the bit line BLT and the complementary bit line BLN. The output terminal is coupled to one input terminal of the NAND gate NA21, the other input terminal of the NAND gate NA21 receives the row address signal X12B13B, and the row address signal X12B13B operates which word line WL. The output terminal of the NAND gate NA21 is coupled to the input terminal of the inverter INV22, the inverter INV22 and the inverter INV23 are connected in series, and the inverter INV23 is the first precharge enable. Signal BLP1 Forces. The inverter INV24, the inverter INV25, and the inverter INV26 are connected in series, the inverter INV24 receives the row address signal X12B13B, and the inverter INV26 outputs the second precharge enable signal BLP2.

  Accordingly, the precharge enable control circuit 210 is coupled to the sense amplifier circuit 110 and generates the first precharge enable signal BLP1 and the second precharge enable signal BLP2 based on the precharge enable signal BLPE1 and the row address signal X12B13B. And provided to the sense amplifier circuit 110. When a test write operation and a test read operation are performed on the memory unit MC, the precharge enable control circuit 210 can control the first precharge enable signal BLP1 to switch the voltage level, and the second precharge enable signal BLP1. The logic level of the charge enable signal BLP2 is different from that of the first precharge enable signal BLP1, and after the test write operation and test read operation are completed, the precharge enable control circuit 210 sets the voltage level of the second precharge enable signal BLP2. By switching, the logic level of the first precharge enable signal BLP1 is restored to the same level.

  The sense amplification voltage control circuit 220 includes inverters INV27 to INV29, NAND gate NA22 and NAND gate NA23, and switches Q21 to Q25, and the switches Q21 to Q25 are implemented by a transistor method. The voltage levels of the SAP output node NP and the SAN output node NN are switched among the precharge reference voltage HFV, the power supply voltage VDD, and the ground voltage VSS, respectively. The SAP output node NP and the SAN output node NN can output the p-channel control voltage SAP and the n-channel control voltage SAN.

  Specifically, the NAND gates NA22 and NA23 receive the row address signal X12B13B, the other input terminals receive the sense enable signals SE1 and SE2, respectively, and the NAND gate NA22, the inverter INV27, and the inverter INV28 are serially connected in order. Connected, the switch Q21 is controlled by the output signal of the inverter INV28, the first end receives the power supply voltage VDD, the second end is coupled to the SAP output node NP, and the p-channel control voltage SAP is supplied to the power supply voltage. Used to pull up to VDD.

  The NAND gate NA23 and the inverter INV29 are connected in series, the switch Q22 is controlled by the output signal of the inverter INV29, the first end is coupled to the SAN output node NN, the second end is coupled to the ground voltage VSS, Used to lower the n-channel control voltage SAN to the ground voltage VSS.

  The switches Q23, Q24, and Q25 are all controlled by the second precharge enable signal BLP2, and the first ends of the switches Q24 and Q25 receive the precharge reference voltage HFV, and the precharge reference voltage HFV is The voltage value of the precharge reference voltage HFV is generally half of the power supply voltage VDD. The second end of the switch Q24 is coupled to the first end of the switch Q23, and the second end of the switch Q25 is coupled to the SAP output node NP, and the second end of the switch Q23 is coupled to the SAN output node NN. Is done. The switches Q23 to Q25 are enabled periods of the second precharge enable signal BLP2 (for example, the switches Q23 to Q25 are n-channel transistors here, and therefore the second precharge enable signal BLP2 The enable period is in a high level state), and is used to restore the voltage levels of the p-channel control voltage SAP and the n-channel control voltage SAN to the precharge reference voltage HFV.

  FIG. 5 is a schematic circuit diagram illustrating a test read / write circuit according to an embodiment of the present invention. Referring to FIG. 5, the test read / write circuit 300 includes a precharge voltage control circuit 310 and a test comparison circuit 320, and the precharge voltage control circuit 310 is coupled to the test comparison circuit 320 and the sense amplifier circuit 110. For example, the precharge voltage control circuit 310 includes inverters INV31 to INV33, NAND gates NA31 to NA33, NOR gates NO31 and NO32, switches Q31 to Q36, and transmission gates TG31 to TG34. Test comparison circuit 320 includes a comparator 312, inverters INV34 and INV35, NAND gates NA34 and NA35, a NOR gate NO33, and switches Q37 to Q39. In the present embodiment, the switches Q31 to Q39 and the transmission gates TG31 to TG34 are implemented by a CMOS transistor method, but are not limited thereto.

  In this embodiment, the test comparison circuit 320 further includes a latch circuit (latch) 314. However, this is not always necessary, and in another embodiment, the test comparison circuit 320 may not include the latch circuit 314.

  Specifically, the NAND gate NA31 of the precharge voltage control circuit 310 receives the row address signal X12B13B and the test enable signal TEST, and the output terminal of the NAND gate NA31 has n terminals of the inverter INV31, the transmission gate TG31, and the transmission gate TG32. The output terminal of the inverter INV31 is coupled to the p-channel gates of the transmission gate TG31 and the transmission gate TG32, one end of the transmission gate TG31 and the transmission gate TG32 receives the precharge reference voltage HFV, and the other end Are coupled to HFVT output node NHT and HFVN output node NHN, respectively, and HFVT output node NHT and HFVN output node NHN are respectively connected to first precharge voltage HFVT and second precharge voltage HFVN. Providing the sense amplifier circuit 110. Here, the transmission gate TG31 and the transmission gate TG32 are turned on or off at the same time, and when turned on, the HFVT output node NHT and the HFVN output node NHN receive the precharge reference voltage HFV at the same time.

  The inverter INV32 receives the test data signal TDA, and its output terminal is coupled to one input terminal of the p-channel gate of the transmission gate TG33, the n-channel gate of the transmission gate TG34, the input terminal of the inverter INV33, and the NOR gate NO31. Is done. The output terminal of the inverter INV33 is coupled to one input terminal of the n-channel gate of the transmission gate TG33, the p-channel gate of the transmission gate TG34, and the NOR gate NO32. One end of each of the transmission gate TG33 and the transmission gate TG34 is coupled to the HFVT output node NHT and the HFVN output node NHN, respectively, and the other end is commonly coupled to the inverting input terminal of the comparator 312 of the test comparison circuit 320, and the first precharge One of the voltage HFVT and the second precharge voltage HFVN is used to provide the comparator 312.

  The NAND gate NA32 receives the row address signal X12B13B and the test data line precharge signal TPIO, and the output terminal controls whether the switch Q35 and the switch Q36 are conductive, and the first of the switches Q35 and Q36. One end receives power supply voltage VDD, the second end of switch Q35 is coupled to HFVN output node NHN, and the second end of switch Q36 is coupled to HFVT output node NHT. Therefore, the voltage values of the first precharge voltage HFVT and the second precharge voltage HFVN are raised to the power supply voltage VDD during the enable period of the test data line precharge signal TPIO (here, for example, in a high level state). .

  NAND gate NA33 receives row address signal X12B13B and test write enable signal TWE, and its output end is coupled to the other input ends of NOR gate NO31 and NOR gate NO32. The output terminal of the NOR gate NO31 controls whether the switch Q31 and the switch Q34 are conductive, and the output terminal of the NOR gate NO32 controls whether the switch Q32 and the switch Q33 are conductive. One end receives the power supply voltage VDD, the second end is coupled to the first end of the switch Q32 and the HFVT output node NHT, and the second end of the switch Q32 is coupled to the ground voltage VSS. The precharge voltage HFVT can be set to a voltage obtained by subtracting the critical voltage of the switch Q31 from the ground voltage VSS or the power supply voltage VDD, and the first end of the switch Q33 receives the power supply voltage VDD, The end is coupled to the first end of the switch Q34 and the HFVN output node NHN, and the second end of the switch Q34 is connected to the ground voltage VSS. Together is, therefore, the voltage level of the second precharge voltage HFVN, may be a voltage obtained by subtracting the threshold voltage of the switch Q33 from the ground voltage VSS or the power supply voltage VDD.

  Therefore, the precharge voltage control circuit 310 generates the first precharge voltage HFVT and the second precharge voltage HFVN based on the precharge reference voltage HFV, and generates the test write enable signal TWE and the test data signal TDA. Further, the first precharge voltage HFVT and the second precharge voltage HFVN are changed to the power supply voltage VDD, the voltage obtained by subtracting the critical voltage of the transistor from the power supply voltage VDD, the ground voltage VSS, or the precharge reference voltage HFV. be able to.

  Specifically, the NAND gate NA34 of the test comparison circuit 320 receives the row address signal X12B13B and the test data enable signal TDE, and outputs them to the inverter INV34. The output terminal of the inverter INV34 is the input terminal of the inverter INV35 and the NAND gate. The output terminal of the inverter INV35 is coupled to one input terminal of the NOR gate NO33. The non-inverting input terminal of the comparator 312 receives the test reference voltage TMREF, and the inverting input terminal is one of the first precharge voltage HFVT and the second precharge voltage HFVN from the transmission gate TG33 or the transmission gate TG34. The output terminal of the comparator 312 is coupled to the other input terminal of the NAND gate NA35 and the NOR gate NO33. Here, the test reference voltage TMREF is an initially set constant voltage value, and the voltage value is larger than ½ of the power supply voltage VDD or higher than the precharge reference voltage HFV and smaller than the power supply voltage VDD. The test reference voltage TMREF is 3/4 of the power supply voltage VDD.

  The switch Q37 is controlled by the output result of the control by the NAND gate NA35, the first end is coupled to the power supply voltage VDD, the second end is coupled to the test node NT, and the test node NT outputs the test result TFAIL. . Switch Q38 is controlled by the output result of NOR gate NO33, with the first end coupled to test node NT and the second end coupled to ground voltage VSS. Therefore, the voltage level of the test result TFAIL becomes the power supply voltage VDD or the ground voltage VSS depending on the output result of the comparator 312.

  The first end of the switch Q39 is also coupled to the test node NT, the second end is coupled to the ground voltage VSS, and is controlled by the test data line precharge signal TPIO to enable the test data line precharge signal TPIO. , The voltage level of the test result TFAIL is lowered to the ground voltage VSS. Latch circuit 314 is also coupled to test node NT and is used to latch the voltage level of test result TFAIL.

  Briefly, the test comparison circuit 320 compares one of the first precharge voltage HFVT and the second precharge voltage HFVN and the test reference voltage TMREF to generate a test result TFAIL, and It is determined whether or not the unit MC has a defect, and when one of the first precharge voltage HFVT and the second precharge voltage HFVN is higher than the test reference voltage TMREF, the test result TFAIL is, for example, the power supply voltage Substantially equal to one of VDD and ground voltage VSS, indicating that the data detection of the memory unit MC is successful, and both the first precharge voltage HFVT and the second precharge voltage HFVN are tested. When smaller than the reference voltage TMREF, the test result TFAIL is, for example, the power supply voltage VDD Other substantially equal among the fine ground voltage VSS, represents that the data detected in the memory unit MC has failed. In the following embodiment, an implementation method for determining whether or not the test read / write and the memory unit MC have defects will be described in more detail.

  Subsequently, referring to FIGS. 6 to 8, FIGS. 6 to 8 are waveform diagrams respectively illustrating test write operations of logic “0” and logic “1” of the memory device according to the embodiment of the present invention. . The operations shown in FIGS. 6 to 8 can be applied to the embodiment shown in FIGS. In the test write operation, taking any one memory unit MC as an example, FIG. 6 shows a word line signal WLn, a test write enable signal TWE, sense enable signals SE1, SE2, and a first precharge in the corresponding word line WL. The operation waveform diagram of the enable signal BLP1 and the second precharge enable signal BLP2 is shown. FIG. 7 shows a test write operation when the write data is logic “0”, the first precharge voltage HFVT, the second precharge voltage HFVN, the p channel control voltage SAP, the n channel control voltage SAN, and the bit line BLT. Also, an operation waveform diagram of the voltage level of the complementary bit line BLN is shown. In particular, the thin straight lines described in FIG. 7 and FIG. 8 that are described with different symbols represent the waveform behavior in FIG. 6 and are not labeled to avoid cluttering the drawings. However, those skilled in the art can know the meaning of these thin straight lines from FIG.

  First, referring to FIG. 6 and FIG. 7 in combination with FIG. 1 to FIG. 5, the first precharge voltage HFVT and the second precharge voltage HFVN are set to the transmission gate TG31 and the transmission gate TG32 before performing the test. Is conducted and maintained at the magnitude of the voltage value of the precharge reference voltage HFV. In the test write operation, in particular, in the test write detection period tW, the voltage value of one of the first precharge voltage HFVT and the second precharge voltage HFVN is lower than the power supply voltage VDD, but the precharge reference voltage HFV The higher voltage value is lower than the precharge reference voltage HFV and is substantially equal to the ground voltage VSS, for example.

  First, in the case where data representing logic “0” is to be written to the memory unit MC, the test data signal TDA is set to the low level, and at this time, the word line signal WLn and the test write enable are set. Since the voltage of the signal TWE is in a high level state, the switches Q31 and Q34 are cut off and the switches Q32 and Q33 are turned on. Here, the switches Q31 to Q34 are all n-channel transistors as an example. Without limitation, the voltage of the first precharge voltage HFVT provided by the precharge voltage control circuit 310 is lowered to the ground voltage VSS, and the second precharge voltage HFVN is used to reduce the critical voltage VTN of the n-channel transistor from the power supply voltage VDD. Raised to the magnitude of the pulled voltage. It is necessary to explain that the voltage value of the power supply voltage VDD is larger than the sum of the precharge reference voltage HFV and the critical voltage VTN.

  Subsequently, the precharge enable control circuit 210 switches the first precharge enable signal BLP1 from the original low level state to the high level state, while the second precharge enable signal BLP2 maintains the low level state, The first switch T1 and the second switch T2 are turned on and the third switch T3 is disconnected, and the bit line BLT and the complementary bit line BLN are connected to the first precharge voltage HFVT and the second precharge voltage HFVN, respectively. Can be received.

  In particular, in this embodiment, when a test write operation is performed on the memory unit MC, and before the first precharge enable signal BLP1 is switched to the enable state, that is, the first switch T1 and Before the second switch T2 becomes conductive, the voltage levels of the first precharge voltage HFVT and the second precharge voltage HFVN are already different.

  Subsequently, the sense amplification voltage control circuit 220 switches the p-channel control voltage SAP and the n-channel control voltage SAN from the precharge reference voltage HFV to the power supply voltage VDD and the ground voltage VSS, respectively. The voltage levels of the p-channel control voltage SAP and the n-channel control voltage SAN are originally maintained lower than the power supply voltage VDD, and are the same as the precharge reference voltage HFV here, and in the enable period of the sense enable signals SE1 and SE2, The switches Q21 and Q22 are turned on, and the p-channel control voltage SAP and the n-channel control voltage SAN are switched to the power supply voltage VDD and the ground voltage VSS, respectively, so that the voltage difference between the bit line BLT and the complementary bit line BLN is increased. Therefore, in the test write detection period tW, the voltage level of the bit line BLT is substantially equal to the ground voltage VSS, the voltage level of the complementary bit line BLN is the power supply voltage VDD, and the logic “ Data representing “0” is saved.

  Subsequently, referring to FIGS. 6 and 8 together with FIGS. 1 to 5, FIG. 8 shows a test write operation when writing data of logic “1”, the first precharge voltage HFVT, Operation waveform diagrams of the second precharge voltage HFVN, the p-channel control voltage SAP, and the n-channel control voltage SAN are shown. In the test write operation, for example, when data representing logic “1” is written to the memory unit MC, the test data signal TDA is set to the high level state, and the precharge voltage is set in the test write detection period tW. The voltage value of the first precharge voltage HFVT output from the control circuit 310 is raised to a voltage level obtained by subtracting the critical voltage VTN of the n-channel transistor from the power supply voltage VDD, and the voltage level of the second precharge voltage HFVN Is reduced to ground voltage VSS, and detailed implementation schemes can be obtained by those skilled in the art from the above embodiments and general techniques, and will not be repeated here.

  FIGS. 9-11 are waveform diagrams each illustrating a test read operation of a memory device according to an embodiment of the present invention. The operation shown in FIGS. 9 to 11 can be applied to the embodiment shown in FIGS. 9 to 11 together with FIGS. 1 to 5, when any one memory unit MC is taken as an example in the test read operation, FIG. 9 shows the word line signal WLn, the sense enable signals SE 1 and SE 2. FIG. 5 shows operation waveform diagrams of the test data line precharge signal TPIO, the test data enable signal TDE, the first precharge enable signal BLP1, and the second precharge enable signal BLP2. 10 and 11 show the first precharge voltage HFVT, the second precharge voltage HFVN, the p-channel control voltage SAP, and the n-channel control voltage SAN when it is determined that the read result of the test read operation is successful and unsuccessful, respectively. FIG. 5 shows operation waveform diagrams of voltage levels of the bit line BLT and the complementary bit line BLN. In particular, the thin straight lines described in FIG. 10 and FIG. 11 that are described with different symbols represent the waveform behavior in FIG. 9 and are not labeled so that the drawings do not become cluttered. However, those skilled in the art can know the meaning of these thin straight lines from FIG.

  First, referring to FIGS. 9 and 10, the first precharge voltage HFVT and the second precharge voltage HFVN are turned on before the test, and the transmission gate TG31 and the transmission gate TG32 are turned on. The voltage value of the voltage HFV is maintained.

  As an example, when performing a test read operation on the memory unit MC, the memory unit MC reads data representing logic “0”. In the high level state of the word line signal WLn, and in the test read detection period tR. Before the data line precharge operation is performed, that is, in the enable period of the test data line precharge signal TPIO, the switch Q35, the switch Q36, and the switch Q39 are turned on, so that the first precharge voltage HFVT and the second The second precharge voltage HFVN is first pulled up to a voltage substantially equal to the power supply voltage VDD, and the test node NT substantially receives the ground voltage VSS. Here, the switches Q35 and Q36 are p-channel transistors, and the switch Q39 is an n-channel transistor.

  After the data line precharge operation is completed, the test data line precharge signal TPIO is disabled (for example, in a low level state) and the sense enable signals SE1 and SE2 are enabled, so that the p-channel control voltage SAP and the n-channel control voltage SAN is switched from the precharge reference voltage HFV to the power supply voltage VDD and the ground voltage VSS, respectively.

  Subsequently, the first precharge enable signal BLP1 is switched from the original low level state to the high level state, and the second precharge enable signal BLP2 is maintained in the low level state. The first precharge enable signal BLP1 switched to the high level state makes the first switch T1 and the second switch T2 conductive, and both the data of the memory unit MC in the same word line WL are successfully detected. In the test read detection period tR, the voltage levels of the first precharge voltage HFVT and the second precharge voltage HFVN are different, and one of the first precharge voltage HFVT and the second precharge voltage HFVN. Is maintained at the power supply voltage VDD and the other voltage level is pulled down to a voltage substantially equal to the ground voltage VSS. In the embodiment of FIG. 9, the second precharge voltage HFVN is the power supply voltage VDD. And the first precharge voltage HFVT is pulled down to the ground voltage VSS. Rukoto the as an example.

  In particular, in the test write operation and the test read operation, the first precharge enable signal BLP1 has a different timing for switching from the low level state to the high level state. Specifically, the first precharge enable signal When the BLP1 performs a test write operation, the timing for switching the voltage level is earlier than the timing for performing the test read operation. In the test write operation, the first precharge enable signal BLP1 is switched to the high level earlier than the sense enable signals SE1 and SE2, whereas in the test read operation, the first precharge enable signal BLP1 is switched to the sense enable signal SE1 and Switch to the high level state later than SE2.

Subsequently, the comparator 312 receives one of the test reference voltage TMREF, the first precharge voltage HFVT, and the second precharge voltage HFVN, for example, one having a high voltage level. The comparator 312 receives the test reference voltage TMREF and the second precharge voltage HFVN, the voltage value of the test reference voltage TMREF is set to 3/4 of the power supply voltage VDD, and the second precharge voltage HFVN is Is substantially equal to the power supply voltage VDD. In the test read detection period tR, since the second precharge voltage HFVN is higher than the test reference voltage TMREF, the test result TFAIL is set to a low level, for example, substantially equal to the ground voltage VSS, and the same word Any data of the memory unit MC on the line WL is successfully detected.

  Referring to FIGS. 9 and 11, when a data detection failure occurs in the memory unit MC in the same word line WL, the first precharge enable signal BLP1 is switched to the high level state, and the first switch T1 and Since the voltage value is lowered to the ground voltage VSS after the second switch T2 is turned on, the signal that is originally in the high level state among the first precharge voltage HFVT and the second precharge voltage HFVN is Less than the voltage level.

  In the present embodiment, the second precharge voltage HFVN is originally in a high level state, the voltage value is substantially equal to the power supply voltage VDD, and the magnitude of the voltage value of the first precharge voltage HFVT is , Substantially equal to the ground voltage VSS. In the test read detection period tR, after the first switch T1 and the second switch T2 are turned on, the first precharge voltage HFVT is equal to the ground voltage VSS, but the voltage of the second precharge voltage HFVN is , The voltage of the second precharge voltage HFVN is a voltage obtained by subtracting the critical voltage VTN of the n-channel transistor from the power supply voltage VDD. In the embodiment, the power supply voltage VDD is 1.5V, and the critical voltage VTN of the n-channel transistor is 0.7V. Therefore, the reduced voltage of the second precharge voltage HFVN is the power supply voltage. It is about 1/2 the size of VDD.

  Subsequently, the comparator 312 receives and compares the test reference voltage TMREF and the second precharge voltage HFVN, and the voltage value of the test reference voltage TMREF is set to 3/4 of the initially set power supply voltage VDD. Since the voltage value of the second precharge voltage HFVN at this time is equal to about 1/2 of the power supply voltage VDD and smaller than the test reference voltage TMREF, the test result TFAIL is changed to a high voltage level, for example, , Which is substantially equal to the power supply voltage VDD and represents a state in which detection of data in the memory unit MC in the same word line WL has failed.

  9 to 11, when a test read operation is performed on the memory unit MC, one of the first precharge voltage HFVT and the second precharge voltage HFVN in the test read detection period tR. Is not higher than the power supply voltage VDD, but is higher than the precharge reference voltage HFV, and the other voltage value is lower than the precharge reference voltage HFV, for example, equal to the ground voltage VSS.

  In another embodiment, the first precharge voltage HFVT is in a high level state, and the comparator 312 may receive and compare the test reference voltage TMREF and the first precharge voltage HFVT, Detailed implementations can be fully learned from the above description and general techniques by those skilled in the art and will not be repeated here.

  Referring to FIG. 12, FIG. 12 is an operational waveform diagram illustrating a test write of logic “0” to all memory units by a memory device according to another embodiment of the present invention. This embodiment can be applied to the memory device 100 of the embodiment shown in FIGS. In the embodiment of FIG. 12, after the memory device 100 is powered on (Power up) or reset (RESET), the memory device 100 is within an extended write cycle T, eg, within a range of less than 200 μs to 300 μs. In the embodiment of FIG. 12, taking the extended write cycle T as about 300 μs as an example, a write operation is performed on all word lines WL and all associated sense amplifier circuits 110 in the memory device 100, and The reference numerals omitted in FIG. 12 represent this. That is, the memory device 100 of the present invention writes logic “0” data to the memory units MC in all the word lines WL within a short time. Those skilled in the art will be able to obtain sufficient teaching and presentation from the embodiments of FIGS. 6-8 regarding the manner of implementation of the operating waveforms of FIG. 12, and will not be repeated here.

  As described above, the present invention provides a memory device including a precharge voltage control circuit and a sense amplifier circuit. The precharge voltage control circuit generates a first precharge voltage and a second precharge voltage based on the precharge reference voltage. A sense amplifier is coupled between the bit line and the complementary bit line, is used to detect data in the memory unit coupled to the bit line, and is coupled to a precharge voltage control circuit, during a precharge operation. The voltage levels of the first precharge voltage and the second precharge voltage are the same. In the test write detection period and the test read detection period after the precharge operation, the precharge voltage control circuit operates the bit line and the complementary bit line. The voltage levels of the first precharge voltage and the second precharge voltage are different from each other. As described above, it is possible to realize a parallel test mode by selecting a plurality of sense amplifiers in a word line within one cycle.

  Although the text is shown as the above embodiments, it is not intended to limit the present invention, but can be changed or modified by those skilled in the art without departing from the spirit of the present invention. The scope of protection of the invention is based on what is limited in the scope of patent claims.

  The detector provided by the present invention completes the detection operation of the data bus inversion function with low power consumption. In the memory device, the efficiency of the data bus inversion function is effectively improved. In addition, the data access efficiency of the electronic device described in the memory device is also effectively improved.

100: memory circuit 110: sense amplifier circuit 120: control test circuit 130: memory array 140: X decoder block 150: Y decoder block 160: sense amplifier block 200: sense control circuit 210: precharge enable control circuit 220: sense amplification voltage Control circuit 300: Test read / write circuit 310: Precharge voltage control circuit 312: Comparator 314: Latch circuit 320: Test comparison circuit BLT: Bit line BLN: Complementary bit line BLPE1: Precharge enable signal BLP1: First precharge enable Signal BLP2: second precharge enable signal HFV: precharge reference voltage HFVT: first precharge voltage HFVN: second precharge voltage INV: inverter MC: memory unit N1 First intermediate node N2: Second intermediate node NP: SAP output node NN: SAN output node NHT: HFVT output node NHN: HFVN output node NT: Test nodes NA21 to NA23, NA31 to NA35: NAND gates NO31 to NO33: NOR gates Q1, Q2, Q3, Q4: transistors Q21 to Q25, Q1 to Q39: switch SA: sense circuits SE1, SE2: sense enable signal SAP: p channel control voltage SAN: n channel control voltage T: extended write cycle T1: First switch T2: Second switch T3: Third switch TFAIL: Test results TG31 to TG34: Transmission gate TWE: Test write enable signal TDA: Test data signal TDE: Test data enable signal TEST: Test enable Signal TPIO: test data line precharge signal tR: test read detection period tW: test write detection period TMREF: test reference voltage VDD: power supply voltage VSS: ground voltage VTN: critical voltage of n-channel transistors WL: word lines WLn, WLm : Word line signal X12B13B: Row address signal

Claims (14)

A precharge voltage control circuit for generating a first precharge voltage and a second precharge voltage based on the precharge reference voltage;
Coupled between a bit line and a complementary bit line, used to detect data of a memory unit coupled to the bit line, coupled to the precharge voltage control circuit, coupled to the bit line and the complementary bit line; A sense amplifier circuit for receiving the first precharge voltage and the second precharge voltage, respectively.
During the precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are the same, and in the test write detection period and the test read detection period after the precharge operation, the precharge voltage the voltage level of the first pre-charge voltage and the second precharge voltage control circuit is provided to the bit line and the complementary bit line varies,
And a test comparison circuit coupled to the precharge voltage control circuit and configured to compare one of the first precharge voltage and the second precharge voltage and a test reference voltage to generate a test result. ,
When one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, the test result indicates that the data detection of the memory unit is successful; When both the precharge voltage and the second precharge voltage are lower than the test reference voltage, the test result indicates that the data detection of the memory unit has failed . The sense amplifier circuit includes:
A first end receives the first precharge voltage and a second end is coupled to the bit line and is controlled by a first precharge enable signal;
A first end receiving the second precharge voltage; a second end coupled to the complementary bit line; and a second switch controlled by the first precharge enable signal;
A third switch coupled between the bit line and the complementary bit line and controlled by a second precharge enable signal;
The memory device of claim 1, further comprising: a sense circuit coupled between the bit line and the complementary bit line and used to increase a voltage difference between the bit line and the complementary bit line. A precharge enable control circuit coupled to the sense amplifier circuit and generating the first precharge enable signal and the second precharge enable signal based on a precharge enable signal;
When performing a test write operation and a test read operation on the memory unit, the voltage level of the first precharge enable signal is switched, and the logic level of the second precharge enable signal is changed to the first precharge enable signal. Unlike the enable signal, after the test write operation and the test read operation, the voltage level of the second precharge enable signal is switched and recovered to the same level as the logic level of the first precharge enable signal. The memory device according to claim 2. The memory device according to claim 1, wherein a voltage level of the test reference voltage is higher than the precharge reference voltage and lower than a power supply voltage. When one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, the voltage value of the test result is substantially equal to one of the power supply voltage and the ground voltage. When both the first precharge voltage and the second precharge voltage are smaller than the test reference voltage, the voltage value of the test result is substantially equal to the other of the power supply voltage and the ground voltage. The memory device according to claim 4, which is equal to: In the test write detection period, one voltage value of the first precharge voltage and the second precharge voltage is lower than the power supply voltage but higher than the precharge reference voltage, and the other voltage value is The memory device of claim 1, lower than the precharge reference voltage. When performing the test read operation on the memory unit, before performing the test read detection, the first precharge voltage and the second precharge voltage are first voltages substantially equal to a power supply voltage. The memory device of claim 1, wherein the memory device is pulled up. A read / write method for a memory device used to perform a test write operation and a test read operation on a memory unit,
  Generating a first precharge voltage and a second precharge voltage based on the precharge reference voltage;
Allowing the bit line and the complementary bit line to receive the first precharge voltage and the second precharge voltage, respectively,
During the precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are the same, and the precharge voltage control is performed in the test write detection period and the test read detection period after the precharge operation. The voltage levels of the first precharge voltage and the second precharge voltage (HFVN) that the circuit provides to the bit line and the complementary bit line are different,
Comparing one of the first precharge voltage and the second precharge voltage and a test reference voltage to generate a test result;
When one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, the test result indicates that the data detection of the memory unit is successful; When both the precharge voltage and the second precharge voltage are lower than the test reference voltage, the test result indicates that the data detection of the memory unit has failed. The first switch and the second switch are controlled by a first precharge enable signal, and the bit line and the complementary bit line are connected to the first precharge voltage and the second precharge, respectively. Determining whether to receive the voltage;
Controlling a third switch with a second precharge enable signal to determine whether to electrically connect the bit line and the complementary bit line;
The read / write method according to claim 8, further comprising increasing a voltage difference between the bit line and the complementary bit line by a sense circuit. Generating the first precharge enable signal and the second precharge enable signal based on a precharge enable signal;
When performing the test write operation and the test read operation on the memory unit, the voltage level of the first precharge enable signal is switched, and the logic level of the second precharge enable signal is the first level. Unlike the precharge enable signal, the voltage level of the second precharge enable signal is switched to the same level as the logic level of the first precharge enable signal after completion of the test write operation and the test read operation. The reading and writing method according to claim 9, wherein the reading and writing method is restored. The read / write method according to claim 8, wherein a voltage level of the test reference voltage is higher than the precharge reference voltage and lower than a power supply voltage. When one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, the voltage value of the test result is substantially equal to one of the power supply voltage and the ground voltage. When both the first precharge voltage and the second precharge voltage are smaller than the test reference voltage, the voltage value of the test result is substantially equal to the other of the power supply voltage and the ground voltage. The reading and writing method according to claim 11, which is equal to: In the test write detection period, one voltage value of the first precharge voltage and the second precharge voltage is lower than the power supply voltage but higher than the precharge reference voltage, and the other voltage value is 9. The read / write method according to claim 8, wherein the read / write method is lower than the precharge reference voltage. When performing the test read operation on the memory unit, before performing the test read detection, the first precharge voltage and the second precharge voltage are first voltages substantially equal to a power supply voltage. The reading and writing method according to claim 8, wherein