KR102167831B1 - Memory device and method for test reading and writing thereof - Google Patents

Abstract

<purpose>
The present invention provides a memory device and a test read/write method thereof.
<Solution>
The precharge voltage control circuit generates a first precharge voltage and a second precharge voltage based on the precharge reference voltage. The sense amplification circuit is coupled between the bit line and the complementary bit line and is used to detect data of the memory unit coupled to the bit line, while coupled to the precharge voltage control circuit, the bit line and the complementary bit line. , A first precharge voltage and a second precharge voltage are received. During the precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are the same, and in the test write detection period and the test read detection period after the precharge operation, the precharge voltage control circuit is The voltage levels of the first precharge voltage and the second precharge voltage provided to the line are different.

Description

Memory device and its test read and write method {MEMORY DEVICE AND METHOD FOR TEST READING AND WRITING THEREOF}

The present invention relates to a semiconductor memory technology, and in particular, to a memory device capable of reading and writing all sense circuits on a selected word line at once in a parallel test mode, and a test read and write method thereof. will be.

In a typical semiconductor memory device, for example, a sense amplifier is configured in a DRAM, connected to a bit line of a memory unit array, and amplifying data by accessing data from a selected memory unit.

In the prior art, when performing a test on a memory device, for example, in the parallel test mode, a plurality of amplifiers that normally read and write are selected at once, but more memory than the number of data lines Since the unit cannot be selected and tested at a time, how to select multiple sense amplifiers on the word line within one cycle and perform the parallel test mode is a problem that needs to be solved. It has become one of them.

An object of the present invention is to provide a memory device capable of performing a parallel test mode by selecting a plurality of sense amplifiers of a word line within one cycle, and a test read/write method thereof.

The present invention provides a precharge voltage control circuit for generating a first precharge voltage and a second precharge voltage based on the precharge reference voltage, and a memory coupled between the bit line and the complementary bit line, and coupled to the bit line. It is used to detect the data of the unit, is coupled to the precharge voltage control circuit, and includes a sense amplification circuit for receiving a first precharge voltage and a second precharge voltage, respectively, in the bit line and the complementary bit line, and precharge During operation, the voltage levels of the first precharge voltage and the second precharge voltage are the same, and in the test write detection period and the test read detection period after the precharge operation, the precharge voltage control circuit is provided to the bit line and the complementary bit line. The voltage levels of the first precharge voltage and the second precharge voltage are different to provide a memory device.

A read/write method for a memory device, which is used to perform a test write operation and a test read operation on a memory unit, and generates a first precharge voltage and a second precharge voltage based on a precharge reference voltage,

Receiving a first precharge voltage and a second precharge voltage, respectively, to the bit line and the complementary bit line,

During the precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are the same, and in the test write detection period and the test read detection period after the precharge operation, the precharge voltage control circuit is a bit line and a complementary bit line. The voltage levels of the first precharge voltage and the second precharge voltage provided to provide different read/write methods.

Based on the above, it is possible to provide a memory device capable of realizing the selection of a plurality of sense amplifiers in a word line within one cycle and performing a parallel test mode, and a test read/write method thereof.

In order to further clarify the above-described features and advantages of the present invention, a detailed description will be given below with reference to the drawings by illustrating embodiments.

1 is a schematic diagram showing a memory device based on an embodiment of the present invention.
Fig. 2 is a schematic diagram showing an array structure of a memory device based on an embodiment of the present invention.
3 is a block schematic diagram showing a control test circuit based on an embodiment of the present invention.
4 is a circuit schematic diagram showing a sense control circuit based on an embodiment of the present invention.
Fig. 5 is a schematic circuit diagram showing a test read/write circuit based on an embodiment of the present invention.
6 to 8 are waveform diagrams showing test write operations of logic &quot;0&quot; and logic &quot;1&quot;
9 to 11 are waveform diagrams each showing a test read operation of a memory device according to an embodiment of the present invention.
12 is an operational waveform diagram showing test writes of logic &quot;0&quot; to all memory units by a memory device based on another embodiment of the present invention.

Referring to Fig. 1, Fig. 1 is a schematic diagram showing a memory device based on an embodiment of the present invention. The memory circuit 100 includes a word line WL, a bit line BLT, a complementary bit line BLN, a memory unit MC, a sense amplifier circuit 110, and a control test circuit 120. The control test circuit 120 is coupled to the sense amplifier circuit 110 and provides a plurality of control signals.

The memory unit MC includes, for example, a memory capacitor used to preserve a data level and a metal oxide semiconductor transistor (Metal Oxide Semiconductor, MOSFET) (not shown in the figure) as a switch, and MOS The first end of the transistor is coupled to the capacitor, the second end is coupled to the bit line BLT, and the gate is coupled to the word line WL. Here, the plurality of memory units MC form the memory array 130 by arranging arrays in the directions of the plurality of word lines WL, the plurality of bit lines BLT, and the plurality of complementary bit lines BLN. Further, the word line signals WLn and WLm shown in Fig. 1 denote signals from other word lines WL.

The sense amplifier circuit 110 is used to detect the data of the memory unit MC by being coupled to a pair of bit lines, that is, the bit line BLT and the complementary bit line BLN, and thus, a test write operation for the memory unit MC. Alternatively, you can perform a test read operation.

The sense amplifier circuit 110 receives a first precharge voltage HFVT, a second precharge voltage HFVN, a first precharge enable signal BLP1, and a second precharge enable signal BLP2 from the control test circuit 120. The sense amplifying circuit 110 is based on the first precharge enable signal BLP1 and the second precharge enable signal BLP2, to the bit line BLT and the complementary bit line BLN, respectively, a first precharge voltage HFVT and a second precharge voltage. It is determined whether to receive the charge voltage HFVN, and during the precharge operation, the voltage levels of the first precharge voltage HFVT and the second precharge voltage HFVN are from the same, to the bit line BLT and the complementary bit line BLN, the same voltage level. However, in the test write detection period and the test read detection period after the precharge operation, the voltage levels of the first precharge voltage HFVT and the second precharge voltage HFVN provided by the control test circuit 120 are different, on the other hand, The first precharge enable signal BLP1 differs from a general memory device in that the timing of switching the voltage level is also different in the test write detection period and the test read detection period, and in the detection process, the bit line BLT and the complementary bit The voltage difference between the lines BLN is mainly influenced by the data emitted by the memory unit MC, and the voltage difference between the bit line BLT and the complementary bit line BLN in this embodiment is the first precharge voltage HFVT and the second precharge voltage. It relates to the voltage difference between the charge voltage HFVN. In the following examples, it will be described in more detail.

The sense amplification circuit 110 includes a first switch T1, a second switch T2, a third switch T3, and a sense circuit SA, and the first switch T1, the second switch T2, and the third switch T3 are , Here, an n-channel transistor is used as an example, but is not limited thereto. The first end (drain) of the first switch T1 receives the first precharge voltage HFVT, the second end (source) is coupled to the bit line BLT, and the gate end is the first precharge enable signal BLP1 Is received, it is determined whether or not it conducts. The first end (drain) of the second switch T2 receives the second precharge voltage HFVN, the second end (source) is coupled to the complementary bit line BLN, and the gate end is the same as the first precharge in It receives the enable signal BLP1 and determines whether it conducts. The third switch T3 is coupled between the bit line BLT and the complementary bit line BLN, and the gate end receives the second precharge enable signal BLP2.

The sense circuit SA is coupled between the bit line BLT and the complementary bit line BLN, and based on the p-channel control voltage SAP and the n-channel control voltage SAN received from the sense amplification circuit 120, the bit line BLT and the complementary bit line It is used to increase the voltage difference between BLNs. In this embodiment, the sense circuit SA is implemented to be connected to the flip-flop of the positive feedback path by a CMOS inverter including two MOS transistors Q1 and Q2 and a CMOS inverter including two MOS transistors Q3 and Q4.

The first stage of transistors Q1 and Q3 of the sense circuit SA (which is the source here) is coupled to a first intermediate node N1, and this first intermediate node N1 receives the p-channel control voltage SAP, and the transistors Q2 and Q4 The second stage (which is the source here) is coupled to the second intermediate node N2, and this second intermediate node N2 receives the n-channel control voltage SAN. The other ends of the transistors Q1 and Q2 of the sense circuit SA (which are drains here) and the gates of the transistors Q3 and Q4 are coupled to the bit line BLT, and the other ends of the transistors Q3 and Q4 (here, the drain) and the transistors Q1 and Q2 are The gate is coupled to the complementary bit line BLN, and thus, the voltage levels of the bit line BLT and the complementary bit line BLN are pulled up under the influence of the p-channel control voltage SAP and the n-channel control voltage SAN, or It is pulled down and can represent logic "1" or logic "0".

Fig. 2 is a schematic diagram showing an array structure of a memory device according to an embodiment of the present invention. The embodiment of FIG. 2 can be applied to the memory device 100 of FIG. 1. Referring to FIG. 2, the memory array 130 includes a memory unit MC at a connection point of a plurality of word lines WL and a plurality of bit lines BLT, and an X decoder block (XDEC) 140 and a Y decoder block (YDEC). ) 150 is coupled to the memory array 130 and is used to select which memory unit MC to perform data access to. The memory array 130 is coupled to the sense amplifier block 160, the sense amplifier block 160 is coupled to the control test circuit 120, and the sense amplifier block 160 comprises a plurality of the sense amplifier circuits ( 110), and the arrangement relationship between the control test circuit 120 and the sense amplifying circuit 110 of the sense amplifier block 160 may be referred to the disclosure of FIG. 1.

3 is a block schematic diagram showing a control test circuit based on an embodiment of the present invention. Referring to FIG. 3, the control test circuit 120 includes a sense control circuit 200 and a test read/write circuit 300 disposed in the vicinity of the sense control circuit 200. Both the sense control circuit 200 and the test read/write circuit 300 are coupled to the sense amplification circuit 110, respectively, a first precharge enable signal BLP1, a second precharge enable signal BLP2, and a p-channel control voltage. SAP, an n-channel control voltage SAN, a first precharge voltage HFVT and a second precharge voltage HFVN are provided. In the test mode, the test read/write circuit 300 generates a test result TFAIL based on the comparison result of one of the first precharge voltage HFVT and the second precharge voltage HFVN with the test reference voltage TMREF, and the memory unit It is determined whether the MC has a bad state. The following embodiment describes in detail a mechanism for determining that the memory unit MC is in a bad state.

4 is a schematic circuit diagram showing a sense control circuit based on an embodiment of the present invention. Referring to FIG. 4, in this embodiment, the sense control circuit 200 includes a precharge enable control circuit 210 and a sense amplification voltage control circuit 220. The precharge enable control circuit 210 is formed by connecting inverters INV21 to INV26 and NAND gate NA21, for example.

Specifically, the input terminal of the inverter INV21 receives the precharge enable signal BLPE1, and the precharge enable signal BLPE1 is used to determine when to precharge the bit line BLT and the complementary bit line BLN, and the output terminal Is coupled to one input of the NAND gate NA21, the other input of the NAND gate NA21 receives the low address signal X12B13B, and the low address signal X12B13B is used to select which word line WL to act on. The output terminal of the NAND gate NA21 is coupled to the input terminal of the inverter INV22, the inverter INV22 and the inverter INV23 are connected in series, and the inverter INV23 outputs the first precharge enable signal BLP1. Inverter INV24, inverter INV25, and inverter INV26 are serially connected in sequence, the inverter INV24 receives the low address signal X12B13B, and the inverter INV26 outputs the second precharge enable signal BLP2.

Accordingly, the precharge enable control circuit 210 is coupled to the sense amplification circuit 110, based on the precharge enable signal BLPE1 and the low address signal X12B13B, the first precharge enable signal BLP1 and the second precharge. The charge enable signal BLP2 is generated and provided to the sense amplifying circuit 110. When performing a test write operation and a test read operation on the memory unit MC, the precharge enable control circuit 210 controls the first precharge enable signal BLP1 to switch the voltage level, and the second The logic level of the precharge enable signal BLP2 is different from the first precharge enable signal BLP1, after the test write operation and the test read operation are finished, the precharge enable control circuit 210, the second precharge enable signal The voltage level of BLP2 is switched, and the level is restored to the same level as the logic level of the first precharge enable signal BLP1.

In addition, in the sense amplification voltage control circuit 220, inverter INV27 to inverter INV29, NAND gate NA22 and NAND gate NA23, and switches Q21 to Q25 are connected, and the switches Q21 to Q25 are implemented by the method of a transistor, The voltage levels of the SAP output node NP and the SAN output node NN are switched between the precharge reference voltage HFV, the power supply voltage VDD, and the ground voltage VSS, respectively. The SAP output node NP and the SAN output node NN can output a p-channel control voltage SAP and an n-channel control voltage SAN.

Specifically, the NAND gates NA22 and NA23 receive the raw address signal X12B13B, one input terminal receives the sense enable signals SE1 and SE2, respectively, and the NAND gate NA22, the inverter INV27, and the inverter INV28 are serially serialized. Is connected, the switch Q21 is controlled by the output signal of the inverter INV28, on the other hand, the first stage receives the supply voltage VDD, the second stage is coupled to the SAP output node NP, and the p-channel control voltage SAP is converted to the supply voltage It is used to raise to VDD.

The NAND gate NA23 and the inverter INV29 are connected in series, and the switch Q22 is controlled by the output signal of the inverter INV29, while the first stage is coupled to the SAN output node NN, and the second stage is coupled to the ground voltage VSS. , it is used to reduce the n-channel control voltage SAN to the ground voltage VSS.

Switch Q23, switch Q24, and switch Q25 are all controlled by the second precharge enable signal BLP2, the first stage of switch Q24 and switch Q25 receives the precharge reference voltage HFV, and the precharge reference voltage HFV is Is lower than the power supply voltage VDD, and generally, the voltage value of the precharge reference voltage HFV is substantially half of the power supply voltage VDD. The second stage of switch Q24 is coupled to the first stage of switch Q23, while the second stage of switch Q25 is coupled to the SAP output node NP, and the second stage of switch Q23 is coupled to the SAN output node NN. do. The switches Q23 to Q25 are the enable period of the second precharge enable signal BLP2 (e.g., the switches Q23 to Q25 here take an n-channel transistor as an example, and thus, the second precharge enable signal BLP2 is The enable period is in a high-level state), which is used to restore the voltage levels of the p-channel control voltage SAP and the n-channel control voltage SAN to the precharge reference voltage HFV.

Fig. 5 is a circuit schematic diagram showing a test read/write circuit based on an embodiment of the present invention. Referring to FIG. 5, the test read/write circuit 300 includes a precharge voltage control circuit 310 and a test comparison circuit 320, and the precharge voltage control circuit 310 is a test comparison circuit 320 And the sense amplifying circuit 110. For example, the precharge voltage control circuit 310 includes inverters INV31 to INV33, NAND gates NA31 to NA33, NOR gates NO31 and NO32, switches Q31 to Q36, and transfer gates TG31 to TG34. The test comparison circuit 320 includes a comparator 312, inverters INV34 and INV35, NAND gates NA34 and NA35, NOR gate NO33, and switches Q37 to Q39. In this embodiment, the switches Q31 to Q39 and the transfer gates TG31 to TG34 are implemented by the CMOS transistor method, but are not limited thereto.

In this embodiment, the test comparison circuit 320 further includes a latch circuit 314, but is not necessarily required, and in another embodiment, the test comparison circuit 320 includes a latch circuit 314. You don't need to include it.

Specifically, the NAND gate NA31 of the precharge voltage control circuit 310 receives the low address signal X12B13B and the test enable signal TEST, and the output terminal of the NAND gate NA31 is the inverter INV31, the transfer gate TG31, and the transfer gate TG32. is coupled to the n-channel gate, the output of the inverter INV31 is coupled to the p-channel gate of the transfer gate TG31 and the transfer gate TG32, one end of the transfer gate TG31 and the transfer gate TG32 receives the precharge reference voltage HFV, and the other end , Respectively coupled to HFVT output nodes NHT and HFVN output nodes NHN, and HFVT output nodes NHT and HFVN output nodes NHN provide a first precharge voltage HFVT and a second precharge voltage HFVN to the sense amplifier circuit 110, respectively. do. Here, the transfer gate TG31 and the transfer gate TG32 are simultaneously turned on or disconnected at the same time, and when they are turned on, the HFVT output node NHT and the HFVN output node NHN simultaneously receive the precharge reference voltage HFV.

The inverter INV32 receives the test data signal TDA, and the output terminal is coupled to one of the p-channel gate of the transmission gate TG33, the n-channel gate of the transmission gate TG34, the input terminal of the inverter INV33, and the NOR gate NO31. The output terminal of the inverter INV33 is coupled to one of the n-channel gate of the transfer gate TG33, the p-channel gate of the transfer gate TG34, and the NOR gate NO32. One end of the transfer gate TG33 and the transfer gate TG34 is coupled to the HFVT output node NHT and HFVN output node NHN, respectively, and the other end is commonly coupled to the inverting input terminal of the comparator 312 of the test comparison circuit 320, and the first free It is used to provide one of the charge voltage HFVT and the second precharge voltage HFVN to the comparator 312.

The NAND gate NA32 receives the raw address signal X12B13B and the test data line precharge signal TPIO, and the output stage controls whether the switches Q35 and Q36 are conducting, while the first stage of the switches Q35 and Q36 is the power supply voltage. Upon receiving VDD, the second stage of switch Q35 is coupled to the HFVN output node NHN, and the second stage of switch Q36 is coupled to the HFVT output node NHT. Therefore, in the enable period of the test data line precharge signal TPIO (here, for example, in a high level state), the voltage values of the first precharge voltage HFVT and the second precharge voltage HFVN are raised to the power supply voltage VDD. do.

The NAND gate NA33 receives the raw address signal X12B13B and the test write enable signal TWE, and the output terminal is coupled to the other input terminal of the NOR gate NO31 and the NOR gate NO32. The output terminal of the NOR gate NO31 controls whether the switch Q31 and the switch Q34 conduct, the output terminal of the NOR gate NO32 controls whether the switch Q32 and the switch Q33 conduct, and the first stage of the switch Q31 receives the power supply voltage VDD. , The second stage is coupled to the first stage of the switch Q32 and the HFVT output node NHT, and the second stage of the switch Q32 is coupled to the ground voltage VSS, and thus the voltage level of the first precharge voltage HFVT to ground The threshold voltage of the switch Q31 can be applied from the voltage VSS or the power supply voltage VDD, and the first stage of the switch Q33 receives the power supply voltage VDD, and the second stage is the first stage of the switch Q34 and the HFVN output. Is coupled to the node NHN, and the second stage of the switch Q34 is coupled to the ground voltage VSS, thus applying the voltage level of the second precharge voltage HFVN to the ground voltage VSS or the threshold voltage of the switch Q33 from the power supply voltage VDD. You can do it with voltage.

Accordingly, the precharge voltage control circuit 310 generates a first precharge voltage HFVT and a second precharge voltage HFVN based on the precharge reference voltage HFV, while a test write enable signal TWE and a test data signal By further receiving TDA, the first precharge voltage HFVT and the second precharge voltage HFVN can be set as the voltage obtained by applying the threshold voltage of the transistor from the power supply voltage VDD, the power supply voltage VDD, the ground voltage VSS, or the precharge reference voltage HFV. have.

Specifically, the NAND gate NA34 of the test comparison circuit 320 receives the low address signal X12B13B and the test data enable signal TDE and outputs it to the inverter INV34, and the output terminal of the inverter INV34 is the input terminal of the inverter INV35 and the NAND gate. It is coupled to one input of NA35, and the output of inverter INV35 is coupled to one input of NOR gate NO33. The non-inverting input terminal of the comparator 312 receives the test reference voltage TMREF, and the inverting input terminal receives one of the first precharge voltage HFVT and the second precharge voltage HFVN from the transmission gate TG33 or the transmission gate TG34, and the comparator The output terminal of 312 is coupled to the other input terminal of the NAND gate NA35 and the NOR gate NO33. Here, the test reference voltage TMREF is a constant voltage value of the initial setting, and the voltage value is greater than 1/2 of the power supply voltage VDD, or higher than the precharge reference voltage HFV, and less than the power supply voltage VDD, for example, test The reference voltage TMREF is 3/4 of the power supply voltage VDD.

The switch Q37 is controlled by the output result of the control by the NAND gate NA35, the first stage is coupled to the power supply voltage VDD, the second stage is coupled to the test node NT, and the test node NT gives the test result TFAIL. Print. Switch Q38 is controlled by the output result of the NOR gate NO33, the first stage is coupled to the test node NT, and the second stage is coupled to the ground voltage VSS. Accordingly, as a result of the test, the voltage level of TFAIL becomes the power supply voltage VDD or the ground voltage VSS according to the output result of the comparator 312.

Further, the first stage of the switch Q39 is also coupled to the test node NT, the second stage is coupled to the ground voltage VSS, controlled by the test data line precharge signal TPIO, and the enable period of the test data line precharge signal TPIO. In the test result, the voltage level of TFAIL is reduced to the ground voltage VSS. The latch circuit 314 is also coupled to the test node NT and is used to latch the voltage level of the test result TFAIL.

In simple terms, the test comparison circuit 320 compares one of the first precharge voltage HFVT and the second precharge voltage HFVN and the test reference voltage TMREF to generate a test result TFAIL, so that the memory unit MC is in a poor state. It is determined whether or not, and when one of the first precharge voltage HFVT and the second precharge voltage HFVN is greater than the test reference voltage TMREF, the test result TFAIL is, for example, one of the power supply voltage VDD and the ground voltage VSS. It is substantially the same, indicates that the data detection of the memory unit MC is successful, and when both the first precharge voltage HFVT and the second precharge voltage HFVN are less than the test reference voltage TMREF, the test result TFAIL is, for example , The power supply voltage VDD and the ground voltage VSS are substantially the same as the other, indicating that data detection of the memory unit MC has failed. The following embodiments will be described in more detail with respect to an implementation manner of determining whether a test read/write and a memory unit MC has a bad state.

Next, referring to Figs. 6 to 8, Figs. 6 to 8 are waveform diagrams showing test write operations of logic "0" and logic "1" of the memory device according to the embodiment of the present invention, respectively. The operations of FIGS. 6 to 8 can be applied to the embodiments of FIGS. 1 to 5. In the test write operation, taking any one memory unit MC as an example, FIG. 6 shows a word line signal WLn at a corresponding word line WL, a test write enable signal TWE, a sense enable signal SE1, SE2, and a first precharge. The operation waveform diagrams of the enable signal BLP1 and the second precharge enable signal BLP2 are shown. 7 shows a test write operation when the write data is logic "0", a first precharge voltage HFVT, a second precharge voltage HFVN, a p-channel control voltage SAP, an n-channel control voltage SAN, a bit line BLT, and a complementary bit. The operation waveform diagram of the voltage level of the line BLN is shown. As to be specifically described, the thin straight lines shown in Figs. 7 and 8 and described by different symbols indicate the waveform operation in Fig. 6, and the symbols are not indicated so as not to obscure the drawing. From 6, we can grasp the meaning of these thin lines.

First of all, referring to FIGS. 6 and 7 in parallel to FIGS. 1 to 5, the first precharge voltage HFVT and the second precharge voltage HFVN are, before performing the test, the transfer gate TG31 and the transfer gate TG32, It conducts and is maintained at the level of the voltage value of the precharge reference voltage HFV. In the test write operation, in particular, in the test write detection period tW, one of the first precharge voltage HFVT and the second precharge voltage HFVN is lower than the power supply voltage VDD, but higher than the precharge reference voltage HFV, The other voltage value is lower than the precharge reference voltage HFV, and is substantially equal to the ground voltage VSS, for example.

First, if it is assumed that data indicating logic "0" is to be written to the memory unit MC as an example, the test data signal TDA enters the low level state, while at this time, the word line signal WLn and the test write enable signal TWE The voltage of is in a high-level state, and therefore, the switches Q31 and Q34 are cut off, and the switches Q32 and Q33 are conducted, where the switches Q31 to Q34 are all n-channel transistors as an example, but are not limited thereto, and the precharge voltage The voltage of the first precharge voltage HFVT provided by the control circuit 310 is lowered to the ground voltage VSS, and the second precharge voltage HFVN is the level of the voltage obtained by applying the threshold voltage VTN of the n-channel transistor from the power supply voltage VDD. Impressed. For explanation, the voltage value of the power supply voltage VDD is greater than the sum of the voltages of the precharge reference voltage HFV and the threshold voltage VTN.

Subsequently, the precharge enable control circuit 210 switches the first precharge enable signal BLP1 from the original low level state to the high level state, but the second precharge enable signal BLP2 maintains the low level state. And, by conducting the first switch T1 and the second switch T2, the third switch T3 is cut, and the bit line BLT and the complementary bit line BLN each receive a first precharge voltage HFVT and a second precharge voltage HFVN. I can.

As to be specifically described, in the present embodiment, when a test write operation is performed on the memory unit MC, on the other hand, the first precharge enable signal BLP1 is before switching to the enable state, i.e., the first switch T1 and Before the second switch T2 conducts, the voltage levels of the first precharge voltage HFVT and the second precharge voltage HFVN are already different.

Subsequently, the sense amplification voltage control circuit 220 switches the p-channel control voltage SAP and the n-channel control voltage SAN from the precharge reference voltage HFV to the power supply voltage VDD and the ground voltage VSS, respectively. The voltage level of the p-channel control voltage SAP and the n-channel control voltage SAN is originally kept lower than the power supply voltage VDD, here equal to the precharge reference voltage HFV, and in the enable period of the sense enable signals SE1 and SE2. , The switch Q21 and the switch Q22 are conducted, the p-channel control voltage SAP and the n-channel control voltage SAN are switched to power supply voltage VDD and ground voltage VSS, respectively, and increase the voltage difference between the bit line BLT and the complementary bit line BLN. Therefore, in the test write detection period tW, the voltage level of the bit line BLT is substantially the same as the ground voltage VSS, the voltage level of the complementary bit line BLN is the power supply voltage VDD, and the logic "0" to the memory unit MC. Save the data indicating "".

Subsequently, referring to FIGS. 6 and 8 in parallel to FIGS. 1 to 5, FIG. 8 shows a test write operation when writing data of logic "1", a first precharge voltage HFVT, and a second precharge. The operation waveform diagram of voltage HFVN, p-channel control voltage SAP, and n-channel control voltage SAN is shown. In the test write operation, assuming that data indicating logic "1" is to be written to the memory unit MC as an example, the test data signal TDA enters a high level state, and in the test write detection period tW, the precharge voltage control circuit ( The voltage value of the first precharge voltage HFVT output by 310) is increased to the level of the voltage obtained by applying the threshold voltage VTN of the n-channel transistor from the power supply voltage VDD, and the voltage level of the second precharge voltage HFVN is the ground voltage VSS The detailed implementation method is reduced to, and a person skilled in the art can obtain sufficient teaching and presentation from the above-described examples and general techniques, and is not described herein repeatedly.

9 to 11 are waveform diagrams each showing a test read operation of the memory device according to the embodiment of the present invention. The operations of FIGS. 9 to 11 can be applied to the embodiments of FIGS. 1 to 8. Referring to FIGS. 1 to 5 in parallel and referring to FIGS. 9 to 11, in the test read operation, taking any one memory unit MC as an example, FIG. 9 shows a word line signal WLn, sense enable signals SE1 and SE2, and The operation waveform diagram of the test data line precharge signal TPIO, the test data enable signal TDE, the first precharge enable signal BLP1, and the second precharge enable signal BLP2 is shown. 10 and 11 show a first precharge voltage HFVT, a second precharge voltage HFVN, a p-channel control voltage SAP, an n-channel control voltage SAN, and bits when it is determined that the read result of the test read operation is success or failure, respectively. The operation waveform diagram of the voltage level of the line BLT and the complementary bit line BLN is shown. As a special description, the thin straight lines shown in FIGS. 10 and 11 and described with different symbols represent the waveform operation in FIG. 9, and the symbols are not indicated so that the drawings are not messy. From 9, we can grasp the meaning of these thin lines.

First, referring to Figs. 9 and 10, the first precharge voltage HFVT and the second precharge voltage HFVN are, before performing the test, the transfer gate TG31 and the transfer gate TG32 are conductive, and the precharge reference voltage HFV is It is maintained by the magnitude of the voltage value.

When a test read operation is performed on the memory unit MC, as an example, if the memory unit MC reads data indicating logic "0", it is in a high level state at the word line signal WLn, while the test read detection period tR is Prior to that, first, the data line precharge operation is performed, that is, in the enable period of the test data line precharge signal TPIO, by conducting the switch Q35, the switch Q36 and the switch Q39, the first precharge voltage HFVT and The second precharge voltage HFVN is first raised to a voltage substantially equal to the power supply voltage VDD, and the test node NT receives substantially the ground voltage VSS. Here, the switch Q35 and the switch Q36 are p-channel transistors, and the switch Q39 is an n-channel transistor.

After the data line precharge operation is completed, the test data line precharge signal TPIO is disabled (e.g., in a low level state), and the sense enable signals SE1 and SE2 are enabled. The SAP and n-channel control voltage SAN are switched from the precharge reference voltage HFV to the power supply voltage VDD and the ground voltage VSS, respectively.

Subsequently, the first precharge enable signal BLP1 is switched from the original low level state to the high level state, and the second precharge enable signal BLP2 is held in the low level state. The first precharge enable signal BLP1 switched to the high-level state conducts the first switch T1 and the second switch T2, and if all data of the memory unit MC in the same word line WL are detected successfully, a test In the read detection period tR, the voltage levels of the first precharge voltage HFVT and the second precharge voltage HFVN are different, and the voltage level of one of the first precharge voltage HFVT and the second precharge voltage HFVN is the power supply voltage VDD. Is maintained at, and the other voltage level is lowered to a voltage substantially equal to the ground voltage VSS, and in the embodiment of FIG. 9, the second precharge voltage HFVN is maintained at the power supply voltage VDD, while the first precharge As an example, the voltage HFVT is lowered to the ground voltage VSS.

As specifically described, in the test write operation and the test read operation, the first precharge enable signal BLP1 has different timings for switching from the low level state to the high level state, and specifically, the first precharge enable signal In the BLP1, when performing the test write operation, the timing of switching the voltage level is earlier than the timing when performing the test read operation. In the test write operation, the first precharge enable signal BLP1 switches to the high level state earlier than the sense enable signals SE1 and SE2, but in the test read operation, the first precharge enable signal BLP1 is sense-enable. It switches to the high level state later than the enable signals SE1 and SE2.

Subsequently, the comparator 312 from receiving the test reference voltage TMREF and one of the first precharge voltage HFVT and the second precharge voltage HFVN, for example, the voltage level is high, in this embodiment, the comparator 312 receives the test reference voltage TMREF and the second precharge voltage HFVN, the voltage value of the test reference voltage TMREF becomes 3/4 of the power supply voltage VDD, and the second precharge voltage HFVN is the power supply at this time. Is substantially equal to the voltage VDD. In the test read detection period tR, since the second precharge voltage HFVN is greater than the test reference voltage TMREF, the test reference voltage TMREF is in a low level state, and is substantially equal to the ground voltage VSS, for example, All of the data of the memory unit MC in the same word line WL is successfully detected.

9 and 11, when a data detection failure occurs in the memory unit MC in the same word line WL, the first precharge enable signal BLP1 is switched to the high level state, and the first switch T1 and the second 2 Since the voltage value is lowered to the ground voltage VSS after the switch T2 is turned on, the first precharge voltage HFVT and the second precharge voltage HFVN, which is originally in a high level state, is smaller than the original voltage level.

In this embodiment, the second precharge voltage HFVN is originally in a high level state, while the voltage value is substantially the same as the power supply voltage VDD, and the magnitude of the voltage value of the first precharge voltage HFVT is the ground voltage VSS Is substantially the same as In the test read detection period tR, after the first switch T1 and the second switch T2 conduct, the first precharge voltage HFVT is the same as the ground voltage VSS, but the voltage of the second precharge voltage HFVN is the power supply voltage VDD. Is reduced to a size of about 1/2, and specifically, the voltage of the second precharge voltage HFVN is reduced to the size of the voltage applied from the power supply voltage VDD to the threshold voltage VTN of the n-channel transistor, and in the embodiment , The power supply voltage VDD is 1.5 V, and the threshold voltage VTN of the n-channel transistor is 0.7 V, and thus, the reduced voltage of the second precharge voltage HFVN is about 1/2 of the power supply voltage VDD.

Subsequently, the comparator 312 receives and compares the test reference voltage TMREF and the second precharge voltage HFVN, and the voltage value of the test reference voltage TMREF becomes 3/4 of the initial power supply voltage VDD, and 2 The voltage value at this time of the precharge voltage HFVN is equal to about 1/2 of the power supply voltage VDD and is less than the test reference voltage TMREF, so that the test result TFAIL is changed to a high voltage level, for example , Which is substantially the same as the power supply voltage VDD, and indicates a state in which detection of data of the memory unit MC in the same word line WL has failed.

9 to 11, when performing a test read operation on the memory unit MC, in the test read detection period tR, one of the first precharge voltage HFVT and the second precharge voltage HFVN The value is not greater than the power supply voltage VDD, but is higher than the precharge reference voltage HFV, and the other voltage value is lower than the precharge reference voltage HFV, and is, for example, the same as the ground voltage VSS.

In another embodiment, the first precharge voltage HFVT is in a high level state, while the comparator 312 may receive and compare the test reference voltage TMREF and the first precharge voltage HFVT, and a detailed implementation method Is, since a person skilled in the art can obtain sufficient teaching from the above description and general technique, it is not described repeatedly here.

Referring to Fig. 12, Fig. 12 is an operational waveform diagram showing test writes of logic &quot;0&quot; to all memory units by a memory device according to another embodiment of the present invention. This embodiment can be applied to the memory device 100 of the embodiments of FIGS. 1 to 11. In the embodiment of FIG. 12, after the memory device 100 is powered on (Power 　 up) or after a reset state (RESET), the memory device 100 is within the extended write cycle T, for example, 200 μs to 300 μs. Within a range of less than a second, in the embodiment of FIG. 12, if, as an example, the extended write cycle T is about 300 μs, all word lines WL in the memory device 100 and all the sense amplifying circuits 110 related thereto A write operation is performed, and reference numerals abbreviated in Fig. 12 indicate this. That is, the memory device 100 of the present invention writes data of logic &quot;0&quot; to the memory units MC in all word lines WL within a short period of time. Regarding the implementation method of the operation waveform of Fig. 12, a person skilled in the art can obtain sufficient teaching and presentation from the embodiment of Figs. 6 to 8, and it is not described herein repeatedly.

In the above, the present invention provides a memory device including a precharge voltage control circuit and a sense amplifier circuit. The precharge voltage control circuit generates a first precharge voltage and a second precharge voltage based on the precharge reference voltage. The sense amplifier is coupled between the bit line and the complementary bit line, and is used to detect data of the memory unit coupled to the bit line, while coupled to the precharge voltage control circuit, during precharge operation, the first precharge. The voltage levels of the charge voltage and the second precharge voltage are the same, and in the test write detection period and the test read detection period after the precharge operation, the precharge voltage control circuit provides the first precharge to the bit line and the complementary bit line. The voltage levels of the voltage and the second precharge voltage are different. In this way, it is possible to implement the parallel test mode by selecting a plurality of sense amplifiers in the word line within one cycle.

Although the text is shown as in the above examples, it is not intended to limit the present invention, and since it is possible to change or modify a person skilled in the art without departing from the scope of the technical idea of the present invention, the scope of protection of the present invention is patented. Based on what is defined in the claims.

The detector provided by the present invention completes the detection operation of the data bus inversion function with low power consumption. In the memory device, the efficiency of the data bus inversion function is effectively improved. On the other hand, the data access efficiency of the electronic device described in the memory device is also effectively improved.

100: memory circuit
110： Sense amplifier circuit
120： Control test circuit
130： Memory array
140: X decoder block
150: Y decoder block
160： Sense amplifier block
200: sense control circuit
210: Precharge enable control circuit
220： sense amplification voltage control circuit
300: Test read and write circuit
310: Precharge voltage control circuit
312： Comparator
314: Latch circuit
320： Test comparison circuit
BLT: Bit line
BLN: Complementary bit line
BLPE1: Precharge enable signal
BLP1: 1st precharge enable signal
BLP2: 2nd precharge enable signal
HFV ： Precharge reference voltage
HFVT: 1st precharge voltage
HFVN ： Second precharge voltage
INV ： Inverter
MC: Memory unit
N1: first intermediate node
N2: Second intermediate node
NP ： SAP output node
NN: SAN output node
NHT: HFVT output node
NHN: HFVN output node
NT: Test node
NA21~NA23, NA31~NA35: NAND gate
NO31~NO33: NOR gate
Q1, Q2, Q3, Q4: Transistor
Q21 to Q25, Q1 to Q39: Switch
SA: sense circuit
SE1, SE2 ： Sense enable signal
SAP ： p-channel control voltage
SAN: n-channel control voltage
T: Extended write cycle
T1: 1st switch
T2: 2nd switch
T3: 3rd switch
TFAIL ： Test result
TG31~TG34: Transfer gate
TWE: Test write enable signal
TDA: Test data signal
TDE: Test data enable signal
TEST ： Test enable signal
TPIO: Test data line precharge signal
tR: Test read detection period
tW: Test write detection period
TMREF: Test reference voltage
VDD: Power supply voltage
VSS: ground voltage
VTN: Threshold voltage of n-channel transistor
WL: Word line
WLn, WLm: Word line signal
X12B13B: Low address signal

Claims (16)

A precharge voltage control circuit that generates a first precharge voltage and a second precharge voltage based on the precharge reference voltage,
It is coupled between a bit line and a complementary bit line, is used to detect data of a memory unit coupled to the bit line, is coupled to the precharge voltage control circuit, and is coupled to the bit line and the complementary bit line, respectively, the A sense amplifier circuit for receiving a first precharge voltage and the second precharge voltage, and
A test comparison circuit coupled to the precharge voltage control circuit and comparing one of the first precharge voltage and the second precharge voltage and a test reference voltage to generate a test result
Including,
During a precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are the same, and in the test write detection period and the test read detection period after the precharge operation, the precharge voltage control circuit The voltage levels of the first precharge voltage and the second precharge voltage provided to the bit line and the complementary bit line are different.
Memory device. The method of claim 1,
The sense amplification circuit,
A first stage receives the first precharge voltage, and a second stage is a first switch coupled to the bit line and controlled by a first precharge enable signal,
A first stage receives the second precharge voltage, and a second stage is coupled to the complementary bit line, and a second switch controlled by the first precharge enable signal,
A third switch coupled between the bit line and the complementary bit line and controlled by a second precharge enable signal,
A sense circuit coupled between the bit line and the complementary bit line and used to increase a voltage difference between the bit line and the complementary bit line
A memory device comprising a. The method of claim 2,
A precharge enable control circuit coupled to the sense amplifying circuit and generating the first precharge enable signal and the second precharge enable signal based on a precharge enable signal
Including more,
When performing a test write operation and a test read operation on the memory unit, the voltage level of the first precharge enable signal is switched, and the logic level of the second precharge enable signal is the first precharge enable. Unlike the enable signal, after the test write operation and the test read operation are finished, the voltage level of the second precharge enable signal is switched to recover to the same level as the logic level of the first precharge enable signal.
Memory device. The method of claim 1,
When one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, the test result indicates that data detection of the memory unit is successful, and the first precharge voltage and the first When both precharge voltages are less than the test reference voltage, the test result indicates that the data detection of the memory unit has failed.
Memory device. The method of claim 4,
The voltage level of the test reference voltage is higher than the precharge reference voltage and smaller than the power supply voltage.
Memory device. The method of claim 5,
When one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, the voltage value of the test result is substantially the same as one of the power supply voltage and the ground voltage, and the first precharge voltage When both the voltage and the second precharge voltage are less than the test reference voltage, the voltage value of the test result is substantially the same as the other of the power supply voltage and the ground voltage.
Memory device. The method of claim 1,
In the test write detection period, one of the first precharge voltage and the second precharge voltage is lower than the power supply voltage, but higher than the precharge reference voltage, and the other voltage value is referred to the precharge. Lower than voltage
Memory device. The method of claim 3,
When performing the test read operation on the memory unit, before performing the test read detection, the first precharge voltage and the second precharge voltage are first raised to a voltage substantially equal to the power supply voltage.
Memory device. In the read/write method for a memory device used to perform a test write operation and a test read operation for a memory unit,
Generating a first precharge voltage and a second precharge voltage based on the precharge reference voltage,
Receiving the first precharge voltage and the second precharge voltage, respectively, to a bit line and a complementary bit line,
Comparing one of the first precharge voltage and the second precharge voltage and a test reference voltage to generate a test result
Including,
During a precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are the same, and in the test write detection period and the test read detection period after the precharge operation, the precharge voltage control circuit The voltage levels of the first precharge voltage and the second precharge voltage provided to the line and the complementary bit line are different
Read and write method. The method of claim 9,
Controlling a first switch and a second switch by a first precharge enable signal, and determining whether the bit line and the complementary bit line each receive the first precharge voltage and the second precharge voltage With,
Controlling a third switch according to a second precharge enable signal to determine whether to electrically connect the bit line and the complementary bit line;
Enlarging the voltage difference between the bit line and the complementary bit line by a sense circuit
Read and write method comprising more. The method of claim 10,
Generating the first precharge enable signal and the second precharge enable signal based on a precharge enable signal
Including more,
When performing the test write operation and the test read operation on the memory unit, the voltage level of the first precharge enable signal is switched, and the logic level of the second precharge enable signal is the first precharge enable signal. Unlike the charge enable signal, after the test write operation and the test read operation are finished, the voltage level of the second precharge enable signal is switched to recover to the same level as the logic level of the first precharge enable signal. doing
Read and write method. The method of claim 9,
When one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, the test result indicates that data detection of the memory unit is successful, and the first precharge voltage and the first When both precharge voltages are less than the test reference voltage, the test result indicates that the data detection of the memory unit has failed.
Read and write method. The method of claim 12,
The voltage level of the test reference voltage is higher than the precharge reference voltage and smaller than the power supply voltage.
Read and write method. The method of claim 13,
When one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, the voltage value of the test result is substantially the same as one of the power supply voltage and the ground voltage, and the first precharge voltage When both the voltage and the second precharge voltage are less than the test reference voltage, the voltage value of the test result is substantially the same as the other of the power supply voltage and the ground voltage.
Read and write method. The method of claim 9,
In the test write detection period, one of the first precharge voltage and the second precharge voltage is lower than the power supply voltage, but higher than the precharge reference voltage, and the other voltage value is referred to the precharge. Lower than voltage
Read and write method. The method of claim 9,
When performing the test read operation on the memory unit, before performing the test read detection, the first precharge voltage and the second precharge voltage are first raised to a voltage substantially equal to the power supply voltage.
Read and write method.

Images