KR20190143602A - Memory device and method for test reading and writing thereof - Google Patents

Abstract

The present invention provides a memory device and a test reading and writing method thereof. A precharge voltage control circuit generates a first precharge voltage and a second precharge voltage based on a precharge reference voltage. A sense amplifying circuit is coupled between a bit line and a complementary bit line and used to detect data of a memory unit coupled to the bit line. Meanwhile, the sense amplifying circuit is coupled to a precharge voltage control circuit to receive the first precharge voltage and the second precharge voltage to the bit line and the complementary bit line. During a precharge operation, voltage levels of the first precharge voltage and the second precharge voltage are the same. In a test writing detection period and a test reading detection period after the precharge operation, voltage levels of the first precharge voltage and the second precharge voltage provided to the bit line and the complementary bit line by the precharge voltage control circuit are different.

Description

MEMORY DEVICE AND METHOD FOR TEST READING AND WRITING THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory technology, and more particularly, to a memory device capable of reading and writing all sense circuits on a selected word line at a time in a parallel test mode and a test read-write method thereof. will be.

In a typical semiconductor memory device, for example, a sense amplifier is formed in a DRAM, connected to a bit line of a memory unit array, and accessing data from a selected memory unit to amplify the data.

In the prior art, when testing a memory device, for example, in a parallel test mode, a plurality of amplifiers that normally read and write are selected at one time, but more memory than the number of data lines (Data line) is selected. Since the unit cannot be selected and tested at a time, how to select a plurality of sense amplifiers in a word line and execute a parallel test mode in one cycle is a problem that needs to be solved at present. Has become one of.

An object of the present invention is to provide a memory device and a test read / write method thereof capable of selecting a plurality of sense amplifiers of a word line in a single cycle and performing a parallel test mode.

The present invention relates to a precharge voltage control circuit that generates a first precharge voltage and a second precharge voltage based on a precharge reference voltage, and a memory coupled between the bit line and the complementary bit line, and coupled to the bit line. A sense amplification circuit used to detect data of the unit, coupled to the precharge voltage control circuit, and receiving a first precharge voltage and a second precharge voltage on the bit line and the complementary bit line, respectively, and precharge During operation, the voltage levels of the first precharge voltage and the second precharge voltage are the same, and in the test write detection period and the test read detection period after the precharge operation, the precharge voltage control circuit is provided to the bit line and the complementary bit line. The voltage levels of the first precharge voltage and the second precharge voltage provide different memory devices.

A read write method for a memory device, which is used to perform a test write operation and a test read operation on a memory unit, the method comprising: generating a first precharge voltage and a second precharge voltage based on a precharge reference voltage;

Receiving in the bit line and the complementary bit line a first precharge voltage and a second precharge voltage, respectively,

During the precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are the same, and in the test write detection period and the test read detection period after the precharge operation, the precharge voltage control circuit includes a bit line and a complementary bit line. The voltage levels of the first precharge voltage and the second precharge voltage provided to provide different read and write methods.

Based on the above, a memory device and a test read / write method thereof capable of realizing selecting a plurality of sense amplifiers on a word line and performing a parallel test mode in one cycle can be provided.

DETAILED DESCRIPTION In order to further clarify the above-described features and advantages of the present invention, the following detailed description will be given with reference to the accompanying drawings.

1 is a schematic diagram showing a memory device based on an embodiment of the present invention.
2 is a schematic diagram showing an array structure of a memory device based on an embodiment of the present invention.
3 is a block schematic diagram showing a control test circuit based on the embodiment of the present invention.
4 is a circuit schematic diagram showing a sense control circuit based on the embodiment of the present invention.
Fig. 5 is a circuit schematic diagram showing a test read / write circuit based on the embodiment of the present invention.
6 to 8 are waveform diagrams showing test write operations of logic "0" and logic "1", respectively, of the memory device based on the embodiment of the present invention.
9 to 11 are waveform diagrams each showing a test read operation of the memory device based on the embodiment of the present invention.
Fig. 12 is an operational waveform diagram showing test writing of logic " 0 " to all memory units by a memory device based on another embodiment of the present invention.

Referring to FIG. 1, FIG. 1 is a schematic diagram showing a memory device based on an embodiment of the present invention. The memory circuit 100 includes a word line WL, a bit line BLT, a complementary bit line BLN, a memory unit MC, a sense amplifier circuit 110, and a control test circuit 120. The control test circuit 120 is coupled to the sense amplifier circuit 110 to provide a plurality of control signals.

The memory unit MC includes, for example, a memory capacitor used to preserve the data level, and a metal oxide semiconductor transistor (Metal? Oxide? Semiconductor? Transistor, MOSFET) (not shown in the figure) serving as a switch. The first end of the transistor is coupled to the capacitor, the second end is coupled to the bit line BLT, and the gate is coupled to the word line WL. Here, the plurality of memory units MC form an array arrangement in the directions of the plurality of word lines WL, the plurality of bit lines BLT, and the plurality of complementary bit lines BLN to form the memory array 130. In addition, the word line signals WLn and WLm shown in FIG. 1 represent signals at other word lines WL.

The sense amplifier circuit 110 is used to detect data of the memory unit MC by being coupled to a pair of bit lines, namely, the bit line BLT and the complementary bit line BLN, and thus a test write operation on the memory unit MC. Alternatively, a test read operation can be performed.

The sense amplifier circuit 110 receives the first precharge voltage HFVT, the second precharge voltage HFVN, the first precharge enable signal BLP1, and the second precharge enable signal BLP2 from the control test circuit 120. The sense amplification circuit 110 is based on the first precharge enable signal BLP1 and the second precharge enable signal BLP2, respectively, for the first precharge voltage HFVT and the second precharge to the bit line BLT and the complementary bit line BLN. It is determined whether the charge voltage HFVN is to be received, and during the precharge operation, the voltage levels of the first precharge voltage HFVT and the second precharge voltage HFVN are the same voltage level from the same to the bit line BLT and the complementary bit line BLN. However, in the test write detection period and the test read detection period after the precharge operation, the voltage levels of the first precharge voltage HFVT and the second precharge voltage HFVN provided by the control test circuit 120 are different, The first precharge enable signal BLP1 has a different timing at which the voltage level is switched in the test write detection period and the test read detection period. In the detection process, the voltage difference between the bit line BLT and the complementary bit line BLN is mainly influenced by the data emitted by the memory unit MC, and thus between the bit line BLT and the complementary bit line BLN in this embodiment. The voltage difference is related to the voltage difference between the first precharge voltage HFVT and the second precharge voltage HFVN. In the following Examples, it demonstrates further in detail.

The sense amplifier circuit 110 includes a first switch T1, a second switch T2, a third switch T3, and a sense circuit SA. The first switch T1, the second switch T2, and the third switch T3 Here, although an n-channel transistor is taken as an example, it does not restrict to this. The first stage (drain) of the first switch T1 receives the first precharge voltage HFVT, the second stage (source) is coupled to the bit line BLT, and the gate stage is the first precharge enable signal BLP1. To determine whether to conduct. The first stage (drain) of the second switch T2 receives the second precharge voltage HFVN, the second stage (source) is coupled to the complementary bit line BLN, and the gate stage is similarly the first precharge in Receive the enable signal BLP1 to determine if it is conductive. The third switch T3 is coupled between the bit line BLT and the complementary bit line BLN, and the gate end receives the second precharge enable signal BLP2.

The sense circuit SA is coupled between the bit line BLT and the complementary bit line BLN, and is based on the p-channel control voltage SAP and the n-channel control voltage SAN received from the sense amplification circuit 120, and thus the bit line BLT and the complementary bit line. It is used to increase the voltage difference between BLNs. In this embodiment, the sense circuit SA is implemented to be connected to the flip-flop of the positive feedback path by a CMOS inverter including two MOS transistors Q1 and Q2 and a CMOS inverter including two MOS transistors Q3 and Q4.

The first stages (here, the source) of the transistors Q1 and Q3 of the sense circuit SA are coupled to a first intermediate node N1, which receives the p-channel control voltage SAP, and the transistors Q2 and Q4. The second stage of (here is a source) is coupled to a second intermediate node N2, which receives the n-channel control voltage SAN. The other ends of the transistors Q1 and Q2 of the sense circuit SA (here are drains) and the gates of the transistors Q3 and Q4 are coupled to the bit lines BLT and the other ends of the transistors Q3 and Q4 (here are drains) and the transistors Q1 and Q2. The gate is coupled to the complementary bit line BLN, so that the voltage levels of the bit line BLT and the complementary bit line BLN are pulled up under the influence of the p-channel control voltage SAP and the n-channel control voltage SAN, or It may be pulled down to represent a logic "1" or a logic "0".

2 is a schematic diagram showing an array structure of a memory device based on the embodiment of the present invention. 2 may be applied to the memory device 100 of FIG. 1. Referring to FIG. 2, the memory array 130 includes a memory unit MC connected to a plurality of word lines WL and a plurality of bit lines BLT, and includes an X decoder block (XDEC) 140 and a Y decoder block (YDEC). 150 is coupled to the memory array 130 and used to select which memory unit MC to perform data access to. The memory array 130 is coupled to the sense amplifier block 160, the sense amplifier block 160 is coupled to the control test circuit 120, and the sense amplifier block 160 includes a plurality of sense amplifier circuits ( The arrangement relationship between the control test circuit 120 and the sense amplifier circuit 110 of the sense amplifier block 160 may be referred to the disclosure of FIG. 1.

3 is a block schematic diagram showing a control test circuit based on the embodiment of the present invention. Referring to FIG. 3, the control test circuit 120 includes a sense control circuit 200 and a test read / write circuit 300 disposed near the sense control circuit 200. The sense control circuit 200 and the test read / write circuit 300 are both coupled to the sense amplifier circuit 110, and respectively, the first precharge enable signal BLP1, the second precharge enable signal BLP2, and the p-channel control voltage. SAP, n-channel control voltage SAN, first precharge voltage HFVT and second precharge voltage HFVN. In the test mode, the test read write circuit 300 generates a test result TFAIL based on a result of comparing the test reference voltage TMREF with one of the first precharge voltage HFVT and the second precharge voltage HFVN, and the memory unit Determine if the MC has a bad state. The following embodiment describes in detail the mechanism by which the memory unit MC determines that the state is not good.

4 is a circuit schematic diagram showing a sense control circuit based on the embodiment of the present invention. Referring to FIG. 4, in this embodiment, the sense control circuit 200 includes a precharge enable control circuit 210 and a sense amplification voltage control circuit 220. The precharge enable control circuit 210 is formed by connecting the inverters INV21 to INV26 and the NAND gate NA21, for example.

Specifically, the input terminal of the inverter INV21 receives the precharge enable signal BLPE1, and the precharge enable signal BLPE1 is used to determine when to precharge the bit line BLT and the complementary bit line BLN. Is coupled to one input terminal of the NAND gate NA21, the other input terminal of the NAND gate NA21 receives a low address signal X12B13B, and the low address signal X12B13B is used to select which word line WL acts. The output terminal of the NAND gate NA21 is coupled to the input terminal of the inverter INV22, the inverter INV22 and the inverter INV23 are connected in series, and the inverter INV23 outputs the first precharge enable signal BLP1. Inverter INV24, inverter INV25, and inverter INV26 are serially connected in order, inverter INV24 receives raw address signal X12B13B, and inverter INV26 outputs the 2nd precharge enable signal BLP2.

Accordingly, the precharge enable control circuit 210 is coupled to the sense amplifier circuit 110 and based on the precharge enable signal BLPE1 and the low address signal X12B13B, the first precharge enable signal BLP1 and the second precharge. The charge enable signal BLP2 is generated and provided to the sense amplifying circuit 110. When performing a test write operation and a test read operation on the memory unit MC, the precharge enable control circuit 210 can control the first precharge enable signal BLP1 to switch the voltage level, and thereby the second. Unlike the first precharge enable signal BLP1, the logic level of the precharge enable signal BLP2 is different from the first precharge enable signal BLP1. After the test write operation and the test read operation are completed, the precharge enable control circuit 210 performs the second precharge enable signal. The voltage level of the BLP2 is switched to restore the same level as the logic level of the first precharge enable signal BLP1.

In addition, the sense amplification voltage control circuit 220 is connected to an inverter INV27 to an inverter INV29, a NAND gate NA22 and a NAND gate NA23, and switches Q21 to Q25, and the switches Q21 to Q25 are implemented by a transistor method. The voltage levels of the SAP output node NP and the SAN output node NN are switched between the precharge reference voltage HFV, the power supply voltage VDD, and the ground voltage VSS, respectively. The SAP output node NP and the SAN output node NN can output the p-channel control voltage SAP and the n-channel control voltage SAN.

Specifically, the NAND gates NA22 and NA23 receive the raw address signal X12B13B, and one input terminal receives the sense enable signals SE1 and SE2, respectively, and the NAND gate NA22, the inverter INV27, and the inverter INV28 are in series. Connected, the switch Q21 is controlled by the output signal of the inverter INV28, while the first stage receives the power supply voltage VDD and the second stage is coupled to the SAP output node NP to supply the p-channel control voltage SAP to the power supply voltage. Used to raise to VDD.

The NAND gate NA23 and the inverter INV29 are connected in series, the switch Q22 is controlled by the output signal of the inverter INV29, while the first stage is coupled to the SAN output node NN, and the second stage is coupled to the ground voltage VSS. In other words, it is used to lower the n-channel control voltage SAN to the ground voltage VSS.

The switch Q23, the switch Q24, and the switch Q25 are all controlled by the second precharge enable signal BLP2, and the first stage of the switch Q24 and the switch Q25 receives the precharge reference voltage HFV, and the precharge reference voltage HFV is Is lower than the power supply voltage VDD, and in general, the voltage value of the precharge reference voltage HFV is substantially half of the power supply voltage VDD. The second stage of the switch Q24 is coupled to the first stage of the switch Q23, while the second stage of the switch Q25 is coupled to the SAP output node NP, and the second stage of the switch Q23 is coupled to the SAN output node NN. do. The switches Q23 to Q25 are the enable periods of the second precharge enable signal BLP2 (for example, the switches Q23 to Q25 are exemplified as n-channel transistors, and thus, the second precharge enable signal BLP2 is used). The enable period is in a high level state), and is used to restore the voltage levels of the p-channel control voltage SAP and the n-channel control voltage SAN to the precharge reference voltage HFV.

5 is a circuit schematic diagram showing a test read / write circuit based on the embodiment of the present invention. Referring to FIG. 5, the test read write circuit 300 includes a precharge voltage control circuit 310 and a test comparison circuit 320, and the precharge voltage control circuit 310 includes a test comparison circuit 320. And a sense amplification circuit 110. For example, the precharge voltage control circuit 310 includes inverters INV31 to INV33, NAND gates NA31 to NA33, NOR gates NO31 and NO32, switches Q31 to Q36, and transfer gates TG31 to TG34. The test comparison circuit 320 includes a comparator 312, inverters INV34 and INV35, NAND gates NA34 and NA35, a NOR gate NO33, and switches Q37 to Q39. In the present embodiment, the switches Q31 to Q39 and the transfer gates TG31 to TG34 are implemented by the method of the CMOS transistor, but are not limited thereto.

In this embodiment, the test comparison circuit 320 further includes a latch circuit 314, but is not necessary, and in another embodiment, the test comparison circuit 320 includes the latch circuit 314. It is not necessary to include it.

Specifically, the NAND gate NA31 of the precharge voltage control circuit 310 receives the low address signal X12B13B and the test enable signal TEST, and the output terminals of the NAND gate NA31 are the inverter INV31, the transfer gate TG31, and the transfer gate TG32. coupled to the n-channel gate, the output terminal of the inverter INV31 is coupled to the p-channel gate of the transfer gate TG31 and the transfer gate TG32, one end of the transfer gate TG31 and the transfer gate TG32 receives the precharge reference voltage HFV, and the other end is , Respectively, coupled to the HFVT output node NHT and HFVN output node NHN, wherein the HFVT output node NHT and HFVN output node NHN provide the first precharge voltage HFVT and the second precharge voltage HFVN to the sense amplification circuit 110, respectively. do. Here, the transfer gate TG31 and the transfer gate TG32 are simultaneously turned on or disconnected simultaneously, and at the time of conduction, the HFVT output node NHT and the HFVN output node NHN simultaneously receive the precharge reference voltage HFV.

The inverter INV32 receives the test data signal TDA, and the output terminal is coupled to one of the p-channel gate of the transfer gate TG33, the n-channel gate of the transfer gate TG34, the input terminal of the inverter INV33, and the NOR gate NO31. The output terminal of the inverter INV33 is coupled to one input terminal of the n-channel gate of the transfer gate TG33, the p-channel gate of the transfer gate TG34, and the NOR gate NO32. One end of the transfer gate TG33 and the transfer gate TG34 is coupled to the HFVT output node NHT and the HFVN output node NHN, respectively, and the other end is commonly coupled to the inverting input terminal of the comparator 312 of the test comparison circuit 320, and the first pre One of the charge voltage HFVT and the second precharge voltage HFVN is used to provide a comparator 312.

The NAND gate NA32 receives the low address signal X12B13B and the test data line precharge signal TPIO, and the output terminal controls whether the switch Q35 and the switch Q36 are conducting, while the first stage of the switch Q35 and the switch Q36 is a power supply voltage. Upon receiving VDD, the second end of the switch Q35 is coupled to the HFVN output node NHN, and the second end of the switch Q36 is coupled to the HFVT output node NHT. Therefore, in the enable period of the test data line precharge signal TPIO (here, for example, in a high level state), the voltage values of the first precharge voltage HFVT and the second precharge voltage HFVN are raised to the power supply voltage VDD. do.

The NAND gate NA33 receives the low address signal X12B13B and the test write enable signal TWE, and the output terminal is coupled to the other input terminal of the NOR gate NO31 and the NOR gate NO32. The output terminal of the NOR gate NO31 controls whether the switch Q31 and the switch Q34 conduct, the output terminal of the NOR gate NO32 controls whether the switch Q32 and the switch Q33 conduct, and the first stage of the switch Q31 receives the power supply voltage VDD , The second stage is coupled to the first stage of the switch Q32 and the HFVT output node NHT, and the second stage of the switch Q32 is coupled to the ground voltage VSS, thus grounding the voltage level of the first precharge voltage HFVT to ground. The voltage applied to the threshold voltage of the switch Q31 can be set from the voltage VSS or the power supply voltage VDD. The first stage of the switch Q33 receives the power supply voltage VDD, and the second stage of the first stage and the HFVN output of the switch Q34. The second stage of the switch Q34 is coupled to the node NHN, and is coupled to the ground voltage VSS, thus applying the threshold level of the switch Q33 from the ground voltage VSS or the power supply voltage VDD to the voltage level of the second precharge voltage HFVN. You can do it with voltage.

Accordingly, the precharge voltage control circuit 310 generates the first precharge voltage HFVT and the second precharge voltage HFVN based on the precharge reference voltage HFV, while the test write enable signal TWE and the test data signal are generated. Further receiving TDA, the first precharge voltage HFVT and the second precharge voltage HFVN can be the voltage to which the threshold voltage of the transistor is applied from the power supply voltage VDD and the power supply voltage VDD, the ground voltage VSS, or the precharge reference voltage HFV. have.

Specifically, the NAND gate NA34 of the test comparison circuit 320 receives the low address signal X12B13B and the test data enable signal TDE, and outputs the same to the inverter INV34. The output terminal of the inverter INV34 is an input terminal of the inverter INV35 and a NAND gate. It is coupled to one input terminal of NA35, and the output terminal of inverter INV35 is coupled to one input terminal of NOR gate NO33. The non-inverting input terminal of the comparator 312 receives the test reference voltage TMREF, the inverting input terminal receives one of the first precharge voltage HFVT and the second precharge voltage HFVN from the transmission gate TG33 or the transmission gate TG34, and the comparator The output end of 312 is coupled to the other input end of the NAND gate NA35 and the NOR gate NO33. Here, the test reference voltage TMREF is a predetermined constant voltage value, and the voltage value is larger than 1/2 of the power supply voltage VDD or higher than the precharge reference voltage HFV and smaller than the power supply voltage VDD, for example, a test. The reference voltage TMREF is 3/4 of the power supply voltage VDD.

The switch Q37 is controlled by the output result of the control by the NAND gate NA35, the first stage is coupled to the power supply voltage VDD, the second stage is coupled to the test node NT, and the test node NT returns the test result TFAIL. Output The switch Q38 is controlled by the output result of the NOR gate NO33, the first stage is coupled to the test node NT, and the second stage is coupled to the ground voltage VSS. Therefore, the voltage level of the test result TFAIL becomes the power supply voltage VDD or the ground voltage VSS by the output result of the comparator 312.

The first stage of the switch Q39 is also coupled to the test node NT, and the second stage is coupled to the ground voltage VSS, controlled by the test data line precharge signal TPIO, and the enable period of the test data line precharge signal TPIO. In test results, the voltage level of TFAIL is reduced to the ground voltage VSS. A latch circuit 314 is also coupled to the test node NT and used to latch the voltage level of the test result TFAIL.

In simple terms, the test comparison circuit 320 compares one of the first precharge voltage HFVT and the second precharge voltage HFVN and the test reference voltage TMREF to generate a test result TFAIL so that the memory unit MC is in a bad state. And if one of the first precharge voltage HFVT and the second precharge voltage HFVN is greater than the test reference voltage TMREF, the test result TFAIL is, for example, one of the power supply voltage VDD and the ground voltage VSS. When the data detection of the memory unit MC is substantially the same and indicates that the first precharge voltage HFVT and the second precharge voltage HFVN are both less than the test reference voltage TMREF, the test result TFAIL is, for example, , Which is substantially equal to the other of the power supply voltage VDD and the ground voltage VSS, and indicates that data detection of the memory unit MC has failed. The following embodiments will be described in more detail with respect to an implementation manner in which the test read write and the memory unit MC determine whether the state is in poor condition.

6-8, FIG. 6-8 is a waveform diagram which shows the test write operation of logic "0" and logic "1" of the memory device based on the Example of this invention, respectively. 6 to 8 can be applied to the embodiment of FIGS. 1 to 5. In the test write operation, if one memory unit MC is taken as an example, Fig. 6 shows the word line signal WLn, the test write enable signal TWE, the sense enable signal SE1, SE2, and the first precharge in the corresponding word line WL. The operation waveform diagrams of the enable signal BLP1 and the second precharge enable signal BLP2 are shown. 7 shows a test write operation when the write data is logic "0", a first precharge voltage HFVT, a second precharge voltage HFVN, a p-channel control voltage SAP, an n-channel control voltage SAN, a bit line BLT, and a complementary bit. The operation waveform diagram of the voltage level of the line BLN is shown. As specifically explained, the thin straight lines shown in other symbols shown in FIGS. 7 and 8 show the waveform operation in FIG. 6, and the symbols are not indicated so that the drawings are not obfuscated. From 6, the meaning which these thin straight lines represent can be grasped.

First, referring to FIGS. 6 and 7 in parallel with FIG. 1 to FIG. 5, before the test of the first precharge voltage HFVT and the second precharge voltage HFVN, the transfer gate TG31 and the transfer gate TG32 are performed. It is conducted and maintained at the magnitude of the voltage value of the precharge reference voltage HFV. In the test write operation, in particular, in the test write detection period tW, the voltage value of one of the first precharge voltage HFVT and the second precharge voltage HFVN is lower than the power supply voltage VDD, but is higher than the precharge reference voltage HFV. The other voltage value is lower than the precharge reference voltage HFV and is substantially equal to the ground voltage VSS, for example.

First, assuming that data indicating logic "0" is to be written to the memory unit MC, the test data signal TDA is in a low level state, while the word line signal WLn and the test write enable signal TWE are at this time. Is at a high level, and thus, switches Q31 and Q34 are disconnected, switches Q32 and Q33 are conducted, where switches Q31 to Q34 all use n-channel transistors as an example, but not limited thereto. The voltage of the first precharge voltage HFVT provided by the control circuit 310 is reduced to the ground voltage VSS, and the second precharge voltage HFVN is equal to the voltage of the threshold voltage VTN of the n-channel transistor from the power supply voltage VDD. Is raised. As an explanation is needed, the voltage value of the power supply voltage VDD is larger than the sum of the voltages of the precharge reference voltage HFV and the threshold voltage VTN.

Subsequently, the precharge enable control circuit 210 switches the first precharge enable signal BLP1 from the original low level state to a high level state, but the second precharge enable signal BLP2 maintains the low level state. The first switch T1 and the second switch T2 are turned on to cut the third switch T3, and the bit line BLT and the complementary bit line BLN receive the first precharge voltage HFVT and the second precharge voltage HFVN, respectively. Can be.

Specifically, in the present embodiment, when performing a test write operation on the memory unit MC, on the other hand, the first precharge enable signal BLP1 is switched to the enabled state, that is, the first switch T1 and Before the second switch T2 conducts, the voltage levels of the first precharge voltage HFVT and the second precharge voltage HFVN are already different.

Subsequently, the sense amplification voltage control circuit 220 switches the p-channel control voltage SAP and the n-channel control voltage SAN from the precharge reference voltage HFV to the power supply voltage VDD and the ground voltage VSS, respectively. The voltage levels of the p-channel control voltage SAP and the n-channel control voltage SAN are originally kept lower than the power supply voltage VDD, where they are equal to the precharge reference voltage HFV and are in the enable period of the sense enable signals SE1 and SE2. , The switch Q21 and the switch Q22 are conducted, the p-channel control voltage SAP and the n-channel control voltage SAN are switched to the power supply voltage VDD and the ground voltage VSS, respectively, and greatly increase the voltage difference between the bit line BLT and the complementary bit line BLN. In the test write detection period tW, the voltage level of the bit line BLT is substantially equal to the ground voltage VSS, and the voltage level of the complementary bit line BLN is the power supply voltage VDD. Is stored.

Subsequently, referring to FIGS. 6 and 8 in parallel with FIG. 1 to FIG. 5, FIG. 8 shows a test write operation when writing data having logic "1", a first precharge voltage HFVT, and a second precharge. The operation waveform diagrams of the voltage HFVN, the p-channel control voltage SAP and the n-channel control voltage SAN are shown. In the test write operation, for example, attempting to write data representing logic "1" to the memory unit MC, the test data signal TDA is in a high level state, and in the test write detection period tW, the precharge voltage control circuit ( The voltage value of the first precharge voltage HFVT output by 310 is raised to the magnitude of the voltage applied to the threshold voltage VTN of the n-channel transistor from the power supply voltage VDD, and the voltage level of the second precharge voltage HFVN is the ground voltage VSS. The detailed implementation manners can be obtained by those skilled in the art from the above examples and general techniques, and are not described herein again.

9 to 11 are waveform diagrams each showing a test read operation of the memory device based on the embodiment of the present invention. 9 to 11 can be applied to the embodiment of FIGS. 1 to 8. 9 to 11, referring to FIGS. 9 to 11, in the test read operation, when any one memory unit MC is taken as an example, FIG. 9 shows the word line signals WLn, sense enable signals SE1 and SE2, The operation waveform diagrams of the test data line precharge signal TPIO, the test data enable signal TDE, the first precharge enable signal BLP1 and the second precharge enable signal BLP2 are shown. 10 and 11 show a first precharge voltage HFVT, a second precharge voltage HFVN, a p-channel control voltage SAP, an n-channel control voltage SAN, a bit when it is determined that the read result of the test read operation is success or failure, respectively. The operation waveform diagram of the voltage levels of the line BLT and the complementary bit line BLN is shown. As specifically explained, the thin straight lines shown in FIG. 10 and FIG. 11, which are explained by other symbols, show the waveform operation in FIG. 9, and the symbols are not indicated so that the drawings are not obfuscated. From 9, the meaning which these thin straight lines represent can be grasped | ascertained.

First, referring to FIGS. 9 and 10, before the test is performed on the first precharge voltage HFVT and the second precharge voltage HFVN, the transfer gate TG31 and the transfer gate TG32 are electrically connected to each other so that the precharge reference voltage HFV It is maintained at the magnitude of the voltage value.

When performing a test read operation on the memory unit MC, assuming that the memory unit MC reads data indicating a logic "0", the memory unit MC is in a high level state in the word line signal WLn, while the test read detection period tR Prior to this, first, the data line precharge operation is performed, that is, in the enable period of the test data line precharge signal TPIO, the conduction of the switch Q35, the switch Q36 and the switch Q39 causes the first precharge voltage HFVT and The second precharge voltage HFVN is first raised to a voltage substantially equal to the power supply voltage VDD, and the test node NT substantially receives the ground voltage VSS. Here, the switch Q35 and the switch Q36 are p-channel transistors, and the switch Q39 is an n-channel transistor as an example.

After completion of the data line precharge operation, the test data line precharge signal TPIO is set to disable (for example, low level state), and enables the sense enable signals SE1 and SE2 to enable the p-channel control voltage. The SAP and n-channel control voltage SAN are switched from the precharge reference voltage HFV to the power supply voltage VDD and the ground voltage VSS, respectively.

Subsequently, the first precharge enable signal BLP1 is switched from the original low level state to the high level state, and the second precharge enable signal BLP2 is maintained at the low level state. The first precharge enable signal BLP1 switched to the high-level state conducts the first switch T1 and the second switch T2, and tests all of the data of the memory unit MC in the same word line WL when detection is successful. In the read detection period tR, the voltage levels of the first precharge voltage HFVT and the second precharge voltage HFVN are different, and one of the first precharge voltage HFVT and the second precharge voltage HFVN is the power supply voltage VDD. The other voltage level is lowered to a voltage substantially equal to the ground voltage VSS, and in the embodiment of FIG. 9, the second precharge voltage HFVN is maintained at the power supply voltage VDD, while the first precharge is performed. As an example, the voltage HFVT is lowered to the ground voltage VSS.

Specifically, in the test write operation and the test read operation, the timing of switching the first precharge enable signal BLP1 from the low level state to the high level state is different, and specifically, the first precharge enable signal. When the BLP1 performs the test write operation, the timing for switching the voltage level is faster than the timing when the test read operation is performed. In the test write operation, the first precharge enable signal BLP1 switches to the high level state sooner than the sense enable signals SE1 and SE2, but in the test read operation, the first precharge enable signal BLP1 is sense-input. It switches to the high level state later than the enable signals SE1 and SE2.

Subsequently, the comparator 312 receives one of the test reference voltage TMREF and the first precharge voltage HFVT and the second precharge voltage HFVN, for example, that the voltage level is high. 312 receives the test reference voltage TMREF and the second precharge voltage HFVN, and the voltage value of the test reference voltage TMREF is 3/4 of the power supply voltage VDD, and the second precharge voltage HFVN is a power supply at this time. It is substantially equal to the voltage VDD. In the test read detection period tR, since the second precharge voltage HFVN is greater than the test reference voltage TMREF, the test reference voltage TMREF is in a low level state, for example, is substantially equal to the ground voltage VSS, Detection of all data of the memory unit MC in the same word line WL succeeds.

9 and 11, when data detection failure occurs in the memory unit MC in the same word line WL, the first precharge enable signal BLP1 is switched to a high level state, and the first switches T1 and the first switch are made. Since the voltage value is lowered to the ground voltage VSS after the two switches T2 are conducted, the signal which is originally in the high level state among the first precharge voltage HFVT and the second precharge voltage HFVN is smaller than the original voltage level.

In the present embodiment, the second precharge voltage HFVN is originally in a high level state, while the voltage value is substantially equal to the power supply voltage VDD, and the magnitude of the voltage value of the first precharge voltage HFVT is the ground voltage VSS. Is substantially the same. In the test read detection period tR, after the first switch T1 and the second switch T2 are conducted, the first precharge voltage HFVT is equal to the ground voltage VSS, but the voltage of the second precharge voltage HFVN is the power supply voltage VDD. The voltage of the second precharge voltage HFVN is reduced to the magnitude of the voltage to which the threshold voltage VTN of the n-channel transistor is applied from the power supply voltage VDD. The power supply voltage VDD is 1.5 V, and the threshold voltage VTN of the n-channel transistor is 0.7 V. Therefore, the reduced voltage of the second precharge voltage HFVN is about 1/2 of the power supply voltage VDD.

Subsequently, the comparator 312 receives and compares the test reference voltage TMREF and the second precharge voltage HFVN, and the voltage value of the test reference voltage TMREF is 3/4 of the initial power supply voltage VDD. The voltage value at this time of the two precharge voltages HFVN is equal to about half the magnitude of the power supply voltage VDD, and is smaller than the test reference voltage TMREF, so that the test result TFAIL is changed to a high voltage level. Indicates a state where the detection of data of the memory unit MC at the same word line WL has failed substantially.

9 to 11, one of the first precharge voltage HFVT and the second precharge voltage HFVN in the test read detection period tR when the test read operation is performed on the memory unit MC. The value is not larger than the power supply voltage VDD, but is higher than the precharge reference voltage HFV and the other voltage value is lower than the precharge reference voltage HFV and is equal to, for example, the ground voltage VSS.

In another embodiment, the first precharge voltage HFVT is in a high level state, while the comparator 312 may receive the test reference voltage TMREF and the first precharge voltage HFVT for comparison and perform a detailed implementation. The person skilled in the art can obtain sufficient teachings from the above description and general techniques, and will not be described repeatedly here.

Referring to Fig. 12, Fig. 12 is an operational waveform diagram showing test writing of logic " 0 " for all memory units by a memory device based on another embodiment of the present invention. This embodiment can be applied to the memory device 100 of the embodiment of FIGS. 1 to 11. In the embodiment of FIG. 12, after the power-up or reset state (RESET) of the memory device 100 is turned on, the memory device 100 is in the extended write cycle T, for example, 200 μs to 300 μs. Within the range of less than a second, in the embodiment of FIG. 12, for example, the extended write cycle T is about 300 μsec, for all word lines WL and all related sense amplification circuits 110 in the memory device 100. A write operation is performed, and the code omitted in FIG. 12 indicates this. That is, the memory device 100 of the present invention writes data of logic "0" to the memory units MC in all the word lines WL within a short time. With respect to the implementation manner of the operation waveform of FIG. 12, those skilled in the art can obtain sufficient teaching and presentation from the embodiment of FIGS. 6 to 8, and are not described herein again.

In the above, the present invention provides a memory device including a precharge voltage control circuit and a sense amplifier circuit. The precharge voltage control circuit generates a first precharge voltage and a second precharge voltage based on the precharge reference voltage. The sense amplifier is coupled between the bit line and the complementary bit line and used to detect data of the memory unit coupled to the bit line, while coupled to the precharge voltage control circuit, during the precharge operation, during the first precharge operation. The voltage levels of the charge voltage and the second precharge voltage are the same, and in the test write detection period and the test read detection period after the precharge operation, the first precharge provided by the precharge voltage control circuit to the bit line and the complementary bit line. The voltage levels of the voltage and the second precharge voltage are different. In this manner, it is possible to implement a parallel test mode by selecting a plurality of sense amplifiers on a word line in one cycle.

Although the main text is shown as in the above embodiments, the present invention is not intended to limit the present invention, and the scope of protection of the present invention can be changed or modified without departing from the technical scope of the present invention. Based on what is defined in the claims.

The detector provided by the present invention completes the detection operation of the data bus inversion function at low power consumption. In the memory device, the efficiency of the data bus inversion function is effectively improved. On the other hand, the data access efficiency of the electronic device described in the memory device is also effectively improved.

100 ： memory circuit
110 ： sense amplification circuit
120 ： control test circuit
130 ： memory array
140 ： X decoder block
150 ： Y decoder block
160 ： Sense amplifier block
200 ： Sense control circuit
210 ： Precharge enable control circuit
220: sense amplification voltage control circuit
300 ： test read write circuit
310 ： Precharge voltage control circuit
312 ： Comparator
314 ： latch circuit
320 ： Test comparison circuit
BLT ： Bit line
BLN ： Complementary bit line
BLPE1: Precharge Enable Signal
BLP1: First precharge enable signal
BLP2 ： 2nd precharge enable signal
HFV ： Precharge Reference Voltage
HFVT ： 1st precharge voltage
HFVN ： 2nd precharge voltage
INV ： Inverter
MC ： Memory unit
N1: First intermediate node
N2: Second intermediate node
NP: SAP output node
NN ： SAN output node
NHT ： HFVT output node
NHN ： HFVN output node
NT ： Test node
NA21 to NA23, NA31 to NA35: NAND gate
NO31 ~ NO33 ： NOR gate
Q1, Q2, Q3, Q4 ： Transistor
Q21 ~ Q25, Q1 ~ Q39 ： Switch
SA ： Sense circuit
SE1, SE2: Sense enable signal
SAP: p-channel control voltage
SAN ： n-channel control voltage
T ： Extended write cycle
T1 ： First switch
T2 ： 2nd switch
T3 ： Third switch
TFAIL ： Test result
TG31-TG34 ： Transmission gate
TWE ： Test write enable signal
TDA ： Test data signal
TDE: test data enable signal
TEST ： Test enable signal
TPIO: Test data line precharge signal
tR: Test read detection period
tW: Test write detection period
TMREF: Test Reference Voltage
VDD ： Power supply voltage
VSS ： Ground Voltage
VTN: threshold voltage of n-channel transistor
WL ： Word line
WLn, WLm ： Word line signal
X12B13B: Low address signal

Claims (16)

A precharge voltage control circuit that generates a first precharge voltage and a second precharge voltage based on the precharge reference voltage,
Coupled between the bit line and the complementary bit line, used to detect data of a memory unit coupled to the bit line, coupled to the precharge voltage control circuit, and to the bit line and the complementary bit line, respectively, A sense amplifier circuit for receiving a first precharge voltage and the second precharge voltage;
During the precharge operation, the voltage levels of the first precharge voltage and the second precharge voltage are the same, and in the test write detection period and the test read detection period after the precharge operation, the precharge voltage control circuit performs the above-mentioned operation. Voltage levels of the first precharge voltage and the second precharge voltage provided to the bit line and the complementary bit line are different from each other.
Memory device. The method of claim 1,
The sense amplifier circuit,
A first stage receiving the first precharge voltage, a second stage coupled to the bit line, the first switch being controlled by a first precharge enable signal;
A first switch receiving the second precharge voltage and a second switch coupled to the complementary bit line and controlled by the first precharge enable signal;
A third switch coupled between the bit line and the complementary bit line and controlled by a second precharge enable signal;
A sense circuit coupled between the bit line and the complementary bit line and used to increase the voltage difference between the bit line and the complementary bit line.
Memory device comprising a. The method of claim 2,
A precharge enable control circuit coupled to the sense amplification circuit, the precharge enable control circuit generating the first precharge enable signal and the second precharge enable signal based on a precharge enable signal;
More,
When a test write operation and a test read operation are performed on the memory unit, the voltage level of the first precharge enable signal is switched and the logic level of the second precharge enable signal is the first precharge in. Unlike the enable signal, after completion of the test write operation and the test read operation, the voltage level of the second precharge enable signal is switched to restore the same level as the logic level of the first precharge enable signal.
Memory device. The method of claim 1,
A test comparison circuit coupled to the precharge voltage control circuit and comparing one of the first precharge voltage and the second precharge voltage and a test reference voltage to generate a test result
More,
When one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, the test result indicates that data detection of the memory unit is successful, and the first precharge voltage and the second precharge voltage are successful. When both precharge voltages are less than the test reference voltage, the test result indicates that data detection of the memory unit has failed.
Memory device. The method of claim 4, wherein
The voltage level of the test reference voltage is higher than the precharge reference voltage and smaller than the power supply voltage.
Memory device. The method of claim 5,
When one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, the voltage value of the test result is substantially equal to one of the power supply voltage and the ground voltage, and the first precharge When both the voltage and the second precharge voltage are less than the test reference voltage, the voltage value of the test result is substantially equal to the other of the power supply voltage and the ground voltage.
Memory device. The method of claim 1,
In the test write detection period, one of the first precharge voltage and the second precharge voltage is lower than the power supply voltage, but is higher than the precharge reference voltage and the other voltage value is referred to the precharge. Lower than voltage
Memory device. The method of claim 1,
When performing the test read operation on the memory unit, before performing the test read detection, the first precharge voltage and the second precharge voltage are first raised to a voltage substantially equal to the power supply voltage.
Memory device. In the read-write method for a memory device, which is used to perform a test write operation and a test read operation on a memory unit,
Generating a first precharge voltage and a second precharge voltage based on the precharge reference voltage;
Receiving the first precharge voltage and the second precharge voltage, respectively, in a bit line and a complementary bit line
Including,
During the precharge operation, the voltage level of the first precharge voltage and the second precharge voltage is the same, and in the test write detection period and the test read detection period after the precharge operation, the precharge voltage control circuit is configured to execute the bit. The voltage levels of the first precharge voltage and the second precharge voltage provided to the line and the complementary bit line are different.
Read write method. The method of claim 9,
A first switch and a second switch are controlled by a first precharge enable signal to determine whether the bit line and the complementary bit line receive the first precharge voltage and the second precharge voltage, respectively. And
Controlling a third switch by a second precharge enable signal to determine whether to electrically connect the bit line and the complementary bit line;
Increasing the voltage difference between the bit line and the complementary bit line by a sense circuit
Read and write method that includes more. The method of claim 10,
Generating the first precharge enable signal and the second precharge enable signal based on a precharge enable signal
More,
When the test write operation and the test read operation are performed on the memory unit, a voltage level of the first precharge enable signal is switched, and a logic level of the second precharge enable signal is set to the first precharge. Unlike the charge enable signal, after completion of the test write operation and the test read operation, the voltage level of the second precharge enable signal is switched to recover to the same level as the logic level of the first precharge enable signal. doing
Read write method. The method of claim 9,
Comparing one of the first precharge voltage and the second precharge voltage and a test reference voltage to generate a test result
More,
When one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, the test result indicates that data detection of the memory unit is successful, and the first precharge voltage and the second precharge voltage are successful. When both precharge voltages are less than the test reference voltage, the test result indicates that data detection of the memory unit has failed.
Read write method. The method of claim 12,
The voltage level of the test reference voltage is higher than the precharge reference voltage and smaller than the power supply voltage.
Read write method. The method of claim 13,
When one of the first precharge voltage and the second precharge voltage is greater than the test reference voltage, the voltage value of the test result is substantially equal to one of the power supply voltage and the ground voltage, and the first precharge When both the voltage and the second precharge voltage are less than the test reference voltage, the voltage value of the test result is substantially equal to the other of the power supply voltage and the ground voltage.
Read write method. The method of claim 9,
In the test write detection period, one of the first precharge voltage and the second precharge voltage is lower than the power supply voltage, but is higher than the precharge reference voltage and the other voltage value is referred to the precharge. Lower than voltage
Read write method. The method of claim 9,
When performing the test read operation on the memory unit, before performing the test read detection, the first precharge voltage and the second precharge voltage are first raised to a voltage substantially equal to the power supply voltage.
Read write method.

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