CN118430609A

CN118430609A - Random access memory

Info

Publication number: CN118430609A
Application number: CN202310088537.7A
Authority: CN
Inventors: 邓鹏�; 杨一哲
Original assignee: Shanghai Geyi Electronic Co ltd
Current assignee: Shanghai Geyi Electronic Co ltd
Priority date: 2023-02-02
Filing date: 2023-02-02
Publication date: 2024-08-02

Abstract

The application discloses a random access memory, which comprises a plurality of column gating modules, wherein each column gating module determines whether a current complementary bit line pair is gated with a connected complementary input/output line pair based on a corresponding column gating signal; the column gating signals comprise first column gating signals and second column gating signals, wherein the first column gating signals are column gating signals for controlling the corresponding column gating modules to be conducted, and the second column gating signals are column gating signals for controlling the corresponding column gating modules to be cut off; when the write data corresponding to the current write operation executed by the random access memory is non-mask data, the column gating signal received by the column gating module corresponding to the current write operation is a first column gating signal, and when the write data corresponding to the current write operation executed by the random access memory is mask data, the column gating signal received by the column gating module corresponding to the current write operation is a second column gating signal. By the mode, the power consumption of the random access memory can be reduced.

Description

Random access memory

Technical Field

The application relates to the technical field of storage, in particular to a random access memory.

Background

The memory array of the memory includes a plurality of Word Lines (WL), a plurality of Bit Lines (BL) and a plurality of memory cells, each of which is connected to one of the word lines WL and one of the Bit Lines (BL), respectively.

Further, the memory array further comprises an input/output line pair (IO/IO#) which is connected with a bit line pair (BL/BL#) which is selected by the column selection circuit during data reading/writing so as to exchange data, thereby realizing data reading/writing.

During the continuous writing operation, after each data writing, an equalization (Equalize) stage is included to charge the input/output line pair (IO/io#).

Disclosure of Invention

In order to solve the above problems, the present application provides a random access memory and an input/output circuit thereof, which can reduce circuit power consumption.

In order to solve the technical problems, the application adopts a technical scheme that: there is provided a random access memory including: the memory array comprises a plurality of word lines, a plurality of bit lines and a plurality of memory cells, wherein each memory cell is respectively connected with one word line and a pair of complementary bit lines; complementary input-output line pairs; a column selection circuit including a plurality of column strobe modules, wherein each column strobe module is respectively connected with a pair of complementary bit lines to determine whether a current complementary bit line pair is strobed with a connected complementary input/output line pair based on a corresponding column strobe signal; the column gating signals comprise first column gating signals and second column gating signals, wherein the first column gating signals are column gating signals for controlling the corresponding column gating modules to be conducted, and the second column gating signals are column gating signals for controlling the corresponding column gating modules to be cut off; when the write data corresponding to the current write operation executed by the random access memory is non-mask data, the column gating signal received by the column gating module corresponding to the current write operation is a first column gating signal, and when the write data corresponding to the current write operation executed by the random access memory is mask data, the column gating signal received by the column gating module corresponding to the current write operation is a second column gating signal.

Wherein the column selection circuit includes: a judging circuit for determining whether the write data corresponding to the current write operation is mask data based on the mask signal; and a column selection signal generation circuit outputting the first column selection signal or the second column selection signal based on the judgment result of the judgment circuit.

The judging circuit determines whether write data corresponding to the current write operation is mask data or not based on the first mask signal and the second mask signal.

Wherein the column selection communication generation circuit includes: a first column strobe signal generating unit that generates a first column strobe signal based on the write command; the second column selection signal generating unit is connected with the first column selection signal generating unit and the judging circuit and outputs a first column selection signal or a second column selection signal based on the first column selection signal and a judging result signal output by the judging circuit; wherein the logic potentials of the first column strobe signal and the second column strobe signal are opposite.

Wherein, the judging circuit includes: and the NOR logic gate has a first input end receiving the first shielding signal, a second input end receiving the second shielding signal, and an output end for outputting the judging result signal.

Wherein the second column selection communication generation unit includes: and the logic gate, the first input end of which receives the judging result signal, the second input end of which receives the first column strobe signal, and the output end of which is used for outputting the first column strobe signal or the second column strobe signal.

The first shielding signal is a DM signal, and the judging circuit determines whether the write data corresponding to the current write operation is shielding data according to the logic potential of the DM signal; and/or the second shielding signal is a BC4 signal, and the judging circuit determines whether the write data corresponding to the current write operation is shielding data according to the logic potential of the BC4 signal.

Wherein, further include: and the sensitive amplifying module is coupled with the complementary input-output line pair to perform signal amplifying operation on the corresponding complementary input-output line pair.

Wherein, the sense amplifier module includes: the first inversion unit is coupled between the corresponding target input output line and the complementary input output line, and pulls the complementary input output line voltage on the complementary input output line to the strong potential of the first logic, which is opposite to the potential represented by the written data, based on the written data on the target input output line during the writing operation; and a second inverting unit coupled between the complementary input output line and the target input output line, wherein the second inverting unit pulls the target input output line voltage on the target input output line to a strong potential of a second logic, the second logic being the same as the potential logic characterized by the write data, in response to the complementary input output line voltage on the complementary input output line being pulled to the strong potential of the first logic.

Wherein the first inverting unit includes: a first switch T10 having a first path terminal coupled to the complementary input/output line and a second path terminal connected to a logic high level sense voltage amplification line (SAP); a second switch T11 having a first path terminal connected to the complementary input/output line and a second path terminal connected to a logic low level sense voltage amplification line (SAN); the second inversion unit includes: a third switch T12 having a first path terminal coupled to the target input/output line and a second path terminal connected to a logic high level sense voltage amplification line (SAP); a fourth switch T13 having a first path terminal connected to the target input/output line and a second path terminal connected to a logic low level sense voltage amplification line (SAN); the control ends of the first switch and the second switch receive write voltage signals corresponding to write operation, the first switch or the second switch is turned on in response to the write voltage signals, and the complementary input and output line voltage on the complementary input and output line is pulled to the strong potential of the first logic by utilizing a logic high-level sensitive voltage amplification line (SAP) or a logic low-level sensitive voltage amplification line SAN; in response to the complementary input-output line voltage being pulled to the strong potential of the first logic, the fourth switch or the third switch is turned on, and the target input-output line voltage on the target input-output line is pulled to the strong potential of the second logic using the logic low level sense voltage amplification line SAN or the logic high level sense voltage amplification line SAP.

The random access memory has the beneficial effects that the column selection signal generated by the column selection circuit comprises a first column selection signal and a second column selection signal, wherein the first column selection signal is a column selection signal for controlling the corresponding column selection module to be conducted, and the second column selection signal is a column selection signal for controlling the corresponding column selection module to be cut off; when the write data corresponding to the current write operation executed by the random access memory is non-mask data, the column gating signal received by the column gating module corresponding to the current write operation is a first column gating signal, and when the write data corresponding to the current write operation executed by the random access memory is mask data, the column gating signal received by the column gating module corresponding to the current write operation is a second column gating signal. By the mode, the input writing can be controlled only through the column gating signals, when the writing data needs to be shielded, the writing of the data is prevented, a second initialization module for charging and balancing between the input and output line pairs can be omitted, the power consumption of the circuit is reduced, and the performance of the random access memory is further improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:

FIG. 1 is a schematic diagram of a memory array of a random access memory according to the present application;

FIG. 2 is a schematic diagram illustrating an embodiment of the first initialization module in FIG. 1;

FIG. 3 is a schematic diagram of an embodiment of the first sense amplifier module of FIG. 1;

FIG. 4 is a circuit diagram of an embodiment of the first sense amplifier module of FIG. 3;

FIG. 5 is a schematic diagram of a first embodiment of the column select circuit of FIG. 1;

FIG. 6 is a schematic diagram of an embodiment of the I/O circuit of FIG. 1;

FIG. 7 is a circuit diagram of an embodiment of the second sense amplifier module of FIG. 6;

FIG. 8 is a schematic diagram of potential trend of an embodiment of a random access memory according to the present application;

FIG. 9 is a signal diagram corresponding to FIG. 7;

FIG. 10 is a schematic diagram of a second embodiment of the column select circuit of FIG. 1;

FIG. 11 is a schematic diagram of a third embodiment of the column select circuit of FIG. 1;

FIG. 12 is a schematic diagram of a specific circuit corresponding to FIG. 11;

Fig. 13 is a schematic structural diagram of a random access memory according to the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present application are shown in the drawings. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a memory array of a random access memory according to the present application, the memory array 100 includes a plurality of Word Lines (WL), a plurality of complementary bit lines (BL and bl#) and a plurality of memory cells 110, wherein each memory cell 110 is connected to one WL and a pair of complementary bit lines (BL and bl#).

In an embodiment in which the random access memory is a dynamic random access memory (Dynamic Random Access Memory, DRAM), each memory cell 110 includes an access switch and a storage capacitor. The storage capacitor represents logical "1" and "0" by the more and less of the charge stored therein, or the high and low of the voltage difference across the storage capacitor. The on and off of the access switch determines whether to permit or prohibit reading and writing of information stored in the storage capacitor.

Specifically, the word line WL determines on or off of the access switch, the bit line BL is the only channel for external access to the storage capacitor, and after the access switch is turned on, external access can perform read or write operations on the storage capacitor through the bit line BL.

In one embodiment, the Common terminal (Common) of the storage capacitors is connected to Vcc/2.

When the information stored in the storage capacitor is "1", the voltage at the other end of the storage capacitor is Vcc, and at this time, the stored charge is:

Q＝+Vcc/2*C

When the information stored in the storage capacitor is "0", the voltage at the other end of the storage capacitor is 0, and at this time, the stored charge is:

Q＝-Vcc/2*C

Further, the memory array 100 further includes a first initialization module 120, a first sense amp module 130 (SENSE AMPLIFIER, SA), a column select circuit 140, and an input-output circuit 150.

The first initialization module 120 is connected to a pair of complementary bit lines (BL/bl#) for charging the target bit line BL and the complementary bit line bl#) to an initialization potential in a precharge phase (precharge). The first sense amplifier module 130 is connected to a pair of complementary bit lines (BL/bl#) for amplifying the logic potential on the target bit line BL to a corresponding strong potential when the memory cell 110 connected to the target bit line BL is turned on by the Word Line (WL). The input/output circuit 150 includes a pair of complementary input/output lines (IO/io#), and the column selection circuit 140 includes a plurality of column strobe modules 141 and a column strobe signal generation circuit 142, where each column strobe module 141 is respectively connected to a pair of complementary bit lines to determine whether the current complementary bit line pair is strobed with the connected complementary input/output line pair (IO/io#) based on the corresponding column strobe signal generated by the column strobe signal generation circuit 142.

Referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of the first initialization module in fig. 1, where the first initialization module 120 includes a switch T1, a switch T2, and a switch T3, control terminals of the switch T1, the switch T2, and the switch T3 receive a first precharge control signal EQ1, a first pass terminal of the switch T1 is connected to a target bit line BL, a first pass terminal of the switch T2 is connected to a complementary bit line bl#, second pass terminals of the switch T1 and the switch T2 are connected to an initialization potential Vref (vref=1/2 Vcc in an embodiment), a first pass terminal of the switch T3 is connected to the target bit line BL, and a second pass terminal of the switch T3 is connected to the complementary bit line bl#.

In the precharge phase (precharge), the first precharge control signal EQ1 controls the switches T1 and T2 to be turned on, and charges the target bit line BL and the complementary bit line bl# with the initialization potential Vref so that the potentials of the target bit line BL and the complementary bit line bl# are the initialization potentials. Further, the first precharge control signal EQ1 controls the switch T3 to be turned on so that the potentials of the target bit line BL and the complementary bit line bl# remain identical.

Alternatively, the above-mentioned switches T1, T2 and T3 may be nMOS transistors.

Referring to fig. 3, fig. 3 is a schematic structural diagram of an embodiment of the first sense amplifying module in fig. 1, and the first sense amplifying module 130 includes a first inverting unit 131 and a second inverting unit 132.

The first inversion unit 131 is connected between the target bit line BL and the complementary bit line bl#, wherein when the memory cell 110 connected to the target bit line BL is turned on, the target bit line voltage V _BL on the target bit line BL is shifted from the initialization potential Vref according to the logic potential stored in the memory cell 110, and the first inversion unit 131 inverts based on the shifted target bit line voltage V _BL to pull the complementary bit line voltage V _BL# on the complementary bit line bl#, to the strong potential of the first logic.

The second inversion unit 132 is connected between the complementary bit line bl# and the target bit line BL, wherein when the complementary bit line voltage V _BL# of the complementary bit line bl# is pulled to the strong potential of the first logic, the second inversion unit 132 inverts based on the complementary bit line voltage V _BL# to pull the target bit line voltage V _BL of the target bit line BL to the strong potential of the second logic, which is opposite to the first logic.

Referring to fig. 3 and fig. 4, fig. 4 is a circuit schematic of an embodiment of the first sense amplifier module in fig. 3, wherein the first inverting unit 131 includes an nMOS transistor T4 and a pMOS transistor T5, and the second inverting unit 132 includes an nMOS transistor T6 and a pMOS transistor T7.

Referring to fig. 5, fig. 5 is a schematic diagram of an embodiment of the column selection circuit in fig. 1, where the column selection circuit 140 includes a column selection signal generating circuit 142 and a plurality of column strobe modules 141, and each column strobe module 141 is respectively connected to a pair of complementary bit lines (BL/bl#) to determine whether the current complementary bit line pair (BL/bl#) is strobed with the connected complementary input/output line pair (IO/io#) based on the corresponding column selection signal YS generated by the column selection signal generating circuit 142.

The column selection module 141 includes a switch T8 and a switch T9, and control ends of the switch T8 and the switch T9 are connected to a column selection signal generating circuit 142, for receiving a corresponding column selection signal YS; the first path end of the switch T8 is connected with the target bit line BL, the second path end is connected with the first input output line IO, the first path end of the switch T9 is connected with the complementary bit line BL#, and the second path end is connected with the second input output line IO#.

Specifically, when the corresponding column selection communication control switch T8 and the switch T9 generated by the column selection communication generation circuit 142 are turned on, the target bit line BL is connected to the first input/output line IO, and the complementary bit line bl# is connected to the second input/output line io#, so as to realize gating of the complementary bit line pair (BL/bl#) and the complementary input/output line pair (IO/io#). In a Write operation (Write), charging/discharging the complementary bit line (BL/BL#) through the complementary input-output line pair (IO/IO#) to rewrite a signal on the complementary input-output line pair (IO/IO#) to a voltage on the complementary bit line pair (BL/BL#); in a Read operation, a signal on the complementary bit line pair (BL/BL#) is output to the complementary input/output line pair (IO/IO#).

Alternatively, the above-described switches T8 and T9 may be nMOS transistors.

Referring to fig. 6, fig. 6 is a schematic structural diagram of a first embodiment of the input-output circuit in fig. 1, and the input-output circuit 150 includes a second sense amplifying module 151. The second sense amplifier module 151 is coupled to the complementary input/output line pair (IO/io#) to perform a signal amplifying operation on the corresponding complementary input/output line pair (IO/io#). The second sense amp module 151 can be generally implemented by a latch circuit combination.

Specifically, the second sense amplifying module 151 includes a third inverting unit 1511 and a fourth inverting unit 1512. The third inverting unit 1511 is coupled between the corresponding target input output line IO and the complementary input output line io#, and during a write operation, the third inverting unit 1511 pulls the complementary input output line voltage vio# on the complementary input output line io# to a strong potential of the first logic, which is logically opposite to the potential characterized by the write data, based on the write data on the target input output line io#.

The fourth inverting unit 1512 is coupled between the complementary input output line io# and the target input output line io# wherein, in response to the complementary input output line voltage vio# on the complementary input output line io# being pulled to a strong potential of the first logic, the fourth inverting unit 1512 pulls the target input output line voltage VIO on the target input output line IO to a strong potential of the second logic, the second logic being the same as the potential logic characterized by the written data.

Specifically, referring to fig. 7, the third inverting unit 1511 includes: a switch T10 and a switch T11. The fourth inverting unit 1512 includes: a switch T12 and a switch T13.

The first path end of the switch T10 is coupled with the complementary input output line IO#, and the second path end of the switch T10 is connected with a logic high level sensitive voltage amplifying line (SAP);

a first path end of the switch T11 is connected with a complementary input output line IO#, and a second path end of the switch T is connected with a logic low level sensitive voltage amplification line (SAN);

The switch T12 has a first path terminal coupled to the target input/output line IO and a second path terminal connected to a logic high level sensitive voltage amplifying line (SAP).

A first path terminal of the switch T13 is connected to the target input/output line IO, and a second path terminal thereof is connected to a logic low level sense voltage amplification line (SAN).

In some embodiments, the control terminals of the switch T10 and the switch T11 receive a write voltage signal corresponding to a write operation, and in response to the write voltage signal, the switch T11 is turned on and pulls the complementary input output line voltage vio# on the complementary input output line io# to a strong potential of the first logic by using the logic low level sense voltage amplification line SAN; in response to the complementary input-output line voltage vio# being pulled to the strong potential of the first logic, the switch T12 is turned on and pulls the target input-output line voltage VIO on the target input-output line IO to the strong potential of the second logic using the logic high level sense voltage amplification line SAP.

In some embodiments, the control terminals of the switch T10 and the switch T11 receive a write voltage signal corresponding to a write operation, and in response to the write voltage signal, the switch T10 is turned on and pulls the complementary input output line voltage vio# on the complementary input output line io# to a strong potential of the first logic using a logic low level sense voltage amplification line (SAN); in response to the complementary input-output line voltage vio# being pulled to the strong potential of the first logic, the switch T13 turns on and pulls the target input-output line voltage VIO on the target input-output line IO to the strong potential of the second logic using a logic low level sense voltage amplification line (SAN).

The write operation described above may be a write 1 operation or a write 0 operation.

Specifically, the switches T10 and T12 are pMOS transistors, and the switches T11 and T13 are nMOS transistors.

At this time, whether the write data needs to be written is controlled by the column selection circuit 140 according to the logic levels of the complementary input output line io# and the target input output line IO.

Referring to fig. 8 in combination with fig. 1-7, fig. 8 is a schematic potential trend diagram of an embodiment of the dynamic random access memory according to the present application, and the following describes the operation of the dynamic random access memory according to the present embodiment in a Read operation (Read) process, which includes a precharge phase, an access phase, a sense amplification phase, and a restore phase.

Precharge phase:

At this stage, the voltages on the target bit line BL and the complementary bit line bl# are stabilized on Vref by first turning on the switches T1, T2, T3 by the control signal EQ1, assuming vref=vcc/2. And then proceeds to the next stage.

Access phase:

through the precharge phase, the voltages on the target bit line BL and the complementary bit line bl# have stabilized at Vref, at which point the access switch in the memory cell 110 is turned on by controlling the word line WL (applying a voltage to the word line WL by an Active command). Positive charge stored in the storage capacitor in the memory cell 110 (e.g., vcc/2 for the common single-ended voltage of the capacitor and Vcc for the other end if the memory cell 110 stores a "1") flows to the target bit line BL, which in turn shifts the voltage of the target bit line BL upward to vref+. If the memory cell 110 stores a "0," the voltage of the target bit line BL is shifted downward to Vref-. And then proceeds to the next stage.

Sense phase:

Assume that the storage unit 110 stores "1": since the voltage of the target bit line BL is shifted up to Vref+ during the access phase, SAN is set to a strong potential of logic "0" and SAP is set to a strong potential of logic "1". Since the "1" stored in the memory cell 110 pulls up the voltage of the target bit line BL to Vref+, and the voltage of the complementary bit line BL# is still Vref, the switch T4 in FIG. 4 is more conductive than the switch T6, and the voltage on the complementary bit line BL# is pulled to a strong potential of logic "0" by SAN due to the conduction of T4. Since the gate of T7 is turned on at this time with a strong "0", the voltage on the target bit line BL is also pulled to a strong potential of logic "1" by SAP faster due to the conduction of T7. Then, the switch T4 and the switch T7 are turned on, and the switch T5 and the switch T6 are turned off. Finally, the voltages on the target Bit line BL and the complementary Bit line BL# both enter a steady state, and the voltage on the target Bit line BL correctly presents the information Bit ("1") stored by the storage capacitance in the memory cell 110.

Assume that the storage unit 110 stores "0": in the access phase, the voltage on the target bit line BL is shifted downward to Vref-, and since the voltage on the complementary bit line BL# is still Vref, the switch T5 in FIG. 4 is more conductive than the switch T7, and the voltage on the complementary bit line BL# is pulled to the strong potential of logic "1" by SAP due to the conduction of T5. Since the gate of T6 is now turned on with a strong "0", the voltage on the target bit line BL will also be pulled to a strong potential of logic "0" by SAN faster due to the turn-on of T6. Then the switches T5 and T6 enter the on state, and the switches T4 and T7 enter the off state. Finally, the voltages on the target Bit line BL and the complementary Bit line BL# both enter a steady state, and the voltage on the target Bit line BL correctly presents the information Bit ("0") stored by the storage capacitance in the memory cell 110.

Restore stage:

After the sense phase operation is completed, the target bit line BL is at a stable strong potential Vcc of logic "1" or logic "0", and the target bit line BL charges or discharges the storage capacitor in the memory cell 110. After a certain time, the charge of the storage capacitor can be restored to the state before the read operation.

Finally, as shown in fig. 5, the column selection signal generating circuit controls the YS signal to make the switch T8 and the switch T9 enter a conducting state, and outputs a strong "1" or a strong "0" signal on the target bit line BL to the IO line, so that the outside can read specific information. It should be noted that the restore phase is performed automatically during the word line WL on period, so that it is also possible for the read operation to perform the restore operation after the YS signal is turned on.

The above procedure describes a complete read operation, the pre-flow of the write operation is the same as the read operation, and precharge, access, sense and restore phase operations are performed. The difference is that the restore phase includes a write phase and then a write recovery operation is performed as follows:

As shown in fig. 5, the column gate signal generation circuit 142 controls the column gate signal YS to put the switch T8 and the switch T9 into the on state, and the signal of the input/output line IO rewrites the target bit line BL. At this time, if "0" is written, the target bit line BL will be pulled to logic "0" potential, and the complementary bit line BL# will be pulled to logic "1" potential; if a "1" is written, the target bit line BL is pulled to a logic "1" level and the complementary bit line BL# is pulled to a logic "0" level.

And then doing write recovery: after a certain time (i.e., tWR), when the charge of the storage capacitor in the memory cell 110 is discharged to the "0" state or charged to the "1" state by the voltage on the target bit line BL, the operation of writing "0" or "1" is completed by controlling the word line WL to turn off the switch in the memory cell 110.

Referring to fig. 5 and fig. 7, during a read/write operation, the column selection signal generation circuit 142 generates a column selection signal YS to control a corresponding column selection module 141 (e.g., the switch T8 and the switch T9) to be turned on, and further connects a bit line pair (BL/bl#) to an input/output line pair (IO/io#), and writes data into the corresponding bit line pair (BL/bl#) through the input/output line pair (IO/io#). After the bit line pair (BL/BL#) is read and written, the input/output line pair (IO/IO#) is charged and equalized (Equalize) to a relatively high potential (logic high potential, typically Vcc) for the next read/write operation.

With further reference to fig. 9, fig. 9 is a schematic diagram of signals corresponding to fig. 7.

During a write 1 operation, the input output line pair (IO/io#) is driven to be pulled to be high and low by the second sense amplifying module 151, during a write 0 operation, the input output line pair (IO/io#) is driven to be pulled to be at 0 potential by the second sense amplifying module 151, and in response to DM being at logic low potential, the column strobe signal YS is switched to be at logic high potential, the column strobe module 141 is controlled to be turned on, data information is transmitted to the bit line pair BL/bl#, and amplified data is further written into the memory cell under the amplifying action of the first sense amplifying module 130.

In response to DM being a logic high potential, switching column strobe signal YS to a logic low potential, controlling column strobe module 141 to turn off, disabling writing of data information to bit line pair BL/BL#.

In another embodiment of the column selection circuit 140, still referring to fig. 7, in this embodiment, the column strobe signal YS includes a first column strobe signal and a second column strobe signal, where the first column strobe signal is a column strobe signal for controlling the corresponding column strobe module 141 to be turned on, and the second column strobe signal is a column strobe signal for controlling the corresponding column strobe module 141 to be turned off; when the write data corresponding to the current write operation executed by the random access memory is non-mask data, the column gating signal received by the column gating module 141 corresponding to the current write operation is a first column gating signal, and when the write data corresponding to the current write operation executed by the random access memory is mask data, the column gating signal received by the column gating module 141 corresponding to the current write operation is a second column gating signal.

Optionally, in an embodiment, the column selection module 141 includes a switch T8 and a switch T9, and control ends of the switch T8 and the switch T9 are connected to the column selection signal generating circuit 142, for receiving the corresponding column selection signal YS; the first path end of the switch T8 is connected with a target bit line BL, the second path end is connected with a target input/output line IO, the first path end of the switch T9 is connected with a complementary bit line BL#, and the second path end is connected with a complementary input/output line IO#.

Alternatively, in an embodiment, the switches T8 and T9 may be nMOS transistors, and when the column strobe signal is a logic high "1", the column strobe signal may be considered to be a first column strobe signal, and when the column strobe signal is a logic low "0", the column strobe signal may be considered to be a second column strobe signal.

Specifically, when the write data corresponding to the current write operation performed by the random access memory is non-mask data, the column selection signal generation circuit 142 generates a first column strobe signal with the corresponding column selection signal YS at a logic high potential "1", so as to control the switch T8 and the switch T9 to be turned on, the target bit line BL is connected to the target input/output line IO, and the complementary bit line bl# is connected to the complementary input/output line io#, so as to realize the gating of the complementary bit line pair (BL/bl#) and the complementary input/output line pair (IO/io#). In a Write operation (Write), the complementary bit line (BL/BL#) is charged/discharged through the complementary input-output line pair (IO/IO#) to rewrite a signal on the complementary input-output line pair (IO/IO#) to a voltage on the complementary bit line pair (BL/BL#).

Specifically, when the write data corresponding to the current write operation performed by the random access memory is the mask data, the column selection signal generation circuit 142 generates the second column strobe signal with the corresponding column selection signal YS being the logic low potential "0", so as to control the switch T8 and the switch T9 to be turned off, the complementary bit line pair (BL/bl#) and the complementary input/output line pair (IO/io#) are not strobed, and the signal on the complementary input/output line pair (IO/io#) does not rewrite the voltage on the complementary bit line pair (BL/bl#) and the corresponding write data is not written into the corresponding memory cell.

It is noted that the above embodiment achieves the purpose of masking data by turning off the switches T8 and T9 by the second column strobe signal during the write operation for the data to be masked when the data is written. Accordingly, the initialization module corresponding to the complementary input/output line pair (IO/io#) as in the related art is not needed in the present embodiment.

The random access memory provided in this embodiment, wherein the column selection signal generated by the column selection circuit includes a first column strobe signal and a second column strobe signal, where the first column strobe signal is a column strobe signal for controlling the corresponding column strobe module to be turned on, and the second column strobe signal is a column strobe signal for controlling the corresponding column strobe module to be turned off; when the write data corresponding to the current write operation executed by the random access memory is non-mask data, the column gating signal received by the column gating module corresponding to the current write operation is a first column gating signal, and when the write data corresponding to the current write operation executed by the random access memory is mask data, the column gating signal received by the column gating module corresponding to the current write operation is a second column gating signal. By the mode, the input writing can be controlled only through the column gating signals, when the writing data needs to be shielded, the writing of the data is prevented, a second initialization module for charging and balancing between the input and output line pairs can be omitted, the power consumption of the circuit is reduced, and the performance of the random access memory is further improved.

Referring to fig. 10, fig. 10 is a schematic diagram of a configuration of a second embodiment of the column selection circuit in fig. 1, where the column selection circuit 140 includes a column selection module 141, a column selection signal generating circuit 142, and a judging circuit 143, and the column selection signal generating circuit 142 is connected to the judging circuit 143.

Wherein, the judging circuit 143 determines whether the write data corresponding to the current write operation is mask data based on the mask signal; the column select signal generation circuit 142 outputs the first column select signal or the second column select signal based on the determination result of the determination circuit 143.

It will be appreciated that the mask signal is used to indicate whether the write data needs to be masked, e.g., the mask signal may be represented by a logic "1" and a logic "0", where if the mask signal is a logic "1" it indicates that the current write data needs to be masked and if the mask signal is a logic "0" it indicates that the current write data does not need to be masked.

Taking DM (data mask) as an example, DM is also called "partial write", and DM is mainly used to mask partial data in a write operation. Specifically, the DM signal and the data signal are sent simultaneously, and the receiving side judges the state of the DM signal at the rising and falling edges, and if the DM signal is at the high level, the currently written data needs to be masked. In addition, for burst writing, if there is data that is not wanted to be stored in it, the DM signal can still be used for masking.

Taking BC4 (Burst stop) as an example, BC4 is used to mask off the last 4 bits of 8 bits (one write or read command, only two cycles of data are collected).

Referring to fig. 11 in combination with fig. 5, fig. 11 is a schematic diagram of a configuration of a third embodiment of the column selection circuit in fig. 1, where the column selection circuit 140 includes a column selection module 141, a column selection signal generation circuit 142, and a determination circuit 143, and the column selection signal generation circuit 142 is connected to the determination circuit 143.

Wherein the column select signal generation circuit 142 includes a first column select signal generation unit 142a and a second column select signal generation unit 142b, the first column select signal generation unit 142a generating a first column strobe signal based on a write command; the second column selection signal generation unit 142b is connected to the first column selection signal generation unit 142a and the judgment circuit 143, and outputs the first column selection signal or the second column selection signal based on the first column selection signal and the judgment result signal output by the judgment circuit; wherein the logic potentials of the first column strobe signal and the second column strobe signal are opposite.

Alternatively, the judging circuit 143 may include a plurality of input terminals for inputting a plurality of masking signals for indicating whether or not the current write data needs to be masked, such as the DM signal and the BC4 signal described above, respectively. The judging circuit 143 is specifically configured to judge whether the current write data needs to be masked according to the plurality of masking signals, for example, if any one of the plurality of masking signals input indicates that the current write data needs to be masked, the judging result signal output by the judging circuit 143 indicates that the current write data needs to be masked; when the plurality of mask signals input indicate that the current write data does not need to be masked, the determination result signal output from the determination circuit 143 indicates that the current write data does not need to be masked.

Referring to fig. 12, fig. 12 is a schematic circuit diagram corresponding to fig. 11, and the column selecting circuit 140 includes a column selecting module 141, a column selecting signal generating circuit 142, and a judging circuit 143, where the column selecting signal generating circuit 142 is connected to the judging circuit 143.

The judging circuit 143 specifically includes a NOR gate, a first input terminal of which receives the first mask signal, a second input terminal of which receives the second mask signal, and an output terminal of which is used for outputting a judging result signal. The second column strobe signal generating unit 142b specifically includes an AND logic gate "AND", a first input terminal thereof receives the determination result signal, a second input terminal thereof receives the first column strobe signal, AND an output terminal thereof is used for outputting the first column strobe signal or the second column strobe signal.

In one embodiment, the first mask signal is a DM signal and the second mask signal is a BC4 signal, see the following table:

First column selection communication	DM	BC4	YS
				“1”	“1”	“0”	“0”
“1”	“0”	“1”	“0”
				“1”	“1”	“1”	“0”
“1”	“0”	“0”	“1”

As can be seen from the analysis of fig. 12 and the table above, when either one of the DM signal and the BC4 signal is at the logic high level "1", it indicates that the current input data needs to be subjected to the mask write operation, the corresponding column selection signal YS is "0", that is, the second column selection signal, and the switch T8 and the switch T9 in the column selection module 141 are turned off, so that the data on the input/output line pair IO/io# cannot rewrite the voltage on the bit line pair BL/bl#; when both the DM signal and the BC4 signal are at the logic low potential "0", it indicates that the current input data does not need to perform the mask write operation, and the corresponding column selection signal YS is "1", that is, the first column selection signal, and the switch T8 and the switch T9 in the column selection module 141 are turned on, so that the data on the input/output line pair IO/io# rewrites the voltage on the bit line pair BL/bl# to complete the current data write operation.

Referring to fig. 13, fig. 13 is a schematic structural diagram of a random access memory 200 according to the present application, and the random access memory 200 includes the memory array 100 described in the above embodiments.

Optionally, the random access memory 200 may further include a controller coupled to the memory array 100 for generating control signals to control the operation of the memory array 100. The control signal may be WL signal, EQ1 signal, EQ2 signal, YS signal, etc. in the above embodiment, and it is understood that the column selection signal generating circuit 142 in the above embodiment may be integrated in the controller.

Optionally, the random access memory 200 in this embodiment is a DRAM (Dynamic Random Access Memory ). DRAM is a semiconductor memory and the main principle of operation is to use how much charge is stored in a capacitor to represent whether a binary bit (bit) is "1" or "0". Alternatively, the random access memory 200 in the present embodiment may be an SRAM (Static Random Access Memory ).

By combining the beneficial effects of the embodiments, the random access memory in the embodiment can control the input writing only by the column strobe signal, and prevent the writing of data when the writing of data needs to be shielded, and can omit a second initialization module for charging and balancing between the input and output line pairs, thereby reducing the power consumption of the circuit and further improving the performance of the random access memory.

The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes according to the present application and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the scope of the present application.

Claims

1. A random access memory, comprising:

the memory array comprises a plurality of word lines, a plurality of bit lines and a plurality of memory cells, wherein each memory cell is respectively connected with one word line and a pair of complementary bit lines;

complementary input-output line pairs;

a column selection circuit including a plurality of column strobe modules, wherein each column strobe module is respectively connected with a pair of complementary bit lines to determine whether a current complementary bit line pair is strobed with the complementary input/output line pair based on a corresponding column strobe signal;

The column selection signal comprises a first column selection signal and a second column selection signal, wherein the first column selection signal is a column selection signal for controlling the corresponding column selection module to be conducted, and the second column selection signal is a column selection signal for controlling the corresponding column selection module to be cut off;

When the write data corresponding to the current write operation executed by the random access memory is non-mask data, the column gating signal received by the column gating module corresponding to the current write operation is the first column gating signal, and when the write data corresponding to the current write operation executed by the random access memory is mask data, the column gating signal received by the column gating module corresponding to the current write operation is the second column gating signal.

2. The random access memory of claim 1, wherein the column select circuit comprises:

A judging circuit for determining whether the write data corresponding to the current write operation is mask data based on a mask signal;

And a column selection signal generation circuit that outputs the first column selection signal or the second column selection signal based on a determination result of the determination circuit.

3. The random access memory of claim 2, wherein the mask signal includes a first mask signal and a second mask signal, and the determination circuit determines whether the write data corresponding to the current write operation is mask data based on the first mask signal and the second mask signal.

4. The random access memory of claim 2, wherein the column select communication generation circuit comprises:

A first column strobe signal generation unit that generates the first column strobe signal based on a write command;

And a second column strobe signal generating unit connected to the first column strobe signal generating unit and the judging circuit, and outputting the first column strobe signal or the second column strobe signal based on the first column strobe signal and the judging result signal output by the judging circuit.

5. A random access memory according to claim 3, wherein the determination circuit comprises:

And the first input end of the NOR logic gate receives the first shielding signal, the second input end of the NOR logic gate receives the second shielding signal, and the output end of the NOR logic gate is used for outputting the judging result signal.

6. The random access memory according to claim 4, wherein the second column selection signal generation unit includes:

and the first input end of the logic gate receives the judging result signal, the second input end of the logic gate receives the first column strobe signal, and the output end of the logic gate is used for outputting the first column strobe signal or the second column strobe signal.

7. A random access memory according to claim 3, wherein,

The first shielding signal is a DM signal, and the judging circuit determines whether the write data corresponding to the current write operation is shielding data according to the logic potential of the DM signal; and/or

The second shielding signal is a BC4 signal, and the judging circuit determines whether the write data corresponding to the current write operation is shielding data according to the logic potential of the BC4 signal.

8. A random access memory according to claim 1, further comprising:

and the sensitive amplifying module is coupled with the complementary input-output line pair to perform signal amplifying operation on the corresponding complementary input-output line pair.

9. The random access memory of claim 8, wherein the sense amplifier module comprises:

The first inversion unit is coupled between a corresponding target input output line and a complementary input output line, and pulls the voltage of the complementary input output line on the complementary input output line to a strong potential of a first logic, which is opposite to the potential represented by the written data, based on the written data on the target input output line during a write operation;

And a second inverting unit coupled between the complementary input output line and the target input output line, wherein the second inverting unit pulls the target input output line voltage on the target input output line to a strong potential of a second logic that is the same as the potential logic characterized by the write data in response to the complementary input output line voltage on the complementary input output line being pulled to the strong potential of the first logic.

10. A random access memory according to claim 9, wherein,

The first inversion unit includes:

a first switch T10 having a first path terminal coupled to the complementary input/output line and a second path terminal connected to a logic high level sense voltage amplification line (SAP);

a second switch T11 having a first path terminal connected to the complementary input/output line and a second path terminal connected to the logic low level sense voltage amplification line (SAN);

the second inversion unit includes:

a third switch T12 having a first path terminal coupled to the target input/output line and a second path terminal connected to the logic high level sense voltage amplification line (SAP);

a fourth switch T13, a first path end of which is connected to the target input/output line, and a second path end of which is connected to the logic low level sense voltage amplification line (SAN);

The control ends of the first switch and the second switch receive write voltage signals corresponding to write operation, respond to the write voltage signals, conduct the first switch or the second switch, and pull the complementary input output line voltage on the complementary input output line to the strong potential of first logic by utilizing the logic high-level sensitive voltage amplification line (SAP) or the logic low-level sensitive voltage amplification line SAN; in response to the complementary input-output line voltage being pulled to the strong potential of the first logic, the fourth switch or the third switch is turned on, and the target input-output line voltage on the target input-output line is pulled to the strong potential of the second logic using the logic low level sense voltage amplification line SAN or the logic high level sense voltage amplification line SAP.