CN116524969A - Random access memory and sensitive amplifying and driving circuit thereof - Google Patents

Abstract

The application discloses random access memory and sense amplifying and driving circuit thereof, this sense amplifying and driving circuit includes sense amplifying module and sense voltage providing module, wherein, sense voltage providing module connects the sense voltage line, in order to provide the sense amplifying voltage, wherein, the sense amplifying voltage includes preset sense amplifying voltage and overvoltage sense amplifying voltage, at the beginning of sense amplifying stage, the sense voltage providing module selects to drive the sense voltage line with overvoltage sense amplifying voltage, in order to make the voltage on the sense voltage line reach target voltage fast, and the sense voltage providing module then selects to drive the sense voltage line with preset sense amplifying voltage, in order to make the sense amplifying module work normally. By the mode, the read/write efficiency of the random access memory can be improved.

Description

Random access memory and sensitive amplifying and driving circuit thereof

Technical Field

The present disclosure relates to the field of memory technologies, and in particular, to a random access memory and a sense amplifying and driving circuit thereof.

Background

The memory array of the memory includes a plurality of Word Lines (WL), a plurality of Bit Lines (BL), and a plurality of memory cells, each of which is connected to one of the word lines WL and one of the bit lines BL, respectively.

After the word line WL is turned on, the data in the memory cell can be read/written, the potential of the bit line BL is shifted along with the potential of the charge stored in the memory cell, and a sense amplifier module is needed to amplify the shift. The voltage rising or dropping process of the voltage on the sensitive voltage line (SAP/SAN) needs to last for an overdrive time t, and the length of the time t affects the read/write performance of the memory.

Disclosure of Invention

In order to solve the above problems, the present application provides a random access memory and a sense amplifying and driving circuit thereof, which can improve the read/write efficiency of the random access memory.

In order to solve the technical problems, one technical scheme adopted by the application is as follows: there is provided a sense amplifying and driving circuit of a random access memory, the sense amplifying and driving circuit including: a sense amplifying module connected between the target bit line and the complementary bit line and connected to a sense voltage line to receive the sense amplified voltage, wherein the target bit line reads a logic level stored in a corresponding turned-on memory cell during an access phase; in the sense amplifying stage, the sense amplifying module pulls the target bit line voltage on the target bit line, the logic level of which is read, to a sense amplifying voltage; the sensitive voltage supply module is connected with the sensitive voltage line to supply sensitive amplified voltage, and at the beginning of the sensitive amplifying stage, the sensitive voltage supply module selects to drive the sensitive voltage line by the overvoltage sensitive amplified voltage so that the voltage on the sensitive voltage line reaches the target voltage quickly, and then selects to drive the sensitive voltage line by the preset sensitive amplified voltage so that the sensitive amplifying module works normally.

The sensitive amplifying voltage comprises a strong logic high-level sensitive amplifying voltage and a strong logic low-level sensitive amplifying voltage; the sensitive voltage lines comprise a strong logic high-level sensitive voltage line and a strong logic low-level sensitive voltage line, wherein the strong logic high-level sensitive voltage line is used for transmitting a strong logic high-level sensitive amplified voltage, and the strong logic low-level sensitive voltage line is used for transmitting a strong logic low-level sensitive amplified voltage; when the storage logic level is a logic high level, in a sense amplification stage, the sense amplification module pulls the target bit line voltage on the target bit line, from which the storage logic level is read, to a strong logic high level sense amplification voltage, and pulls the complementary bit line voltage on the complementary bit line to a strong logic low level sense amplification voltage; when the storage logic level is at a logic low level, in the sense amplification stage, the sense amplification module pulls the target bit line voltage on the target bit line, from which the storage logic level was read, to a strong logic low level sense amplification voltage and pulls the complementary bit line voltage on the complementary bit line to a strong logic high level sense amplification voltage.

Wherein the sensitive voltage lines include a strong logic high level sensitive voltage line and a strong logic low level sensitive voltage line; the sensitive voltage providing module includes a first sensitive voltage providing module connected to a strong logic high-level sensitive voltage line, wherein the first sensitive voltage providing module includes: a first comparator having a first input terminal receiving a first target voltage and a second input terminal receiving a first feedback voltage, the first comparator generating a corresponding comparison result based on the first target voltage and the first feedback voltage, wherein the first feedback voltage is equal to a voltage on a strong logic high-level sensitive voltage line; a first voltage output circuit receiving a preset sense amplification voltage of a strong logic high level and an overvoltage sense amplification voltage of a strong logic high level and connecting the strong logic high level sense voltage lines to selectively output the preset sense amplification voltage of the strong logic high level or the overvoltage sense amplification voltage of the strong logic high level based on a comparison result to drive the strong logic high level sense voltage lines; when the first feedback voltage is smaller than the first target voltage, the first voltage output circuit selectively outputs an overvoltage sensitive amplifying voltage with a strong logic high level so as to drive the voltage on the sensitive voltage line with the strong logic high level to be quickly pulled up; when the first feedback voltage is not smaller than the first target voltage, the first voltage output circuit selectively outputs a preset sensitive amplifying voltage with a strong logic high level so as to drive the voltage on the sensitive voltage line with the strong logic high level to be stabilized at the preset sensitive amplifying voltage with the strong logic high level, and normal operation is carried out, wherein the overvoltage sensitive amplifying voltage is larger than the preset sensitive amplifying voltage.

Wherein the first sensitive voltage supply module further comprises: and the analog sensitive amplifying module is connected with the second input end of the first comparator, wherein the analog sensitive amplifying module simulates the working state of the sensitive amplifying module so as to provide a first feedback voltage for simulating the voltage on the high-logic high-level sensitive voltage line for the first comparator, and the analog sensitive amplifying module and the sensitive amplifying module are electrified at the same time.

The first target voltage is larger than or equal to a preset sensitive amplifying voltage, and the overvoltage sensitive amplifying voltage is larger than the first target voltage.

Wherein the sensitive voltage lines include a strong logic high level sensitive voltage line and a strong logic low level sensitive voltage line; the sensitive voltage providing module includes a second sensitive voltage providing module connected to a strong logic low level sensitive voltage line, wherein the second sensitive voltage providing module includes: a second comparator having a first input terminal receiving a second target voltage and a second input terminal receiving a second feedback voltage, the second comparator generating a corresponding comparison result based on the second target voltage and the second feedback voltage, wherein the second feedback voltage is equal to the voltage on the strong logic low-level sensitive voltage line; a second voltage output circuit receiving the preset sense amplification voltage of the strong logic low level and the overvoltage sense amplification voltage of the strong logic low level and connecting the strong logic low level sense voltage line to selectively output the preset sense amplification voltage of the strong logic low level or the overvoltage sense amplification voltage of the strong logic low level based on the comparison result; when the second feedback voltage is larger than the second target voltage, the second voltage output circuit selectively outputs the overvoltage sensitive amplifying voltage with the strong logic low level so as to drive the voltage on the sensitive voltage line with the strong logic low level to be pulled down quickly; when the second feedback voltage is not greater than the second target voltage, the second voltage output circuit selectively outputs a preset sensitive amplifying voltage with a strong logic low level so as to drive the voltage on the sensitive voltage line with a strong logic high level to be stabilized at the preset sensitive amplifying voltage with the strong logic low level, and normal operation is performed, wherein the overvoltage sensitive amplifying voltage is lower than the preset sensitive amplifying voltage.

Wherein the second sensitive voltage supply module further comprises: and the analog sensitive amplifying module is connected with the second input end of the second comparator, wherein the analog sensitive amplifying module simulates the working state of the sensitive amplifying module so as to provide a second feedback voltage of the voltage on the analog strong logic low-level sensitive voltage line for the second comparator, and the analog sensitive amplifying module and the sensitive amplifying module are powered on simultaneously.

The second target voltage is smaller than or equal to a preset sensitive amplifying voltage, and the overvoltage sensitive amplifying voltage is smaller than the second target voltage.

Wherein, the sense amplifier module includes: a first inversion unit connected between the target bit line and the complementary bit line, wherein when the memory cell connected to the target bit line is turned on, a target bit line voltage on the target bit line is shifted from an initialization potential according to a logic level stored in the memory cell, and the first inversion unit inverts the complementary bit line voltage on the complementary bit line to a strong potential of the first logic based on the shifted target bit line voltage; and a second inversion unit connected between the complementary bit line and the target bit line, wherein when the complementary bit line voltage on the complementary bit line is pulled to the strong potential of the first logic, the second inversion unit inverts based on the complementary bit line voltage to pull the target bit line voltage on the target bit line to the strong potential of the second logic, and the second logic is opposite to the first logic.

In order to solve the technical problems, another technical scheme adopted by the application is as follows: there is provided a random access memory comprising a sense amplifying and driving circuit as described above.

The sense amplifying and driving circuit of the random access memory has the advantages that the sense amplifying voltage is provided by the sense voltage providing module, the sense voltage providing module selectively drives the sense voltage line by the overvoltage sense amplifying voltage so that the voltage on the sense voltage line can reach the target voltage quickly, and the sense voltage providing module subsequently selectively drives the sense voltage line by the preset sense amplifying voltage so that the sense amplifying module works normally. On the one hand, the voltage on the sensitive amplifying line (SAP/SAN) in the sensitive amplifying module can be quickly pulled up/down to be higher/lower than the target voltage through a higher/lower voltage in the early stage of the sense (sensitive amplifying) stage, and then the normal working voltage is recovered to be required, so that the duration of the rising/falling process of the voltage on the SAP/SAN in the sense stage is shortened, and the reading/writing efficiency of the random access memory is further improved; on the other hand, by setting the target voltage such that the voltage on the SAP/SAN is precisely controllable, it does not affect the preset sense-amp voltage, reducing the difficulty in designing the preset sense-amp voltage to subsequently drive the SAP/SAN. The voltage on the SAP is not too high or too low, so that the difficulty in writing operation and damage to a memory cell caused by the too high voltage of the SAP are avoided, and the time (tRCD) of reading operation caused by the too low voltage of the SAP is also avoided to be prolonged, thereby further improving the performance of the random access memory.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:

FIG. 1 is a schematic diagram of a memory array of a random access memory provided herein;

FIG. 2 is a schematic diagram illustrating an embodiment of the first initialization module in FIG. 1;

FIG. 3 is a schematic diagram of an embodiment of the sense amplifier module of FIG. 1;

FIG. 4 is a schematic circuit diagram of an embodiment of the sense amplifier module of FIG. 3;

FIG. 5 is a schematic diagram of an embodiment of the column selection circuit of FIG. 1;

FIG. 6 is a schematic diagram of an embodiment of the I/O circuit of FIG. 1;

FIG. 7 is a schematic diagram of potential trend of an embodiment of the random access memory provided in the present application;

FIG. 8 is a schematic diagram of a sense amplifier and driver circuit provided herein;

FIG. 9 is a schematic diagram of an embodiment of a first voltage supply module according to the present application;

FIG. 10 is a schematic diagram of potential trend of another embodiment of the random access memory provided in the present application;

FIG. 11 is a schematic diagram of a second embodiment of a second voltage supply module according to the present disclosure;

FIG. 12 is a schematic diagram showing potential trend of a random access memory according to another embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of a random access memory provided in the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not limiting. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present application are shown in the drawings. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a memory array of a random access memory provided in the present application, where the memory array 100 includes a plurality of Word Lines (WL), a plurality of Bit Lines (BL), and a plurality of memory cells 110, and each memory cell 110 is connected to one WL and one BL.

In an embodiment in which the random access memory is a dynamic random access memory (Dynamic Random Access Memory, DRAM), each memory cell 110 includes an access switch and a storage capacitor. The storage capacitor represents logical "1" and "0" by the more and less of the charge stored therein, or the high and low of the voltage difference across the storage capacitor. The on and off of the access switch determines whether to permit or prohibit reading and writing of information stored in the storage capacitor.

Specifically, the word line WL determines on or off of the access switch, the bit line BL is the only channel for external access to the storage capacitor, and after the access switch is turned on, external access can perform read or write operations on the storage capacitor through the bit line BL.

In one embodiment, the Common terminal (Common) of the storage capacitors is connected to Vref, and in one embodiment, vref=vcc/2.

When the information stored in the storage capacitor is "1", the voltage at the other end of the storage capacitor is Vcc, and at this time, the stored charge is:

Q＝+Vref*C

when the information stored in the storage capacitor is "0", the voltage at the other end of the storage capacitor is 0, and at this time, the stored charge is:

Q＝-Vref*C

further, the memory array 100 further includes a first initialization module 120, a Sense Amplifier module 130 (SA), a column selection circuit 140, and an input-output circuit 150.

Note that two adjacent bit lines BL can be referred to as a plurality of pairs of complementary bit lines (target bit line BL and complementary bit line bl#). The first initialization module 120 is connected to a pair of complementary bit lines (BL/bl#) for charging the target bit line BL and the complementary bit line bl#) to an initialization potential in a precharge phase (precharge). The sense amplifier module 130 is connected to a pair of complementary bit line pairs (BL/bl#) for amplifying the logic potential on the target bit line BL to a corresponding strong potential when the memory cell 110 connected to the target bit line BL is turned on by the Word Line (WL). The input/output circuit 150 includes a pair of complementary input/output lines (IO/io#), and the column selection circuit 140 includes a plurality of column strobe modules 141 and a column select signal generation circuit 142, where each column strobe module 141 is respectively connected to a pair of complementary bit line pairs to determine whether the current complementary bit line pair is strobed with the connected complementary input/output line pair (IO/io#) based on the corresponding column select signal generated by the column select signal generation circuit 142.

Referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of the first initialization module in fig. 1, where the first initialization module 120 includes a switch T1, a switch T2, and a switch T3, control terminals of the switch T1, the switch T2, and the switch T3 receive a first precharge control signal EQ1, a first pass terminal of the switch T1 is connected to a target bit line BL, a first pass terminal of the switch T2 is connected to a complementary bit line bl#, second pass terminals of the switch T1 and the switch T2 are connected to an initialization potential Vref (vref=1/2 Vcc in an embodiment), a first pass terminal of the switch T3 is connected to the target bit line BL, and a second pass terminal of the switch T3 is connected to the complementary bit line bl#.

In the precharge phase (precharge), the first precharge control signal EQ1 controls the switches T1 and T2 to be turned on, and charges the target bit line BL and the complementary bit line bl# with the initialization potential Vref so that the potentials of the target bit line BL and the complementary bit line bl# are the initialization potentials. Further, the first precharge control signal EQ1 controls the switch T3 to be turned on so that the potentials of the target bit line BL and the complementary bit line bl# remain identical.

Alternatively, the above-mentioned switches T1, T2 and T3 may be nMOS transistors. Preferably, if the first precharge control signal EQ1 is active low, the above-described switches T1, T2 and T3 may be pMOS transistors.

Referring to fig. 3, fig. 3 is a schematic structural diagram of an embodiment of the sense amplifying module in fig. 1, and the sense amplifying module 130 includes a first inverting unit 131 and a second inverting unit 132.

The first inversion unit 131 is connected between the target bit line BL and the complementary bit line BL#, wherein the target bit line voltage V on the target bit line BL is generated when the memory cell 110 connected to the target bit line BL is turned on _BL The first inverting unit 131 is shifted from the initialization potential Vref according to the logic level stored in the memory cell 110, and the shifted target bit line voltage V _BL Flip, the complementary bit line voltage V on the complementary bit line BL# _BL# Pulled to a strong potential of the first logic.

The second inversion unit 132 is connected between the complementary bit line BL# and the target bit line BL, wherein, inComplementary bit line voltage V of BL# on complementary bit line _BL# When the first logic is pulled to a strong potential, the second inverting unit 132 is based on the complementary bit line voltage V _BL# Flip, the target bit line voltage V on the target bit line BL _BL To a strong potential of a second logic opposite to the first logic.

Referring to fig. 3 and fig. 4, fig. 4 is a circuit schematic of an embodiment of the sense amplifying module in fig. 3, wherein the first inverting unit 131 includes a switch T4 and a switch T5, and the second inverting unit 132 includes a switch T6 and a switch T7.

Alternatively, in the present embodiment, the switches T4 and T6 are nMOS transistors, and the switches T5 and T7 are pMOS transistors.

Referring to fig. 5, fig. 5 is a schematic diagram of an embodiment of the column selection circuit in fig. 1, where the column selection circuit 140 includes a column selection signal generating circuit 142 and a plurality of column gating modules 141, and each column gating module 141 is respectively connected to a pair of complementary bit line pairs (BL/bl#) to determine whether the current complementary bit line pair (BL/bl#) is gated with the connected complementary input/output line pair (IO/io#) based on a corresponding column selection signal YS generated by the column selection signal generating circuit 142.

The column selection module 141 includes a switch T8 and a switch T9, and control ends of the switch T8 and the switch T9 are connected to a column selection signal generating circuit 142, for receiving a corresponding column selection signal YS; the first path end of the switch T8 is connected with the target bit line BL, the second path end is connected with the target input/output line IO, the first path end of the switch T9 is connected with the complementary bit line BL#, and the second path end is connected with the complementary input/output line IO#.

Specifically, when the corresponding column selection communication signal YS control switch T8 and switch T9 generated by the column selection communication signal generating circuit 142 are turned on, the target bit line BL is connected to the target input/output line IO, and the complementary bit line bl# is connected to the complementary input/output line io#, so as to realize gating of the complementary bit line pair (BL/bl#) and the complementary input/output line pair (IO/io#). In a Write operation (Write), charging/discharging the complementary bit line pair (BL/BL#) through the complementary input-output line pair (IO/IO#) to rewrite a signal on the complementary input-output line pair (IO/IO#) to a voltage on the complementary bit line pair (BL/BL#); in a Read operation, a signal on the complementary bit line pair (BL/BL#) is output to the complementary input/output line pair (IO/IO#).

Alternatively, the above-described switches T8 and T9 may be nMOS transistors.

Referring to fig. 6, fig. 6 is a schematic diagram of an embodiment of the input/output circuit in fig. 1, where the input/output circuit 150 includes a second initialization module 151.

The second initialization module 151 includes a switch T10, a switch T11, and a switch T12, wherein control ends of the switch T10, the switch T11, and the switch T12 receive a second precharge control signal EQ2, a first path end of the switch T10 is connected to the target input output line IO, a first path end of the switch T11 is connected to the complementary input output line io#, a second path end of the switch T10 and the switch T11 is connected to the reference potential Vcc, a first path end of the switch T12 is connected to the target input output line IO, and a second path end of the switch T12 is connected to the complementary input output line io#.

In the initialization stage of the input-output circuit 150, the second precharge control signal EQ2 controls the switch T10 and the switch T11 to be turned on, and charges the target input-output line IO and the complementary input-output line io# with the reference voltage Vcc, so that the potentials of the target input-output line IO and the complementary input-output line io# are the reference potential Vcc. Further, the second precharge control signal EQ2 controls the switch T12 to be turned on so that the potentials of the target input output line IO and the complementary input output line io# remain uniform. After the sense amplifier module 130 amplifies the logic level stored in the memory cell 110 read out on the complementary bit line pair (BL/bl#) and pulls it to either strong "0" or strong "1", the input and output are connected to each other to complete the read and write operation.

Alternatively, the above-described switch T10, switch T11, and switch T12 may be nMOS transistors. Preferably, if the second precharge control signal EQ2 is active low, the above-described switches T10, T11 and T12 may be pMOS transistors.

Referring to fig. 7 in combination with fig. 1 to 6, fig. 7 is a schematic potential trend diagram of an embodiment of the dynamic random access memory provided in the present application, and the following describes the working process of the dynamic random access memory in the embodiment in a Read operation (Read) process, which includes a precharge phase, an access phase, a sense amplification phase, and a restore phase.

precharge phase:

at this stage, the voltages on the target bit line BL and the complementary bit line bl# are stabilized on Vref by first turning on the switches T1, T2, T3 by the control signal EQ1, assuming vref=vcc/2. And then proceeds to the next stage.

access phase:

through the precharge phase, the voltages on the target bit line BL and the complementary bit line bl# have stabilized at Vref, at which point the access switch in the memory cell 110 is turned on by controlling the word line WL (applying a voltage to the word line WL by an Active command). Positive charge stored in the storage capacitor in the memory cell 110 (e.g., vcc/2 for the common single-ended voltage of the capacitor and Vcc for the other end if the memory cell 110 stores a "1") flows to the target bit line BL, which in turn shifts the voltage of the target bit line BL upward to vref+. If the memory cell 110 stores a "0," the voltage of the target bit line BL is shifted downward to Vref-. And then proceeds to the next stage.

sense phase:

assume that the storage unit 110 stores "1": since the voltage of the target bit line BL is shifted up to Vref+ during the access phase, SAN is set to a strong potential of logic "0" and SAP is set to a strong potential of logic "1". Since the "1" stored in the memory cell 110 pulls up the voltage of the target bit line BL to Vref+, and the voltage of the complementary bit line BL# is still Vref, the switch T4 in FIG. 4 is more conductive than the switch T6, and the voltage on the complementary bit line BL# is pulled to a strong potential of logic "0" by SAN due to the conduction of T4. Since the gate of T7 is turned on at this time with a strong "0", the voltage on the target bit line BL is also pulled to a strong potential of logic "1" by SAP faster due to the conduction of T7. Then, the switch T4 and the switch T7 are turned on, and the switch T5 and the switch T6 are turned off. Finally, the voltages on the target Bit line BL and the complementary Bit line BL# both enter a steady state, and the voltage on the target Bit line BL correctly presents the information Bit ("1") stored by the storage capacitance in the memory cell 110.

Assume that the storage unit 110 stores "0": in the access phase, the voltage on the target bit line BL is shifted downward to Vref-, and since the voltage on the complementary bit line BL# is still Vref, the switch T5 in FIG. 4 is more conductive than the switch T7, and the voltage on the complementary bit line BL# is pulled to the strong potential of logic "1" by SAP due to the conduction of T5. Since the gate of T6 is now turned on with a strong "0", the voltage on the target bit line BL will also be pulled to a strong potential of logic "0" by SAN faster due to the turn-on of T6. Then the switches T5 and T6 enter the on state, and the switches T4 and T7 enter the off state. Finally, the voltages on the target Bit line BL and the complementary Bit line BL# both enter a steady state, and the voltage on the target Bit line BL correctly presents the information Bit ("0") stored by the storage capacitance in the memory cell 110.

Restore stage:

after the sense phase operation is completed, the target bit line BL is at a stable strong potential of logic "1" or logic "0", and the target bit line BL charges or discharges the storage capacitor in the memory cell 110. After a certain time, the charge of the storage capacitor can be restored to the state before the read operation.

Finally, as shown in fig. 5, the column selection signal generating circuit controls the YS signal to make the switch T8 and the switch T9 enter a conducting state, and outputs a strong "1" or a strong "0" signal on the target bit line BL to the IO line, so that the outside can read specific information. It should be noted that the restore phase is performed automatically during the word line WL on period, so that it is also possible for the read operation to perform the restore operation after the YS signal is turned on.

The above procedure describes a complete read operation, the pre-flow of the write operation is the same as the read operation, and precharge, access, sense and restore phase operations are performed. The difference is that the restore phase includes a write phase and then a write recovery operation is performed as follows:

as shown in fig. 5, the column selection signal YS is controlled by the column selection signal generating circuit 142 to put the switch T8 and the switch T9 into the on state, and the signal of the input/output line IO rewrites the target bit line BL. At this time, if "0" is written, the target bit line BL is pulled to a logic "0" level, and the complementary bit line BL# is pulled to a logic "1" level; if a "1" is written, the target bit line BL is pulled to a logic "1" level, and the complementary bit line BL# is pulled to a logic "0" level.

And then doing write recovery: after a certain time (i.e., tWR), when the charge of the storage capacitor in the memory cell 110 is discharged to the "0" state or charged to the "1" state by the voltage on the target bit line BL, the operation of writing "0" or "1" is completed by controlling the word line WL to turn off the switch in the memory cell 110.

In an embodiment, in conjunction with fig. 3, 4 and 7, in the sense phase, the voltage value on SAP is pulled high under a high level of driving, this time being the overdrive time t, which is independent of the voltage value on SAP, so that it may happen that the voltage value on SAP is not raised to the desired strong "1" voltage value for too short a time t, and the voltage value on SAP is too high for too long a time t.

The voltage value on SAP is higher than the "1" potential, and for writing, writing "1" is difficult compared with latching higher than "1" potential in the sense amplifier module SA. Meanwhile, the SAP value of the high potential affects the voltage of the bit line BL, and thus may affect the voltage of the storage capacitor, which may pose a performance threat to the storage capacitor.

The voltage value on SAP is lower than "1" potential, which can prolong the time of tRCD (interval time between two adjacent read/write operations) for read operation, reduce the read/write efficiency, and affect the circuit performance.

Referring to fig. 1 and 8, fig. 8 is a schematic diagram of a sense amplifying and driving circuit provided in the present application, which includes a sense voltage providing module 160 and a sense amplifying module 130 in the above embodiment, the sense voltage providing module 160 is connected to a sense voltage line (SAP or SAN) to provide a sense amplifying voltage, wherein the sense amplifying voltage includes a preset sense amplifying voltage and an over-voltage sense amplifying voltage, the sense voltage providing module 160 selects to drive the sense voltage line (SAP or SAN) with the over-voltage sense amplifying voltage at the beginning of the sense amplifying stage so that the voltage on the sense voltage line (SAP or SAN) reaches a target voltage rapidly, and the sense voltage providing module 160 then selects to drive the sense voltage line (SAP or SAN) with the preset sense amplifying voltage so that the sense amplifying module 130 operates normally.

In one embodiment, the sense amp voltages include a strong logic high level (strong "1") sense amp voltage and a strong logic low level (strong "0") sense amp voltage; the sense voltage lines include a strong logic high-level sense voltage line SAP for transmitting a strong logic high-level (strong "1") sense amplification voltage and a strong logic low-level sense voltage line SAN for transmitting a strong logic low-level (strong "0") sense amplification voltage.

When the storage logic level is a logic high level ("1"), the sense amplification module 130 pulls the target bit line voltage on the target bit line BL, which has read the storage logic level, to a strong logic high level (strong "1") sense amplification voltage and pulls the complementary bit line voltage on the complementary bit line bl# to a strong logic low level (strong "0") sense amplification voltage during a sense amplification phase (i.e., sense phase described in fig. 7).

When the storage logic level is a logic low level ("0"), the sense amplification module 130 pulls the target bit line voltage on the target bit line BL, which has read the storage logic level, to a strong logic low level (strong "0") sense amplification voltage and pulls the complementary bit line voltage on the complementary bit line bl# to a strong logic high level (strong "1") sense amplification voltage in the sense amplification stage.

In the following, taking the strong logic high-level sensitive voltage line SAP as an example, as shown in fig. 9, fig. 9 is a schematic diagram of an embodiment of the first sensitive voltage providing module provided in the present application, and the first sensitive voltage providing module 160a includes a first comparator 161a and a first voltage output circuit 163a. In one embodiment, the first sensitive voltage providing module 160a further includes a first logic gate 162a. The first voltage output circuit 163a receives as inputs a preset sense amplified voltage Vary-H of a strong logic high level (strong "1") and an overvoltage sense amplified voltage Vod-H of a strong logic high level (strong "1").

Wherein the first input terminal of the first comparator 161a receives the first Target voltage Target V1, the second input terminal receives the first feedback voltage Copy SAP, and the first comparator 161a generates a corresponding comparison result based on the first Target voltage Target V1 and the first feedback voltage Copy SAP, wherein the first feedback voltage Copy SAP is equal to the voltage on the strong logic high-level sensitive voltage line SAP, and in one embodiment, the first feedback voltage Copy SAP is provided by an analog sense amplifier module (Copy SA) 164a, and the analog sense amplifier module (Copy SA) 164a is used for simulating the operation of the sense amplifier module 130 inside the memory array 100, so that the first feedback voltage Copy SAP on the strong logic high-level sensitive voltage line SAP of the Copy SA 164a is equal to the voltage on the strong logic high-level sensitive voltage line SAP of the sense amplifier module 130 inside the memory array 100, and the operation of the Copy SA 164a will be described later; the first voltage output circuit 163a receives the preset sense amplification voltage Vary-H of the strong logic high level (strong "1") and the overvoltage sense amplification voltage Vod-H of the strong logic high level (strong "1"), and connects the strong logic high level sense voltage line SAP to selectively output the preset sense amplification voltage Vary-H of the strong logic high level (strong "1") or the overvoltage sense amplification voltage Vod-H of the strong logic high level (strong "1") based on the comparison result. In an embodiment, the first logic gate 162a is connected between the output terminal of the first comparator 161a and the control terminal of the first voltage output circuit 163a, so as to generate a corresponding first control signal based on the comparison result of the first comparator 161a as a basis for selecting the preset sense amplifying voltage Vary-H or the over-voltage sense amplifying voltage Vod-H to drive the strong logic high-level sense voltage line SAP.

The first Target voltage Target V1 is greater than or equal to a preset sense amplifying voltage Vary-H of a strong logic high level (strong "1"), and an overvoltage sense amplifying voltage Vod-H of the strong logic high level (strong "1") is greater than the first Target voltage Target V1.

Specifically, when the first feedback voltage Copy SAP is smaller than the first Target voltage Target V1, the first voltage output circuit 163a selectively outputs the over-voltage sense amplified voltage Vod-H of the strong logic high level (strong "1") to quickly pull up the voltage on the strong logic high level sense voltage line SAP.

Specifically, when the first feedback voltage copy SAP is not less than the first Target voltage Target V1, the first voltage output circuit 163a selectively outputs the preset sense amplified voltage Vary-H of the strong logic high level (strong "1") to stabilize the voltage on the strong logic high level sense voltage line SAP at the preset sense amplified voltage Vary-H of the strong logic high level (strong "1") for normal operation.

Referring to fig. 10, fig. 10 is a schematic potential trend diagram of another embodiment of the random access memory provided in the present application, where a dotted line portion corresponding to SAP represents before improvement and a solid line portion corresponding to SAP represents after improvement.

When the copy SAP does not rise to the first Target voltage Target V1, the comparator output is kept at "0", the first voltage output circuit 163a selectively outputs the over-voltage sense amplification voltage Vod-H to drive the SAP line through the control of the first logic gate circuit 162a, the sense amplification module 130 is powered up by the over-voltage sense amplification voltage Vod-H, and when the copy SAP exceeds the first Target voltage Target V1, the comparator is turned over to "1", the first voltage output circuit 163a selectively outputs the preset sense amplification voltage Vary-H to drive the SAP line through the control of the first logic gate circuit 162a, and the voltage on the strong logic high level sense voltage line SAP falls back to Vary-H and does not rise/fall any more.

By the above manner, on one hand, the voltage on the SAP can be quickly pulled to be higher than the first Target voltage Target V1 by a stronger voltage Vod-H at the early stage of the sense stage, and then the preset sense amplifying voltage Vary-H required by the normal operation of the sense amplifying module 130 is restored, so that the time of the duration t (oversover) of the rising process of the voltage on the strong logic high-level sense voltage line SAP at the sense stage is shortened, and the read/write efficiency of the random access memory is further improved; on the other hand, by setting the first Target voltage Target V1, the voltage on the strong logic high-level sensitive voltage line SAP is precisely controllable, which does not affect the preset sensitive amplified voltage Vary-H, reducing the difficulty in designing the preset sensitive amplified voltage to subsequently drive SAP. The voltage on the SAP is not too high or too low, so that the difficulty in writing operation and damage to a memory cell caused by the too high voltage of the SAP are avoided, and the time (tRCD) of reading operation caused by the too low voltage of the SAP is also avoided to be prolonged, thereby further improving the performance of the random access memory.

In an alternative embodiment, an analog sense amplifier module (copy SA) may be further included and connected to the second input terminal of the first comparator 161a, where the analog sense amplifier module (copy SA) simulates an operation state of the sense amplifier module 130 to provide the first comparator 161a with the first feedback voltage copy SAP of the voltage on the SAP line of the analog sense amplifier module 130, that is, the first feedback voltage copy SAP is kept equal to the voltage on the SAP line of the sense amplifier module 130. In one embodiment, the analog sense amp module (copy SA) is powered up simultaneously with the sense amp module 130.

It will be appreciated that the analog sense amplifier module (copy SA) 164a is completely consistent with the internal circuit and external access timing of the original sense amplifier module 130, and the sense phase in the read/write operation is simultaneously when the sense amplifier module 130 is powered on, so that the voltage (copy SAP) on the SAP line of the analog sense amplifier module copy SA 164a is completely synchronous and consistent with the voltage (copy SAP) on the SAP line of the sense amplifier module 130, and thus the analog sense amplifier module copy SA 164a can use the voltage (copy SAP) on the SAP line thereof as the first feedback voltage to realize the simulation and monitoring of the voltage on the SPA line of the sense amplifier module 130. It should be noted that, the analog sense amplifier module copy SA 164a is an independent circuit outside the memory array 100, and generally, the circuits (including the circuit structure and the MOS transistor size) of the sense amplifier module 130 to which each target bit line pair (BL/bl#) in the same Bank of the memory array 100 is coupled are the same, so that only one analog sense amplifier module copy SA 164a needs to be set in each Bank, and the circuit area is not excessively increased; and since the analog sense amp module copy SA 164a is disposed outside the memory array 100, there is no need to separately draw the voltage on the SAP line from the memory array 100. Further, the sense amplifier module 130 of the target bit line pair (BL/bl#) of the read/write operation needs to be powered up, the SAP line is pulled high, the SAN line is set low, and the other sense amplifier modules 130 need not be powered up, so that only one sense voltage providing module 160a needs to be provided for each bank to drive the sense amplifier modules 130 of all the target bit line pairs (BL/bl#) in the bank, so as to further reduce the circuit area.

In the following, taking the strong logic low level sensitive voltage line SAN as an example, as shown in fig. 11, fig. 11 is a schematic diagram of an embodiment of the second sensitive voltage providing module provided in the present application, and the second sensitive voltage providing module 160b includes a second comparator 161b and a second voltage output circuit 163b. In one embodiment, the second sensitive voltage providing module 160b further includes a second logic gate 162b. The second voltage output circuit 163b receives as inputs a preset sense amplified voltage Vary-L of a strong logic low level (strong "0") and an overvoltage sense amplified voltage Vod-L of a strong logic low level (strong "0").

Wherein the first input terminal of the second comparator 161b receives the second Target voltage Target V2, the second input terminal receives the second feedback voltage Copy SAN, and the second comparator 161b generates a corresponding comparison result based on the second Target voltage Target V2 and the second feedback voltage Copy SAN, wherein the second feedback voltage Copy SAN is equal to the voltage on the strong logic low-level sensitive voltage line SAN, and in one embodiment, the second feedback voltage Copy SAN is provided by an analog sense amplifier module (Copy SA) 164b, and the analog sense amplifier module (Copy SA) 164b is used for simulating the operation of the sense amplifier module 130 inside the memory array 100, so that the first feedback voltage Copy SAN on the strong logic low-level sensitive voltage line SAN of the Copy SA 164b is equal to the voltage on the strong logic low-level sensitive voltage line SAN of the sense amplifier module 130 inside the memory array 100, and the operation of the Copy SA 164b will be described later; the second voltage output circuit 163b receives the preset sense amplification voltage Vary-L of the strong logic low level (strong "0") and the overvoltage sense amplification voltage Vod-L of the strong logic low level (strong "0"), and connects the strong logic low level sense voltage line SAN to selectively output the preset sense amplification voltage Vary-L of the strong logic low level (strong "0") or the overvoltage sense amplification voltage Vod-L of the strong logic low level (strong "0") based on the comparison result. In an embodiment, the second logic gate 162b is connected between the output terminal of the second comparator 161b and the control terminal of the second voltage output circuit 163b, so as to generate a corresponding second control signal based on the comparison result of the second comparator 161b, as a basis for selecting whether the preset sense amplifying voltage Vary-L or the over-voltage sense amplifying voltage Vod-L drives the strong logic low-level sense voltage line SAN.

The second Target voltage Target V2 is less than or equal to a preset sense amplifying voltage Vary-L of a strong logic low level (strong "0"), and the overvoltage sense amplifying voltage Vod-L of the strong logic low level (strong "0") is less than the second Target voltage Target V2.

Specifically, when the second feedback voltage copy SAN is greater than the second Target voltage Target V2, the second voltage output circuit 163b selectively outputs the over-voltage sense amplified voltage Vod-L of the strong logic low level (strong "0") to quickly pull down the voltage on the strong logic low level sense voltage line SAN.

Specifically, when the second feedback voltage copy SAN is not greater than the second Target voltage Target V2, the second voltage output circuit 163b selectively outputs the preset sense amplified voltage Vary-L of the strong logic low level (strong "0") to stabilize the voltage on the strong logic high level sense voltage line SAN at the preset sense amplified voltage Vary-L of the strong logic low level (strong "0") for normal operation.

With reference to fig. 12, fig. 12 is a schematic diagram of potential trend of still another embodiment of the random access memory provided in the present application, where a dashed line portion corresponding to SAN represents before improvement and a solid line portion corresponding to SAN represents after improvement.

When the copy SAN is not lowered to the second Target voltage Target V2, the comparator output is kept at "0", the second voltage output circuit 163b selectively outputs the over-voltage sense amplification voltage Vod-L to drive SAN lines under the control of the second logic gate circuit 162b, the sense amplification module 130 is powered down by the over-voltage sense amplification voltage Vod-L, and when the copy SAN is lower than the second Target voltage Target V2, the comparator is turned over to "1", the second voltage output circuit 163b selectively outputs the preset sense amplification voltage Vary-L to drive SAN lines under the control of the second logic gate circuit 162b, and the voltage on the strong logic low level sense voltage line SAN rises to Vary-L and is not raised/lowered any more.

By the above way, on one hand, the voltage on the SAN can be quickly pulled to be lower than the second Target voltage Target V2 by a stronger voltage Vod-L at the early stage of the sense stage, and then the preset sense amplifying voltage Vary-L required by the normal operation of the sense amplifying module 130 is restored, so that the duration of the voltage dropping process on the strong logic low level sense voltage line SAN at the sense stage is shortened, and the read/write efficiency of the random access memory is further improved; on the other hand, the voltage on the strong logic low-level sensitive voltage line SAN is made precisely controllable by setting the second Target voltage Target V2.

In an alternative embodiment, an analog sense amplifier module (copy SA) 164b may be further included and connected to the second input terminal of the second comparator 161b, where the analog sense amplifier module (copy SA) 164b simulates the operation state of the sense amplifier module 130 to provide the second comparator 161b with the second analog feedback voltage copy SAN of the voltage on the SAN line of the analog sense amplifier module 130, that is, the second feedback voltage copy SAN remains equal to the voltage on the SAN line of the sense amplifier module 130. It should be noted that, in an embodiment, the analog sense amplifier module (copy SA) 164b in fig. 11 and the analog sense amplifier module (copy SA) 164a in fig. 9 are the same module, i.e. the copy SA 164a may provide the first feedback voltage copy SAP of fig. 9 and the second feedback voltage copy SAN of fig. 11 at the same time. The specific operation of the analog sense amplifier module (copy SA) 164b is not described herein.

Referring to fig. 13, fig. 13 is a schematic structural diagram of a random access memory provided in the present application, and the random access memory 200 includes the memory array 100 described in the above embodiments.

Optionally, the random access memory 200 may further include a controller coupled to the memory array 100 for generating control signals to control the operation of the memory array 100. The control signal may be WL signal, EQ1 signal, YS signal, etc. in the above embodiment, and it is understood that the column selection signal generating circuit 142 in the above embodiment may be integrated in the controller.

Optionally, the random access memory 200 in the present embodiment is a DRAM (Dynamic Random Access Memory ). DRAM is a semiconductor memory and the main principle of operation is to use how much charge is stored in a capacitor to represent whether a binary bit (bit) is "1" or "0".

By combining the beneficial effects of the embodiments, on one hand, the voltage on the SAP/SAN can be quickly pulled up/down to be higher/lower than the target voltage through a higher/lower voltage in the early stage of the sense stage, and then the normal working voltage is recovered to be required, so that the duration of the rising/falling process of the voltage on the SAP/SAN in the sense stage is shortened, and the read/write efficiency of the random access memory is further improved; on the other hand, by setting the target voltage such that the voltage on the SAP/SAN is precisely controllable, it does not affect the preset sense-amp voltage, reducing the difficulty in designing the preset sense-amp voltage to subsequently drive the SAP/SAN. The voltage on the SAP is not too high or too low, so that the difficulty in writing operation and damage to a memory cell caused by the too high voltage of the SAP are avoided, and the time (tRCD) of reading operation caused by the too low voltage of the SAP is also avoided to be prolonged, thereby further improving the performance of the random access memory.

Embodiments of the present application are implemented in the form of software functional units and sold or used as a stand-alone product, which may be stored on a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution, in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the patent application, and all equivalent structures or equivalent processes according to the specification and drawings of the present application, or direct or indirect application in other related technical fields, are included in the scope of the patent protection of the present application.

Claims (10)

1. A sense amplifying and driving circuit of a random access memory, comprising:

a sense amplifying module connected between a target bit line and a complementary bit line and connected to a sense voltage line to receive a sense amplified voltage, wherein the target bit line reads a logic level stored in a corresponding turned-on memory cell during an access phase; in a sense amplifying stage, the sense amplifying module pulls a target bit line voltage on the target bit line, from which a logic level is read, to the sense amplifying voltage;

and the sensitive voltage supply module is connected with the sensitive voltage line to supply the sensitive amplifying voltage, and is used for selecting to drive the sensitive voltage line with the overvoltage sensitive amplifying voltage at the beginning of the sensitive amplifying stage so as to enable the voltage on the sensitive voltage line to quickly reach the target voltage, and then selecting to drive the sensitive voltage line with the preset sensitive amplifying voltage so as to enable the sensitive amplifying module to work normally.

2. The sense amplifier and driver circuit of claim 1, wherein,

the sensitive amplifying voltage comprises a strong logic high-level sensitive amplifying voltage and a strong logic low-level sensitive amplifying voltage; the sensitive voltage lines comprise strong logic high-level sensitive voltage lines and strong logic low-level sensitive voltage lines, wherein the strong logic high-level sensitive voltage lines are used for transmitting the strong logic high-level sensitive amplified voltages, and the strong logic low-level sensitive voltage lines are used for transmitting the strong logic low-level sensitive amplified voltages;

When the storage logic level is a logic high level, in a sense amplifying stage, the sense amplifying module pulls a target bit line voltage on the target bit line, from which the storage logic level is read, to the strong logic high level sense amplifying voltage and pulls a complementary bit line voltage on the complementary bit line to the strong logic low level sense amplifying voltage;

when the storage logic level is a logic low level, in a sense amplification stage, the sense amplification module pulls a target bit line voltage on the target bit line that has read the storage logic level to the strong logic low level sense amplification voltage and pulls a complementary bit line voltage on the complementary bit line to the strong logic high level sense amplification voltage.

3. The sense amplifying and driving circuit according to claim 1, wherein the sense voltage lines include a strong logic high level sense voltage line and a strong logic low level sense voltage line;

the sense voltage providing module includes a first sense voltage providing module connected to the strong logic high-level sense voltage line, wherein the first sense voltage providing module includes:

a first comparator having a first input terminal receiving a first target voltage and a second input terminal receiving a first feedback voltage, the first comparator generating a corresponding comparison result based on the first target voltage and the first feedback voltage, wherein the first feedback voltage is equal to the voltage on the strong logic high-level sensitive voltage line;

A first voltage output circuit receiving the preset sense amplification voltage of a strong logic high level and the overvoltage sense amplification voltage of a strong logic high level and connecting the strong logic high level sense voltage lines to selectively output the preset sense amplification voltage of a strong logic high level or the overvoltage sense amplification voltage of a strong logic high level to drive the strong logic high level sense voltage lines based on the comparison result;

when the first feedback voltage is smaller than the first target voltage, the first voltage output circuit selectively outputs the overvoltage sensitive amplifying voltage with a strong logic high level so as to drive the voltage on the strong logic high level sensitive voltage line to quickly rise;

when the first feedback voltage is not less than the first target voltage, the first voltage output circuit selectively outputs the preset sense amplifying voltage with a strong logic high level to drive the voltage on the sense voltage line with the strong logic high level to be stabilized at the preset sense amplifying voltage with the strong logic high level for normal operation,

wherein the overvoltage sense amplifying voltage is greater than the preset sense amplifying voltage.

4. The sense amplifying and driving circuit of claim 3, wherein the first sense voltage providing module further comprises:

and the analog sensitive amplifying module is connected with the second input end of the first comparator, wherein the analog sensitive amplifying module simulates the working state of the sensitive amplifying module so as to provide the first feedback voltage for the first comparator, which simulates the voltage on the high-logic high-level sensitive voltage line, and the analog sensitive amplifying module and the sensitive amplifying module are electrified at the same time.

5. The sense amplifying and driving circuit of claim 3, wherein the first target voltage is equal to or greater than the preset sense amplifying voltage, and the overvoltage sense amplifying voltage is greater than the first target voltage.

6. The sense amplifying and driving circuit according to claim 1, wherein the sense voltage lines include a strong logic high level sense voltage line and a strong logic low level sense voltage line;

the sense voltage providing module includes a second sense voltage providing module connected to the strong logic low level sense voltage line, wherein the second sense voltage providing module includes:

A second comparator having a first input terminal receiving a second target voltage and a second input terminal receiving a second feedback voltage, the second comparator generating a corresponding comparison result based on the second target voltage and the second feedback voltage, wherein the second feedback voltage is equal to the voltage on the strong logic low-level sensitive voltage line;

a second voltage output circuit receiving the preset sense amplification voltage of a strong logic low level and the overvoltage sense amplification voltage of a strong logic low level and connecting the strong logic low level sense voltage lines to selectively output the preset sense amplification voltage of a strong logic low level or the overvoltage sense amplification voltage of a strong logic low level based on the comparison result;

when the second feedback voltage is larger than the second target voltage, the second voltage output circuit selectively outputs the overvoltage sensitive amplifying voltage with a strong logic low level so as to drive the voltage on the strong logic low level sensitive voltage line to be quickly pulled down;

when the second feedback voltage is not greater than the second target voltage, the second voltage output circuit selectively outputs the preset sense amplifying voltage with a strong logic low level to drive the voltage on the high-level sense voltage line to be stabilized at the preset sense amplifying voltage with the strong logic low level for normal operation,

Wherein the overvoltage sense amplifier voltage is lower than the preset sense amplifier voltage.

7. The sense amplifying and driving circuit of claim 6, wherein the second sense voltage providing module further comprises:

and the analog sensitive amplifying module is connected with the second input end of the second comparator, wherein the analog sensitive amplifying module simulates the working state of the sensitive amplifying module so as to provide the second feedback voltage for the second comparator, which simulates the voltage on the strong logic low-level sensitive voltage line, and the analog sensitive amplifying module and the sensitive amplifying module are powered on simultaneously.

8. The sense amplifying and driving circuit of claim 7, wherein the second target voltage is less than or equal to the preset sense amplifying voltage, and the overvoltage sense amplifying voltage is less than the second target voltage.

9. The sense amplifying and driving circuit of claim 1, wherein the sense amplifying module comprises:

a first inversion unit connected between the target bit line and the complementary bit line, wherein when a memory cell connected to the target bit line is turned on, a target bit line voltage on the target bit line is shifted from an initialization potential according to a logic level stored in the memory cell, and the first inversion unit inverts the complementary bit line voltage on the complementary bit line to a strong potential of a first logic based on the shifted target bit line voltage;

And a second inversion unit connected between the complementary bit line and the target bit line, wherein when the complementary bit line voltage on the complementary bit line is pulled to the strong potential of the first logic, the second inversion unit inverts based on the complementary bit line voltage to pull the target bit line voltage on the target bit line to the strong potential of a second logic opposite to the first logic.

10. A random access memory comprising a sense amplifying and driving circuit according to any one of claims 1-9.