CN116417038A - Random access memory and bit line processing circuit thereof - Google Patents

Random access memory and bit line processing circuit thereof Download PDF

Info

Publication number
CN116417038A
CN116417038A CN202111672140.XA CN202111672140A CN116417038A CN 116417038 A CN116417038 A CN 116417038A CN 202111672140 A CN202111672140 A CN 202111672140A CN 116417038 A CN116417038 A CN 116417038A
Authority
CN
China
Prior art keywords
column selection
bit line
selection signal
complementary bit
random access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111672140.XA
Other languages
Chinese (zh)
Inventor
王美锋
王锦楠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhaoyi Innovation Technology Group Co ltd
Original Assignee
Zhaoyi Innovation Technology Group Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhaoyi Innovation Technology Group Co ltd filed Critical Zhaoyi Innovation Technology Group Co ltd
Priority to CN202111672140.XA priority Critical patent/CN116417038A/en
Publication of CN116417038A publication Critical patent/CN116417038A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application discloses a random access memory, this random access memory includes: the memory array comprises a plurality of word lines, a plurality of pairs of complementary bit lines and a plurality of memory cells, and a column selection circuit comprises a plurality of column selection modules, wherein each column selection module is respectively connected with a pair of complementary bit line pairs so as to determine whether the current complementary bit line pair is gated with the connected complementary input/output line pair based on a corresponding column selection signal; the column selection signals comprise a first column selection signal and a second column selection signal, wherein the first column selection signal is a column selection signal with normal on time, and the second column selection signal is a column selection signal with prolonged on time; when the current write operation executed by the random access memory is the last read-write operation, executing the column selection signal received by the current column gating module corresponding to the current write operation as a second column selection signal for prolonging the on time. By the mode, the data reading and writing speed can be improved.

Description

Random access memory and bit line processing circuit thereof
Technical Field
The present disclosure relates to the field of memory technologies, and in particular, to a random access memory and a bit line processing circuit thereof.
Background
The memory array of the memory includes a plurality of Word Lines (WL), a plurality of complementary bit lines (BL/bl#) and a plurality of memory cells, each of which is connected to one of the word lines WL and a pair of complementary bit lines (BL/bl#), respectively.
After the read/write operation is completed, since the read/write operation will destroy the information in the memory cell, a period of time (tWR) is waited after the data is successfully read or rewritten, the data on the target bit line BL is written back into the memory cell, so that the opened word line WL can be turned off after the data is restored to a state that can be accessed again, and then the precharge operation (precharge) can be performed on the circuit again, so that the overall read/write operation speed of the circuit will be affected.
Disclosure of Invention
In order to solve the above problems, the present application provides a random access memory capable of improving the speed of data reading and writing.
In order to solve the technical problems, one technical scheme adopted by the application is as follows: there is provided a random access memory including: the memory array comprises a plurality of word lines, a plurality of complementary bit lines and a plurality of memory cells, wherein each memory cell is respectively connected with one word line and one complementary bit line pair; a column selection circuit including a plurality of column select modules, wherein each column select module is respectively connected with a pair of complementary bit line pairs to determine whether the current complementary bit line pair is gated with the connected complementary input/output line pair based on a corresponding column select signal; the column selection signals comprise a first column selection signal and a second column selection signal, wherein the first column selection signal is a column selection signal with normal on time, and the second column selection signal is a column selection signal with prolonged on time; when the current write operation executed by the random access memory is the last read-write operation, the column selection signal received by the current column gating module corresponding to the current write operation is the second column selection signal for prolonging the on time.
Wherein the column select signal gates the current complementary bit line pair and the complementary input output line pair during a normal on time and rewrites the complementary bit line pair with a signal on the complementary input output line pair or outputs a signal on the complementary bit line pair to the complementary input output line pair.
Wherein, in the extension on time after the normal on time, the complementary bit line pair writes back the signal on the complementary bit line pair to the memory cell.
Wherein the column selection circuit includes: a judging circuit for determining whether the current writing operation is the last reading and writing operation based on the input signal; and a column selection signal generation circuit that outputs the first column selection signal or the second column selection signal based on the determination result of the determination circuit.
The input signal is an internal clock signal for performing read-write operation, and the judging circuit determines whether the next read-write operation is the last read-write operation according to the waveform of the internal clock signal after the data transmission of each read-write operation is completed.
Wherein, the word line is turned on; after the word line is started, continuous multi-stroke read-write operation is carried out on different complementary bit line pairs corresponding to the word line; after the last write operation is completed, a precharge phase is entered to charge the corresponding complementary bit line pair to an initialization potential.
Wherein the column selection communication generation circuit includes: a first column selection signal generation unit generating a first column selection signal based on a write command, wherein the first column selection signal is a column selection signal of a normal on-time; a second column selection signal generating unit connected to the first column selection signal generating unit for generating a second column selection signal based on the first column selection signal, wherein the second column selection signal is a column selection signal for prolonging the on time; and an output unit connected to the judging circuit, the first column selection signal generating unit and the second column selection signal generating unit to output the first column selection signal or the second column selection signal based on a judgment result of the judging circuit.
The second column selection signal generating unit is a delay circuit, and adds a delay on time to the on time of the first column selection signal to generate a second column selection signal with a prolonged on time.
Wherein, further include: the sense amplifying circuit comprises a plurality of sense amplifying modules, wherein each sense amplifying module is respectively connected with a corresponding complementary bit line pair so as to perform signal amplifying operation on the corresponding complementary bit line pair.
Wherein, the sense amplifier module includes: the first inversion unit is connected between the corresponding target bit line and the complementary bit line, wherein when the memory cell connected with the target bit line is started, the target bit line voltage on the target bit line is shifted from the initialization potential according to the logic level stored by the memory cell, and the first inversion unit turns over based on the shifted target bit line voltage to pull the complementary bit line voltage on the complementary bit line to the strong potential of the first logic; and a second inversion unit connected between the complementary bit line and the target bit line, wherein when the complementary bit line voltage is pulled to a strong potential placed at the first logic, the second inversion unit inverts based on the complementary bit line voltage, pulls the target bit line voltage to a strong potential of a second logic, the second logic being opposite to the first logic.
Wherein, further include: and the plurality of initialization modules are respectively connected with a corresponding complementary bit line pair to charge the corresponding complementary bit line pair to an initialization potential in a precharge stage.
Wherein, the column gating module includes: an eighth switch, the control end of which receives the column selection signal, the first path end is connected with the corresponding target bit line, and the second path end is connected with the corresponding target input/output line; and a ninth switch, the control end of which receives the column selection signal, the first path end of which is connected with the corresponding complementary bit line, and the second path end of which is connected with the corresponding complementary input/output line.
By means of the mode, the on time of the corresponding column selection signal can be increased when the last write operation is carried out, so that when signals on the complementary bit line pair are written back to the storage capacitor in the storage unit, the signals are simultaneously driven by the complementary bit line pair and the complementary input/output line pair, the speed of the write-back operation is improved, the time required by the write-back operation is further shortened, and the speed of one-time complete read-write operation is accelerated. Further, by increasing the pulse width, only the duration of the column selection signal is improved, the circuit structure is not changed, and the area of the random access memory is not increased. On the other hand, signals on the complementary bit line pair are written into the memory cell by driving the complementary bit line pair and the complementary input/output line pair simultaneously, so that the margin of the node voltage of the memory cell is improved, the data holding capacity of the memory cell is improved, and the accuracy of the memory cell on data storage is further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
FIG. 1 is a schematic diagram of a memory array of a random access memory provided herein;
FIG. 2 is a schematic diagram illustrating an embodiment of the first initialization module in FIG. 1;
FIG. 3 is a schematic diagram of an embodiment of the sense amplifier module of FIG. 1;
FIG. 4 is a schematic circuit diagram of an embodiment of the sense amplifier module of FIG. 3;
FIG. 5 is a schematic diagram of an embodiment of the column selection circuit of FIG. 1;
FIG. 6 is a schematic diagram of an embodiment of the I/O circuit of FIG. 1;
FIG. 7 is a schematic diagram of potential trend of an embodiment of the random access memory provided in the present application;
FIG. 8 is a timing diagram of a random access memory for continuous read/write;
FIG. 9 is a schematic diagram of another embodiment of the column select circuit of FIG. 1;
FIG. 10 is a schematic diagram of a comparison of column select signals;
FIG. 11 is a circuit schematic of an embodiment of a column select communication generation circuit;
FIG. 12 is a circuit schematic of another embodiment of a column select communication generation circuit;
fig. 13 is a schematic structural diagram of a random access memory provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not limiting. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present application are shown in the drawings. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a memory array of a random access memory provided in the present application, where the memory array 100 includes a plurality of Word Lines (WL), a plurality of complementary bit lines (BL and bl#) and a plurality of memory cells 110, and each memory cell 110 is connected to one WL and a pair of complementary bit lines (BL and bl#).
In an embodiment in which the random access memory is a dynamic random access memory (Dynamic Random Access Memory, DRAM), each memory cell 110 includes an access switch and a storage capacitor. The storage capacitor represents logical "1" and "0" by the more and less of the charge stored therein, or the high and low of the voltage difference across the storage capacitor. The on and off of the access switch determines whether to permit or prohibit reading and writing of information stored in the storage capacitor.
Specifically, the word line WL determines on or off of the access switch, the bit line BL is the only channel for external access to the storage capacitor, and after the access switch is turned on, external access can perform read or write operations on the storage capacitor through the bit line BL.
In one embodiment, the Common terminal (Common) of the storage capacitors is connected to Vref, and in one embodiment, vref=vcc/2.
When the information stored in the storage capacitor is "1", the voltage at the other end of the storage capacitor is Vcc, and at this time, the stored charge is:
Q＝+Vref*C
when the information stored in the storage capacitor is "0", the voltage at the other end of the storage capacitor is 0, and at this time, the stored charge is:
Q＝-Vref*C
further, the memory array 100 further includes a first initialization module 120, a sense amplification module 130, a column selection circuit 140, and an input-output circuit 150.
The first initialization module 120 is connected to a pair of complementary bit lines (BL/bl#) for charging the target bit line BL and the complementary bit line bl#) to an initialization potential in a precharge phase (precharge). The sense amplifier module 130 is connected to a pair of complementary bit line pairs (BL/bl#) for amplifying the logic potential on the target bit line BL to a corresponding strong potential when the memory cell 110 connected to the target bit line BL is turned on by the Word Line (WL). The input/output circuit 150 includes a pair of complementary input/output lines (IO/io#), and the column selection circuit 140 includes a plurality of column strobe modules 141 and a column select signal generation circuit 142, where each column strobe module 141 is respectively connected to a pair of complementary bit line pairs to determine whether the current complementary bit line pair is strobed with the connected complementary input/output line pair (IO/io#) based on the corresponding column select signal generated by the column select signal generation circuit 142.
Referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of the first initialization module in fig. 1, where the first initialization module 120 includes a switch T1, a switch T2, and a switch T3, control ends of the switch T1, the switch T2, and the switch T3 receive a first precharge control signal EQ1, a first pass end of the switch T1 is connected to a target bit line BL, a first pass end of the switch T2 is connected to a complementary bit line bl#, second pass ends of the switch T1 and the switch T2 are connected to an initialization potential Vref, a first pass end of the switch T3 is connected to the target bit line BL, and a second pass end of the switch T3 is connected to the complementary bit line bl#.
In the precharge phase, the first precharge control signal EQ1 controls the switches T1 and T2 to be turned on, and charges the target bit line BL and the complementary bit line bl# by the initialization potential Vref so that the potentials of the target bit line BL and the complementary bit line bl# are the initialization potentials. Further, the first precharge control signal EQ1 controls the switch T3 to be turned on so that the potentials of the target bit line BL and the complementary bit line bl# remain identical.
Alternatively, the above-mentioned switches T1, T2 and T3 may be nMOS transistors.
Referring to fig. 3, fig. 3 is a schematic structural diagram of an embodiment of the sense amplifying module in fig. 1, and the sense amplifying module 130 includes a first inverting unit 131 and a second inverting unit 132.
The first inversion unit 131 is connected between the target bit line BL and the complementary bit line BL#, wherein the target bit line voltage V on the target bit line BL is generated when the memory cell 110 connected to the target bit line BL is turned on BL The first inverting unit 131 is shifted from the initialization potential Vref according to the logic level stored in the memory cell 110, and the shifted target bit line voltage V BL Flip, the complementary bit line voltage V on the complementary bit line BL# BL# Pulled to a strong potential of the first logic.
The second inverting unit 132 is connected between the complementary bit line BL# and the target bit line BL, wherein the complementary bit line voltage V of BL# is on the complementary bit line BL# When the first logic is pulled to a strong potential, the second inverting unit 132 is based on the complementary bit line voltage V BL# Flip, the target bit line voltage V on the target bit line BL BL To a strong potential of a second logic opposite to the first logic.
Referring to fig. 3 and fig. 4, fig. 4 is a circuit schematic of an embodiment of the sense amplifying module in fig. 3, wherein the first inverting unit 131 includes a switch T4 and a switch T5, and the second inverting unit 132 includes a switch T6 and a switch T7.
Alternatively, in the present embodiment, the switches T4 and T6 are nMOS transistors, and the switches T5 and T7 are pMOS transistors.
Referring to fig. 5, fig. 5 is a schematic diagram of an embodiment of the column selection circuit in fig. 1, where the column selection circuit 140 includes a column selection signal generating circuit 142 and a plurality of column gating modules 141, and each column gating module 141 is respectively connected to a pair of complementary bit line pairs (BL/bl#) to determine whether the current complementary bit line pair (BL/bl#) is gated with the connected complementary input/output line pair (IO/io#) based on a corresponding column selection signal YS generated by the column selection signal generating circuit 142.
The column selection module 141 includes a switch T8 and a switch T9, and control ends of the switch T8 and the switch T9 are connected to a column selection signal generating circuit 142, for receiving a corresponding column selection signal YS; the first path end of the switch T8 is connected with the target bit line BL, the second path end is connected with the target input/output line IO, the first path end of the switch T9 is connected with the complementary bit line BL#, and the second path end is connected with the complementary input/output line IO#.
Specifically, when the corresponding column selection communication signal YS control switch T8 and switch T9 generated by the column selection communication signal generating circuit 142 are turned on, the target bit line BL is connected to the target input/output line IO, and the complementary bit line bl# is connected to the complementary input/output line io#, so as to realize gating of the complementary bit line pair (BL/bl#) and the complementary input/output line pair (IO/io#). In a Write operation (Write), charging/discharging the complementary bit line pair (BL/BL#) through the complementary input-output line pair (IO/IO#) to rewrite a signal on the complementary input-output line pair (IO/IO#) to a voltage on the complementary bit line pair (BL/BL#); in a Read operation, a signal on the complementary bit line pair (BL/BL#) is output to the complementary input/output line pair (IO/IO#).
Alternatively, the above-described switches T8 and T9 may be nMOS transistors.
Referring to fig. 6, fig. 6 is a schematic diagram of an embodiment of the input/output circuit in fig. 1, where the input/output circuit 150 includes a second initialization module 151.
The second initialization module 151 includes a switch T10, a switch T11, and a switch T12, wherein control ends of the switch T10, the switch T11, and the switch T12 receive a second precharge control signal EQ2, a first path end of the switch T10 is connected to the target input output line IO, a first path end of the switch T11 is connected to the complementary input output line io#, a second path end of the switch T10 and the switch T11 is connected to the reference potential Vcc, a first path end of the switch T12 is connected to the target input output line IO, and a second path end of the switch T12 is connected to the complementary input output line io#.
In the initialization stage of the input-output circuit 150, the second precharge control signal EQ2 controls the switch T10 and the switch T11 to be turned on, and charges the target input-output line IO and the complementary input-output line io# with the reference voltage Vcc, so that the potentials of the target input-output line IO and the complementary input-output line io# are the reference potential Vcc. Further, the second precharge control signal EQ2 controls the switch T12 to be turned on so that the potentials of the target input output line IO and the complementary input output line io# remain uniform. After the sense amplifier module 130 amplifies the logic level stored in the memory cell 110 read out on the complementary bit line pair (BL/bl#) and pulls it to either a strong "0" or a strong "1", the input output circuit 150 may communicate with the complementary bit line pair (BL/bl#) through the complementary input output line pair (IO/io#) to complete the read and write operation.
Alternatively, the above-described switch T10, switch T11, and switch T12 may be nMOS transistors.
Referring to fig. 7 in combination with fig. 1 to 6, fig. 7 is a schematic potential trend diagram of an embodiment of the dynamic random access memory provided in the present application, and the following describes the working process of the dynamic random access memory in the embodiment in a Read operation (Read) process, which includes a precharge phase, an access phase, a sense amplification phase, and a restore phase.
precharge phase:
at this stage, the voltages on the target bit line BL and the complementary bit line bl# are stabilized on Vref by first turning on the switches T1, T2, T3 by the control signal EQ1, assuming vref=vcc/2. And then proceeds to the next stage.
access phase:
through the precharge phase, the voltages on the target bit line BL and the complementary bit line bl# have stabilized at Vref, at which point the access switch in the memory cell 110 is turned on by controlling the word line WL (applying a voltage to the word line WL by an Active command). Positive charge stored in the storage capacitor in the memory cell 110 (e.g., vcc/2 for the common single-ended voltage of the capacitor and Vcc for the other end if the memory cell 110 stores a "1") flows to the target bit line BL, which in turn pulls up the voltage of the target bit line BL to vref+. And then proceeds to the next stage.
sense phase:
since the voltage of the target bit line BL is pulled up to Vref+ during the access phase, SAN is set to a strong potential of logic "0", and SAP is set to a strong potential of logic "1", vcc. Since the "1" stored in the memory cell 110 pulls up the voltage of the target bit line BL to Vref+, and the voltage of the complementary bit line BL# is still Vref, the switch T4 is more conductive than the switch T6, and the voltage on the complementary bit line BL# is pulled to the strong potential of logic "0" by SAN due to the conduction of T4. Since the gate of T7 is turned on at this time with a strong "0", the voltage on the target bit line BL is also pulled to a strong potential of logic "1" by SAP faster due to the conduction of T7. Then, the switch T4 and the switch T7 are turned on, and the switch T5 and the switch T6 are turned off. Finally, the voltages of the target Bit line BL and the complementary Bit line BL# are brought to a steady state, and the information Bit (previously assumed to be a "1") stored by the storage capacitor in the memory cell 110 is correctly presented.
Restore stage:
after the sense phase operation is completed, the target bit line BL is at a stable logic "1" strong potential Vcc, at which point the target bit line BL charges the storage capacitor in the memory cell 110. After a certain time, the charge of the storage capacitor can be restored to the state before the read operation.
Finally, as shown in fig. 5, the column selection signal generating circuit controls the YS signal to make the switch T8 and the switch T9 enter a conducting state, and outputs a strong "1" or a strong "0" signal on the target bit line BL to the IO line, so that the outside can read specific information. It should be noted that the restore phase is performed automatically during the word line WL on period, so that it is also possible for the read operation to perform the restore operation after the YS signal is turned on.
The above procedure describes a complete read operation, the pre-flow of the write operation is the same as the read operation, and precharge, access, sense and restore phase operations are performed. The difference is that the restore phase includes a write phase and then a write recovery operation is performed as follows:
as shown in fig. 5, the column selection signal YS is controlled by the column selection signal generating circuit 142 to put the switch T8 and the switch T9 into the on state, and the signal of the input/output line IO rewrites the target bit line BL. At this time, if "0" is written, the target bit line BL is pulled to a logic "0" level, and the complementary bit line BL# is pulled to a logic "1" level; if a "1" is written, the target bit line BL is pulled to a logic "1" level, and the complementary bit line BL# is pulled to a logic "0" level.
And then doing write recovery: after a certain time (i.e., tWR), when the charge of the storage capacitor in the memory cell 110 is discharged to the "0" state or charged to the "1" state by the voltage on the target bit line BL, the operation of writing "0" or "1" is completed by controlling the word line WL to turn off the switch in the memory cell 110.
It will be appreciated that, as shown in fig. 1, when one word line WL is turned on, weak charge information of the storage capacitor in the corresponding memory cell 110 appears on the target bit line BL due to charge sharing, and when there is a weak signal difference between the target bit line BL and the complementary bit line bl#, the sense amplifier module 130 can drive the target bit line bl# and the complementary bit line bl# to strong "1" or strong "0", respectively, and the time for completing this step is called tRCD inside the random access memory. The data READ out on the target bit line BL and the complementary bit line bl# may then be rewritten (WRITE) or directly output (READ). Both operations require that the data on the target bit line BL be transferred to the target input output line IO (READ) by the column select circuit 140 or that the BL be rewritten with the data on the target input output line IO (WRITE), and after the WRITE or READ operation is completed, since the information in the memory cell 110 is destroyed by both the READ and WRITE operations, waiting for a period of time after the data is READ or rewritten successfully (for the WRITE operation, the time from the reception of the WRITE command until the rewriting of the charge in the storage capacitor is completed is a tWR) to allow the data on the target bit line BL to be rewritten to the memory cell 110 for recovery (for the READ, for the WRITE, the WRITE recovery stage) until the state can be revisited, and then allowing the precharge operation to be performed again on the target bit line BL for the circuit and turning off the turned-on word line WL. Therefore, the whole read-write operation speed of the circuit can be influenced.
As shown in fig. 8, fig. 8 is a timing diagram of continuous reading/writing of the random access memory, if after a word line WL is turned on by an ACTIVE command to wait for tRCD time, continuous reading/writing operation is performed on the circuit, and the interval between every two consecutive reading/writing operations is tCCD, which is generally shorter, typically 4-5 clock cycles, and for the last writing operation, it takes a waiting time for the tWR to accept the precharge command, and the tWR has a longer time than tCCD, which affects the overall speed in the whole operation flow. Therefore, the conventional circuit configuration has a large influence of the tWR time on the overall speed of the circuit. In general, each WRITE operation is performed to rewrite data on the bit line BL by turning on the column selection signal YS after the data arrives at the input/output line IO, for example, "0" on the input/output line IO path when the data on the bit line BL is "1", and then "1" on the bit line BL is rewritten to "0" after the column selection signal YS is turned on, and then it is necessary to wait for the data on the bit line BL to be written back to the storage capacitor (WRITE recovery), which is a time period of tWR.
In an embodiment of the present invention, the on time of the column selection signal YS of the last write operation can be further increased by adjusting the column selection signal YS to prolong the strobe time of the complementary bit line pair BL/bl# and the complementary input/output line pair IO/io# so that when the data on the bit line BL is written back to the storage capacitor of the memory cell 110, not only the complementary bit line pair BL/bl# provides the operation current when writing back (write recovery) to the currently selected memory cell 110, but also the complementary input/output line IO/io# provides the operation current when writing back (write recovery) to the selected memory cell 110 through the complementary bit line pair BL/bl#.
Specifically, the column selection signal YS includes a first column selection signal and a second column selection signal, wherein the first column selection signal is a column selection signal with normal on time, and the second column selection signal is a column selection signal with extended on time;
when the current write operation performed by the random access memory is not the last read/write operation, the column selection signal YS received by the current column gating module 141 corresponding to the current write operation is the first column selection signal of the normal on time. When the current write operation performed by the random access memory is the last read/write operation, the column selection signal YS received by the current column strobe module 141 corresponding to the current write operation is the second column selection signal for prolonging the on time.
As described above, in the normal on time of the column selection signal YS, the column selection signal YS gates the current complementary bit line pair BL/bl# and the complementary input output line pair IO/io# to rewrite the complementary bit line pair BL/bl# (WRITE operation) with the signal on the complementary input output line pair IO/io#, or outputs the signal on the complementary bit line pair BL/bl#, to the complementary input output line pair IO/io# (READ operation). The invention sets the on time of the YS signal of the last writing operation as the extended on time, and in the extended on time after the normal on time, the complementary bit line pair BL/BL# writes back the signal on the complementary bit line pair BL/BL# into the (write recovery) memory cell 110, at this time, because the column selection signal YS is still on, the complementary input output line IO/IO# and the complementary bit line pair BL/BL# can provide the operation current for writing back to the selected memory cell 110 together, thereby accelerating the speed of charging and discharging the storage capacitor in the memory cell 110.
Referring to fig. 9, fig. 9 is a schematic diagram of another embodiment of the column selection circuit in fig. 1, and the column selection circuit 140 includes a column selection module 141, a column selection signal generating circuit 142, and a judging circuit 143.
Wherein the judging circuit 143 determines whether the current writing operation is the last reading and writing operation based on the input signal; the column selection signal generation circuit 142 outputs the first column selection signal or the second column selection signal based on the determination result of the determination circuit 143. Specifically, when the determination result of the determination circuit 143 is "the current write operation is not the last read/write operation", the first column selection signal is output, and when the determination result of the determination circuit 143 is "the current write operation is the last read/write operation", the second column selection signal is output.
It will be appreciated that in one embodiment, the input signal may be a read/write instruction set including a plurality of consecutive read instructions or write instructions. In another embodiment, the input signal may be an internal clock signal DQS of the ram for performing read/write operations, the read/write Data (DQ) on the complementary input/output line IO/io# is input/output by using the internal clock signal DQS as a sampling clock, and if the internal clock signal DQS continues to be valid after the data DQ of the current read/write operations are transmitted, for example, a subsequent signal (postamble) starts to flip again within a predetermined time, it indicates that the next read/write operation will still occur, so the determining circuit 143 in an embodiment of the present invention may determine whether the next read/write operation is the last write operation according to the waveform of the internal clock signal DQS after the data transmission of each read/write operation is completed.
Referring to fig. 10, fig. 10 is a schematic diagram showing a comparison of column selection signals, in the foregoing embodiment, the pulse width of the turned-on column selection signal YS corresponding to each read/write operation is kept consistent, which results in waiting for a long tWR after the last write operation is sent. In this embodiment, by recognizing the last write operation, the last YS pulse signal is lengthened when the column selection signal YS is transmitted, and the circuit's drawbacks in tWR are improved by this method.
Referring to fig. 9 again, as described above, after the corresponding complementary bit line pair BL/bl# is charged to the initializing potential by entering the precharge phase (precharge), the word line WL (Act in fig. 10) is turned on by the Active command; after the word line WL is turned on, continuous multiple read/write operations can be performed on different complementary bit line pairs BL/bl# corresponding to the word line WL, and it is noted that the word line WL as a row strobe signal can control the turn-on of the memory cells 110 to which the multiple bit lines BL are connected, and after the last read/write operation, multiple read/write operations can be continuously performed on one word line WL, because these continuous read/write operations are performed on different bit lines BL corresponding to the same word line WL, before the last write operation is completed, the bit line WL is turned on all the time, the write-back operation (write-back operation) on the current bit line bl# can be performed while the read/write operations are performed on other bit lines bl# are performed, therefore, only a tCCD with a short interval is needed between the previous two-by-two write operations (or read/write operations), and after the last read/write operation, the bit line WL is turned off and precharge operation is performed on the target bit line, therefore, in addition to the signal pair bl# on the complementary input/io# is required to be rewritten on the complementary bit line pair bl# and the complementary bit line is required to wait for the write-back operation 110 #; after the last read/write operation is completed, the precharge phase (Pre in fig. 10) is entered again to charge the corresponding complementary bit line pair BL/bl# to the initialization potential. Since the width of the pulse signal corresponding to the column selection signal YS of the last write operation is increased, the on time of the switches T8 and T9 is prolonged, and not only the complementary bit line pair BL/bl# provides the memory cell 110 with the operation current of the write-back operation, but also the memory cell 110 with the complementary input/output line IO/io# pair BL/bl# which is kept on. That is, the storage capacitor in the memory cell 110 is charged and discharged by the complementary bit line pair BL/bl# and the complementary input/output line IO/io# at the same time, and the driving capability of the complementary input/output line IO/io# is stronger than that of the complementary bit line pair BL/bl#, so that the charging and discharging speed is increased, the time for the write-back operation of the memory cell 110 is further reduced, and the time required for the tWR is reduced, so that the speed of one complete read-write operation is increased.
Further, by adopting the above mode of increasing the pulse width, only the duration of the column selection signal YS of the last read-write operation is improved, the circuit structure is not changed, and the area of the random access memory is not increased. On the other hand, signals on the complementary bit line pair BL/BL# are written back to the memory cell 110 through the complementary bit line pair BL/BL# and the complementary input/output line IO/IO# in the write-back stage, the margin of the node voltage of the memory cell 110 is improved, the data holding capacity of the memory cell 110 is improved, and the accuracy of data storage of the memory cell is further improved.
Referring to fig. 11, fig. 11 is a circuit diagram of an embodiment of a column selection signal generating circuit, and the column selection signal generating circuit 142 may include a first column selection signal generating unit 142a, a second column selection signal generating unit 142b, and an output unit 142c.
Wherein the first column selection signal generation unit 142a generates a first column selection signal based on the read/write command, wherein the first column selection signal is a column selection signal of a normal on time; the second column selection signal generating unit 142b is connected to the first column selection signal generating unit 142a, and generates a second column selection signal based on the first column selection signal, wherein the second column selection signal is a column selection signal with an extended on time; the output unit 142c is connected to the judgment circuit 143, the first column selection signal generation unit 142a, and the second column selection signal generation unit 142b to output the first column selection signal or the second column selection signal based on the judgment result of the judgment circuit 143.
It will be appreciated that the first column select signal is a high signal that is used to turn on the switches T8 and T9 (T8 and T9 are nMOS transistors), and the duration of the high signal is the on time of the switches T8 and T9. In this embodiment, the high level duration of the first column selection signal is constant, and the second column selection signal generating unit 142b is configured to delay the first column selection signal to extend the duration thereof, and generate a corresponding second column selection signal.
Alternatively, the output unit 142c in this embodiment may be a multiplexer (such as two-way) for selectively outputting the first column selection signal or the second column selection signal according to the determination result of the determination circuit 143.
Referring specifically to fig. 12, fig. 12 is a circuit schematic of another embodiment of a column selection signal generating circuit, and the column selection signal generating circuit 142 may specifically include a first column selection signal generating unit 142a, a delay circuit DLY, and a multiplexer MUX.
Wherein the first column selection signal generation unit 142a generates a first column selection signal based on the read/write command, wherein the first column selection signal is a column selection signal of a normal on time; the delay circuit DLY is used for adding a delay on time to the on time of the first column selection signal so as to generate a second column selection signal with the prolonged on time; the multiplexer MUX connects the judgment circuit 143, the first column selection signal generation unit 142a, and the delay circuit DLY to output the first column selection signal or the second column selection signal based on the judgment result of the judgment circuit 143.
Alternatively, the delay on time may be set correspondingly according to the excess time of tWR compared to tCCD in the previous embodiment. For example, the larger the difference in tWR-tCCD, the larger the delay on time can be.
It can be understood that by increasing the width of the pulse signal of the column selection signal YS for the last writing operation, the storage capacitor in the memory cell 110 is simultaneously charged and discharged by the complementary bit line pair BL/bl# and the complementary input/output line IO/io# at the same time, so that the charging and discharging speed is increased, the time is further reduced, and the time required for the tWR is reduced, and the speed of one complete read/write operation is increased. Further, by adopting the above-mentioned mode of increasing the pulse width, only the duration of the signal is improved, the circuit structure is not changed, and the area of the random access memory is not increased. On the other hand, the complementary bit line pair BL/BL# and the complementary input/output line IO/IO# are charged and discharged simultaneously, so that the margin of the node voltage of the memory cell is improved, the data holding capacity of the memory cell is improved, and the accuracy of data storage of the memory cell is further improved.
Referring to fig. 13, fig. 13 is a schematic structural diagram of a random access memory provided in the present application, and the random access memory 200 includes the memory array 100 described in the above embodiments.
Optionally, the random access memory 200 may further include a controller coupled to the memory array 100 for generating control signals to control the operation of the memory array 100. The control signal may be WL signal, EQ1 signal, YS signal, etc. in the above embodiment, and it is understood that the column selection signal generating circuit 142 in the above embodiment may be integrated in the controller.
Optionally, the random access memory 200 in the present embodiment is a DRAM (Dynamic Random Access Memory ). DRAM is a semiconductor memory and the main principle of operation is to use how much charge is stored in a capacitor to represent whether a binary bit (bit) is "1" or "0".
In combination with the advantages of the above embodiment, since the width of the pulse signal of the column selection signal YS for the last writing operation is increased, the storage capacitor in the memory cell is simultaneously charged and discharged by the complementary bit line pair BL/bl# and the complementary input/output line IO/io# at the same time, so that the charging and discharging speed is increased, the time required for the write-back (write recovery) operation is further reduced, and thus the time required for the tWR is reduced, and the speed of one complete read-write operation is increased. Further, by increasing the pulse width, only the duration of the column selection signal YS is improved, the circuit structure is not changed, and the area of the random access memory is not increased. On the other hand, signals on the complementary bit line pair are written into the memory cell by driving the complementary bit line pair BL/BL# and the complementary input/output line IO/IO# simultaneously, so that the margin of the node voltage of the memory cell is improved, the data holding capacity of the memory cell is improved, and the accuracy of the memory cell on data storage is further improved.
Embodiments of the present application are implemented in the form of software functional units and sold or used as a stand-alone product, which may be stored on a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution, in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the patent application, and all equivalent structures or equivalent processes according to the specification and drawings of the present application, or direct or indirect application in other related technical fields, are included in the scope of the patent protection of the present application.

Claims (12)

1. A random access memory, comprising:
the memory array comprises a plurality of word lines, a plurality of complementary bit lines and a plurality of memory cells, wherein each memory cell is respectively connected with one word line and one complementary bit line pair;
a column selection circuit including a plurality of column select modules, wherein each column select module is respectively connected with a pair of complementary bit line pairs to determine whether the current complementary bit line pair is gated with the connected complementary input/output line pair based on a corresponding column select signal;
the column selection signals comprise a first column selection signal and a second column selection signal, wherein the first column selection signal is a column selection signal with normal on time, and the second column selection signal is a column selection signal with prolonged on time;
when the current write operation executed by the random access memory is the last read-write operation, executing the column selection signal received by the current column gating module corresponding to the current write operation as the second column selection signal for prolonging the on time.
2. The random access memory of claim 1, wherein during the normal on time, the column select signal gates the current complementary bit line pair with the complementary input-output line pair and overwrites the complementary bit line pair with a signal on the complementary input-output line pair or the signal on the complementary bit line pair is output to the complementary input-output line pair.
3. The random access memory of claim 2 wherein said complementary bit line pair writes back a signal thereon to said memory cell during said extended on-time following said normal on-time.
4. The random access memory of claim 1, wherein the column select circuit comprises:
a judging circuit for determining whether the current writing operation is the last reading and writing operation based on an input signal;
and a column selection signal generation circuit that outputs the first column selection signal or the second column selection signal based on a determination result of the determination circuit.
5. The random access memory according to claim 4, wherein the input signal is an internal clock signal for performing the read/write operation, and the determining circuit determines whether the next read/write operation is the last read/write operation according to a waveform of the internal clock signal after the data transmission of each read/write operation is completed.
6. The random access memory of claim 4, wherein the word line is turned on; after the word line is started, performing continuous multi-stroke read-write operation on different complementary bit line pairs corresponding to the word line; after the last write operation is completed, a precharge phase is entered to charge the corresponding complementary bit line pair to an initialization potential.
7. The random access memory of claim 4 wherein said column select communication generation circuit comprises:
a first column selection signal generation unit that generates the first column selection signal based on a write command, wherein the first column selection signal is a column selection signal of a normal on-time;
a second column selection signal generation unit connected to the first column selection signal generation unit, the second column selection signal being generated based on the first column selection signal, wherein the second column selection signal is a column selection signal that extends on-time;
and an output unit connected to the judgment circuit, the first column selection signal generation unit and the second column selection signal generation unit to output the first column selection signal or the second column selection signal based on a judgment result of the judgment circuit.
8. The random access memory according to claim 7, wherein the second column selection signal generating unit is a delay circuit that adds a delayed on-time to an on-time of the first column selection signal to generate the second column selection signal with the extended on-time.
9. A random access memory according to claim 1, further comprising:
the sense amplifying circuit comprises a plurality of sense amplifying modules, wherein each sense amplifying module is respectively connected with a corresponding complementary bit line pair so as to perform signal amplifying operation on the corresponding complementary bit line pair.
10. The random access memory of claim 9, wherein the sense amplifier module comprises:
a first inversion unit connected between a corresponding target bit line and a complementary bit line, wherein when a memory cell connected to the target bit line is turned on, a target bit line voltage on the target bit line is shifted from the initialization potential according to a logic level stored in the memory cell, and the first inversion unit inverts the target bit line voltage based on the shifted target bit line voltage to pull the complementary bit line voltage on the complementary bit line to a strong potential of a first logic;
and a second inversion unit connected between the complementary bit line and the target bit line, wherein the second inversion unit inverts the complementary bit line voltage to pull the target bit line voltage to a strong potential of a second logic opposite to the first logic when the complementary bit line voltage is pulled to the strong potential placed at the first logic.
11. A random access memory according to claim 1, further comprising:
and the plurality of initialization modules are respectively connected with a corresponding complementary bit line pair to charge the corresponding complementary bit line pair to an initialization potential in a precharge stage.
12. The random access memory of claim 1, wherein the column select module comprises:
an eighth switch, the control end of which receives the column selection signal, the first path end is connected with the corresponding target bit line, and the second path end is connected with the corresponding target input/output line;
and a ninth switch, the control end of which receives the column selection signal, the first path end of which is connected with the corresponding complementary bit line, and the second path end of which is connected with the corresponding complementary input/output line.
CN202111672140.XA 2021-12-31 2021-12-31 Random access memory and bit line processing circuit thereof Pending CN116417038A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111672140.XA CN116417038A (en) 2021-12-31 2021-12-31 Random access memory and bit line processing circuit thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111672140.XA CN116417038A (en) 2021-12-31 2021-12-31 Random access memory and bit line processing circuit thereof

Publications (1)

Publication Number Publication Date
CN116417038A true CN116417038A (en) 2023-07-11

Family

ID=87051837

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111672140.XA Pending CN116417038A (en) 2021-12-31 2021-12-31 Random access memory and bit line processing circuit thereof

Country Status (1)

Country Link
CN (1) CN116417038A (en)

Similar Documents

Publication Publication Date Title
JP5080059B2 (en) Execution of read and write operations in the same cycle of the SRAM device
US7505336B2 (en) Method and apparatus for synchronization of row and column access operations
US5315550A (en) Dynamic random access memory having sense amplifier activation delayed based on operation supply voltage and operating method thereof
JP3241280B2 (en) Dynamic semiconductor memory device
US7626877B2 (en) Low voltage sense amplifier and sensing method
KR100247873B1 (en) Semiconductor memory device and a method of reading/writing data
KR100865906B1 (en) Low-voltage sense amplifier and method
JPH087997B2 (en) Random access memory device
US6556482B2 (en) Semiconductor memory device
US20130121053A1 (en) Methods and circuits for limiting bit line leakage current in a content addressable memory (cam) device
US6172919B1 (en) Semiconductor memory device with independently controlled reading and writing time periods
JPH081749B2 (en) Dynamic random access memory device
US5703829A (en) Synchronous type semiconductor memory device which can be adapted to high frequency system clock signal
US6574151B2 (en) Semiconductor memory device and write driving thereof
CN116524969A (en) Random access memory and sensitive amplifying and driving circuit thereof
US20040240303A1 (en) Method of reading memory device in page mode and row decoder control circuit using the same
CN116417038A (en) Random access memory and bit line processing circuit thereof
KR20080047157A (en) Power supply circuit for sense amplifier of semiconductor memory device
US6483762B1 (en) tRCD margin
CN218939253U (en) Random access memory
US6115308A (en) Sense amplifier and method of using the same with pipelined read, restore and write operations
CN116453562A (en) Word line driving circuit suitable for random access memory and random access memory
US20230139664A1 (en) Memory read-write circuit, method for controlling memory, and electronic device
EP1132923B1 (en) Bit line sense circuit and method for dynamic random access memories
CN117995230A (en) Column decoding circuit and random access memory

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination