JP6525554B2 - 基板構造体を含むcmos素子 - Google Patents
基板構造体を含むcmos素子 Download PDFInfo
- Publication number
- JP6525554B2 JP6525554B2 JP2014221672A JP2014221672A JP6525554B2 JP 6525554 B2 JP6525554 B2 JP 6525554B2 JP 2014221672 A JP2014221672 A JP 2014221672A JP 2014221672 A JP2014221672 A JP 2014221672A JP 6525554 B2 JP6525554 B2 JP 6525554B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- type transistor
- type
- cmos device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims description 101
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 35
- 229910052710 silicon Inorganic materials 0.000 claims description 35
- 239000010703 silicon Substances 0.000 claims description 35
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 16
- 229910005542 GaSb Inorganic materials 0.000 claims description 8
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 claims description 8
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 7
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 7
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 7
- 229910005898 GeSn Inorganic materials 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 395
- 239000000463 material Substances 0.000 description 67
- 238000004519 manufacturing process Methods 0.000 description 25
- 239000004065 semiconductor Substances 0.000 description 24
- 239000010408 film Substances 0.000 description 22
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 10
- 229910052796 boron Inorganic materials 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 8
- 239000011574 phosphorus Substances 0.000 description 8
- 230000007547 defect Effects 0.000 description 7
- 150000001875 compounds Chemical class 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/02452—Group 14 semiconducting materials including tin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
- H01L21/02645—Seed materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/062—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the metal-insulator-semiconductor type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Description
前記バッファ層は、Ge、SiGe、又はGeSnを含む少なくとも1層を含み得る。
前記基板は、シリコン系基板又はシリコン基板であり得る。
前記基板構造体は、前記少なくとも1層のバッファ層上に、IV族物質又はIII−V族物質で形成される半導体層を更に備えることができる。
前記IV族物質は、Geを含み得る。
前記III−V族物質は、InGaAs、InP、InSb、InGaSb、GaSb及びInAsのうちの少なくとも一つを含み得る。
前記シード層は、0より大きく100nm以下の範囲の厚みを有し得る。
前記バッファ層は、0より大きく3μm以下の範囲の厚みを有し得る。
10、110、210、310、410 基板
20、220、320、420 シード層
21 第1層
22 第2層
23 第3層
24 第4層
31 第5層
32 第6層
30、230、330、430、431 バッファ層
40 半導体層
100、200 CMOS素子
120 第1シード層
121 第2シード層
130 第1バッファ層
131 第2バッファ層
140、240、347、441 (第1型トランジスタ用)第1層
141、241、355、455 (第2型トランジスタ用)第2層
150、250 第1絶縁層
151、251 第2絶縁層
152、252 第3絶縁層
340、440 第1型トランジスタ用物質層
348、418 第1パターン領域
350、434 絶縁層
353、453 第2パターン領域
360、460 第1ゲート絶縁層
363、463 第1スペーサ
370、470 第2ゲート絶縁層
373、473 第2スペーサ
500 ウェーハ
505 1つのセル
510 第1領域
520 第2領域
530 第3領域
D1、D2、D11、D12 ドレイン電極
G1、G2、G11、G12 ゲート電極
S1、S2、S11、S12 ソース電極
Claims (8)
- 基板と、
前記基板上に具備され、B、BGe、BSiGe、又はBGeからなるグレーデッド層を含む少なくとも1層のシード層と、
前記シード層上の少なくとも1層のバッファ層と、
前記バッファ層上の第1型トランジスタ用第1層と、
前記第1型トランジスタ用第1層から離隔されるように配置されて前記シード層の直上、バッファ層の直上、又は前記基板の直上に配置された第2型トランジスタ用第2層と、
前記第1型トランジスタ用第1層と前記第2型トランジスタ用第2層との間で前記第1層と前記第2層とを離隔させる絶縁層と、を備えることを特徴とするCMOS素子。
- 前記バッファ層は、Ge、SiGe、GeSn、又はSiGeからなるグレーデッド層を含む少なくとも1層を含むことを特徴とする請求項1に記載のCMOS素子。
- 前記基板は、シリコン基板であることを特徴とする請求項1に記載のCMOS素子。
- 前記シード層は、0より大きく100nm以下の範囲の厚みを有することを特徴とする請求項1に記載のCMOS素子。
- 前記バッファ層は、0より大きく3μm以下の範囲の厚みを有することを特徴とする請求項1に記載のCMOS素子。
- 前記第1型トランジスタ用第1層は、InGaAs、InP、InSb、InGaSb、GaSb、及びInAsのうちの少なくとも一つを含むことを特徴とする請求項1に記載のCMOS素子。
- 前記第2型トランジスタ用第2層は、Geを含むことを特徴とする請求項1に記載のCMOS素子。
- 前記第1型トランジスタは、n型MOSFETであり、
前記第2型トランジスタは、p型MOSFETであることを特徴とする請求項1に記載のCMOS素子。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020130131507A KR102104062B1 (ko) | 2013-10-31 | 2013-10-31 | 기판 구조체, 이를 포함한 cmos 소자 및 cmos 소자 제조 방법 |
KR10-2013-0131507 | 2013-10-31 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2015088756A JP2015088756A (ja) | 2015-05-07 |
JP2015088756A5 JP2015088756A5 (ja) | 2017-07-06 |
JP6525554B2 true JP6525554B2 (ja) | 2019-06-05 |
Family
ID=52994405
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014221672A Active JP6525554B2 (ja) | 2013-10-31 | 2014-10-30 | 基板構造体を含むcmos素子 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9570359B2 (ja) |
JP (1) | JP6525554B2 (ja) |
KR (1) | KR102104062B1 (ja) |
CN (1) | CN104600070B (ja) |
TW (1) | TWI639221B (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9558943B1 (en) * | 2015-07-13 | 2017-01-31 | Globalfoundries Inc. | Stress relaxed buffer layer on textured silicon surface |
US10153300B2 (en) * | 2016-02-05 | 2018-12-11 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device including a high-electron-mobility transistor (HEMT) and method for manufacturing the same |
WO2018042534A1 (ja) | 2016-08-31 | 2018-03-08 | 富士通株式会社 | 半導体結晶基板、赤外線検出装置、光半導体装置、半導体装置、熱電変換素子、半導体結晶基板の製造方法及び赤外線検出装置の製造方法 |
CN108063143B (zh) * | 2016-11-09 | 2020-06-05 | 上海新昇半导体科技有限公司 | 一种互补晶体管器件结构及其制作方法 |
CN108573852A (zh) * | 2017-03-08 | 2018-09-25 | 上海新昇半导体科技有限公司 | 具有原子级平整表面的薄膜的制备方法 |
KR102034175B1 (ko) | 2017-05-30 | 2019-10-18 | 한국과학기술연구원 | 수평 배열된 반도체 채널을 가지는 반도체 소자 및 이의 제조 방법 |
Family Cites Families (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2657071B2 (ja) * | 1988-07-18 | 1997-09-24 | 三洋電機株式会社 | 多結晶シリコン薄膜及びその形成方法 |
JP2854038B2 (ja) * | 1989-10-12 | 1999-02-03 | 三洋電機株式会社 | 半導体素子 |
US5273930A (en) | 1992-09-03 | 1993-12-28 | Motorola, Inc. | Method of forming a non-selective silicon-germanium epitaxial film |
CA2295069A1 (en) | 1997-06-24 | 1998-12-30 | Eugene A. Fitzgerald | Controlling threading dislocation densities in ge on si using graded gesi layers and planarization |
US6429061B1 (en) | 2000-07-26 | 2002-08-06 | International Business Machines Corporation | Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation |
US6677192B1 (en) | 2001-03-02 | 2004-01-13 | Amberwave Systems Corporation | Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits |
US6849508B2 (en) | 2001-06-07 | 2005-02-01 | Amberwave Systems Corporation | Method of forming multiple gate insulators on a strained semiconductor heterostructure |
JP2003031813A (ja) * | 2001-07-19 | 2003-01-31 | Matsushita Electric Ind Co Ltd | 半導体装置 |
WO2004102635A2 (en) | 2002-10-30 | 2004-11-25 | Amberwave Systems Corporation | Methods for preserving strained semiconductor layers during oxide layer formation |
JP4306266B2 (ja) * | 2003-02-04 | 2009-07-29 | 株式会社Sumco | 半導体基板の製造方法 |
US7238595B2 (en) | 2003-03-13 | 2007-07-03 | Asm America, Inc. | Epitaxial semiconductor deposition methods and structures |
US6963078B2 (en) | 2003-03-15 | 2005-11-08 | International Business Machines Corporation | Dual strain-state SiGe layers for microelectronics |
US7589003B2 (en) | 2003-06-13 | 2009-09-15 | Arizona Board Of Regents, Acting For And On Behalf Of Arizona State University, A Corporate Body Organized Under Arizona Law | GeSn alloys and ordered phases with direct tunable bandgaps grown directly on silicon |
US7157379B2 (en) | 2003-09-23 | 2007-01-02 | Intel Corporation | Strained semiconductor structures |
US6936530B1 (en) * | 2004-02-05 | 2005-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Deposition method for Si-Ge epi layer on different intermediate substrates |
US7125785B2 (en) * | 2004-06-14 | 2006-10-24 | International Business Machines Corporation | Mixed orientation and mixed material semiconductor-on-insulator wafer |
KR100593747B1 (ko) | 2004-10-11 | 2006-06-28 | 삼성전자주식회사 | 실리콘게르마늄층을 구비하는 반도체 구조물 및 그 제조방법 |
US20090130826A1 (en) | 2004-10-11 | 2009-05-21 | Samsung Electronics Co., Ltd. | Method of Forming a Semiconductor Device Having a Strained Silicon Layer on a Silicon-Germanium Layer |
KR101186291B1 (ko) * | 2005-05-24 | 2012-09-27 | 삼성전자주식회사 | 게르마늄 온 인슐레이터 구조 및 이를 이용한 반도체 소자 |
US8334155B2 (en) * | 2005-09-27 | 2012-12-18 | Philips Lumileds Lighting Company Llc | Substrate for growing a III-V light emitting device |
JP2007142291A (ja) * | 2005-11-21 | 2007-06-07 | Canon Anelva Corp | 半導体構造およびその成長方法 |
US7728387B1 (en) | 2006-06-13 | 2010-06-01 | The Board Of Trustees Of The Leland Stanford Junior University | Semiconductor device with high on current and low leakage |
WO2008030574A1 (en) | 2006-09-07 | 2008-03-13 | Amberwave Systems Corporation | Defect reduction using aspect ratio trapping |
US7799592B2 (en) | 2006-09-27 | 2010-09-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tri-gate field-effect transistors formed by aspect ratio trapping |
KR20090038653A (ko) * | 2007-10-16 | 2009-04-21 | 삼성전자주식회사 | Cmos 소자 및 그 제조방법 |
JP2009158853A (ja) * | 2007-12-27 | 2009-07-16 | Toshiba Corp | 半導体装置 |
US7902009B2 (en) | 2008-12-11 | 2011-03-08 | Intel Corporation | Graded high germanium compound films for strained semiconductor devices |
DE112010000968T5 (de) * | 2009-03-05 | 2012-08-02 | Applied Materials, Inc. | Verfahren zum Ablagern von Schichten mit reduzierter Grenzflächenverschmutzung |
WO2010140373A1 (ja) * | 2009-06-05 | 2010-12-09 | 住友化学株式会社 | センサ、半導体基板、および半導体基板の製造方法 |
CN102449785A (zh) * | 2009-06-05 | 2012-05-09 | 住友化学株式会社 | 光器件、半导体基板、光器件的制造方法、以及半导体基板的制造方法 |
JP5545706B2 (ja) | 2009-06-18 | 2014-07-09 | 日本電信電話株式会社 | ホウ素ドーピング方法および半導体装置の製造方法 |
US9922878B2 (en) | 2010-01-08 | 2018-03-20 | Semiconductor Manufacturing International (Shanghai) Corporation | Hybrid integrated semiconductor tri-gate and split dual-gate FinFET devices and method for manufacturing |
EP2474643B1 (en) | 2011-01-11 | 2016-01-06 | Imec | Method for direct deposition of a germanium layer |
CN102162137B (zh) * | 2011-01-28 | 2013-05-29 | 中国科学院上海硅酸盐研究所 | 一种高质量应变的Ge/SiGe超晶格结构及其制备方法 |
CN102790084B (zh) * | 2011-05-16 | 2016-03-16 | 中国科学院上海微系统与信息技术研究所 | 锗和iii-v混合共平面的soi半导体结构及其制备方法 |
US8835988B2 (en) * | 2011-06-06 | 2014-09-16 | Eta Semiconductor Inc. | Hybrid monolithic integration |
TW201306236A (zh) * | 2011-06-10 | 2013-02-01 | Sumitomo Chemical Co | 半導體裝置、半導體基板、半導體基板之製造方法及半導體裝置之製造方法 |
US20130069172A1 (en) | 2011-09-16 | 2013-03-21 | United Microelectronics Corp. | Semiconductor device and method for fabricating the same |
US8754448B2 (en) | 2011-11-01 | 2014-06-17 | United Microelectronics Corp. | Semiconductor device having epitaxial layer |
JP2013125955A (ja) | 2011-12-16 | 2013-06-24 | Elpida Memory Inc | 半導体装置及びその製造方法 |
KR102083495B1 (ko) | 2013-01-07 | 2020-03-02 | 삼성전자 주식회사 | Cmos 소자와 이를 포함하는 광학장치와 그 제조방법 |
US20150021681A1 (en) * | 2013-07-16 | 2015-01-22 | United Microelectronics Corp. | Semiconductor device having metal gate and manufacturing method thereof |
KR102210325B1 (ko) * | 2013-09-06 | 2021-02-01 | 삼성전자주식회사 | Cmos 소자 및 그 제조 방법 |
-
2013
- 2013-10-31 KR KR1020130131507A patent/KR102104062B1/ko active IP Right Grant
-
2014
- 2014-09-26 TW TW103133382A patent/TWI639221B/zh active
- 2014-10-09 US US14/510,354 patent/US9570359B2/en active Active
- 2014-10-30 JP JP2014221672A patent/JP6525554B2/ja active Active
- 2014-10-31 CN CN201410601952.9A patent/CN104600070B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
US20150115321A1 (en) | 2015-04-30 |
KR102104062B1 (ko) | 2020-04-23 |
TWI639221B (zh) | 2018-10-21 |
JP2015088756A (ja) | 2015-05-07 |
US9570359B2 (en) | 2017-02-14 |
CN104600070A (zh) | 2015-05-06 |
KR20150050096A (ko) | 2015-05-08 |
CN104600070B (zh) | 2019-06-07 |
TW201523837A (zh) | 2015-06-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6525554B2 (ja) | 基板構造体を含むcmos素子 | |
TWI585863B (zh) | 適於具有異質基板的三族氮化物元件的緩衝層結構 | |
KR102210325B1 (ko) | Cmos 소자 및 그 제조 방법 | |
JP5167816B2 (ja) | フィン型半導体装置及びその製造方法 | |
TW202141584A (zh) | 與工程基板整合之電力元件 | |
JP2008505482A5 (ja) | ||
US20140091392A1 (en) | Semiconductor device, semiconductor wafer, method for producing semiconductor wafer, and method for producing semiconductor device | |
US20130062696A1 (en) | SOI Semiconductor Structure with a Hybrid of Coplanar Germanium and III-V, and Preparation Method thereof | |
KR20090100230A (ko) | 샌드위치 구조의 웨이퍼 결합 및 포톤 빔을 이용한 단결정 반도체 박막 전이 | |
US20140299885A1 (en) | Substrate structures and semiconductor devices employing the same | |
KR20200092381A (ko) | 가공된 기판 상의 집적된 디바이스를 위한 시스템 및 방법 | |
US8680510B2 (en) | Method of forming compound semiconductor | |
KR102153945B1 (ko) | 이차원 반도체 소재를 이용한 전자소자 | |
CN102107852A (zh) | 半导体纳米结构和制造方法及其应用 | |
CN101093847A (zh) | 半导体器件及其制造方法 | |
US9209022B2 (en) | Semiconductor structure including laterally disposed layers having different crystal orientations and method of fabricating the same | |
KR20140092605A (ko) | 질화물 반도체 발광 소자 | |
JP7444285B2 (ja) | 半導体構造および電界効果トランジスタの作製方法 | |
JP6228874B2 (ja) | 半導体光素子 | |
KR101531870B1 (ko) | 계단형 트렌치를 이용하여 실리콘 기판 상에 대면적 화합물 반도체 소자를 제조하는 방법 | |
JP6228873B2 (ja) | 半導体光素子の製造方法 | |
JP2014090121A (ja) | 複合基板の製造方法 | |
TWI788869B (zh) | 高電子遷移率電晶體及其複合基板 | |
JP2014150248A (ja) | 素子形成用基板の作製方法 | |
US8536028B1 (en) | Self alignment and assembly fabrication method for stacking multiple material layers |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170526 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20170526 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20180703 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181003 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20181023 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190123 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20190409 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20190507 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6525554 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |