JP2015088756A - 基板構造体とそれを含むcmos素子及びその製造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000000463 material Substances 0.000 claims abstract description 75
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052796 boron Inorganic materials 0.000 claims abstract description 15
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 12
- 239000011574 phosphorus Substances 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 36
- 229910052710 silicon Inorganic materials 0.000 claims description 36
- 239000010703 silicon Substances 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 25
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 22
- 229910005542 GaSb Inorganic materials 0.000 claims description 9
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 claims description 9
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 8
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 8
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 8
- 229910005898 GeSn Inorganic materials 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 405
- 239000010408 film Substances 0.000 description 22
- 238000010586 diagram Methods 0.000 description 21
- 238000000034 method Methods 0.000 description 21
- 230000007547 defect Effects 0.000 description 7
- 150000001875 compounds Chemical class 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- HXQQNYSFSLBXQJ-UHFFFAOYSA-N COC1=C(NC(CO)C(O)=O)CC(O)(CO)CC1=NCC(O)=O Chemical compound COC1=C(NC(CO)C(O)=O)CC(O)(CO)CC1=NCC(O)=O HXQQNYSFSLBXQJ-UHFFFAOYSA-N 0.000 description 1
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
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Abstract
【解決手段】本発明の基板構造体は、基板と、基板上に具備されてホウ素又はリンを含む物質で形成される少なくとも1層のシード層と、シード層上の少なくとも1層のバッファ層と、を備える。
【選択図】図1
Description
また、本発明の目的は、一枚の基板上にn型トランジスタ用層及びp型トランジスタ用層を共に含むCMOS素子を提供することにある。
また、本発明の目的は、一枚の基板上にn型トランジスタ用層及びp型トランジスタ用層を共に含むCMOS素子の製造方法を提供することにある。
前記バッファ層は、Ge、SiGe、又はGeSnを含む少なくとも1層を含み得る。
前記基板は、シリコン系基板又はシリコン基板であり得る。
前記基板構造体は、前記少なくとも1層のバッファ層上に、IV族物質又はIII−V族物質で形成される半導体層を更に備えることができる。
前記IV族物質は、Geを含み得る。
前記III−V族物質は、InGaAs、InP、InSb、InGaSb、GaSb及びInAsのうちの少なくとも一つを含み得る。
前記シード層は、0より大きく100nm以下の範囲の厚みを有し得る。
前記バッファ層は、0より大きく3μm以下の範囲の厚みを有し得る。
10、110、210、310、410 基板
20、220、320、420 シード層
21 第1層
22 第2層
23 第3層
24 第4層
31 第5層
32 第6層
30、230、330、430、431 バッファ層
40 半導体層
100、200 CMOS素子
120 第1シード層
121 第2シード層
130 第1バッファ層
131 第2バッファ層
140、240、347、441 (第1型トランジスタ用)第1層
141、241、355、455 (第2型トランジスタ用)第2層
150、250 第1絶縁層
151、251 第2絶縁層
152、252 第3絶縁層
340、440 第1型トランジスタ用物質層
348、418 第1パターン領域
350、434 絶縁層
353、453 第2パターン領域
360、460 第1ゲート絶縁層
363、463 第1スペーサ
370、470 第2ゲート絶縁層
373、473 第2スペーサ
500 ウェーハ
505 1つのセル
510 第1領域
520 第2領域
530 第3領域
D1、D2、D11、D12 ドレイン電極
G1、G2、G11、G12 ゲート電極
S1、S2、S11、S12 ソース電極
Claims (20)
- 基板と、
前記基板上に具備されてホウ素又はリンを含む物質で形成される少なくとも1層のシード層と、
前記シード層上の少なくとも1層のバッファ層と、を備えることを特徴とする基板構造体。 - 前記シード層は、B、BGe、BSiGe、P、PGe、PSiGe、B:Ge、B:SiGe、P:Ge、又はP:SiGeを含む少なくとも1層を含むことを特徴とする請求項1に記載の基板構造体。
- 前記バッファ層は、Ge、SiGe、又はGeSnを含む少なくとも1層を含むことを特徴とする請求項1に記載の基板構造体。
- 前記基板は、シリコン基板であることを特徴とする請求項1に記載の基板構造体。
- 前記少なくとも1層のバッファ層上に、IV族物質又はIII−V族物質で形成される半導体層を更に備えることを特徴とする請求項1に記載の基板構造体。
- 前記IV族物質は、Geを含むことを特徴とする請求項5に記載の基板構造体。
- 前記III−V族物質は、InGaAs、InP、InSb、InGaSb、GaSb及びInAsのうちの少なくとも一つを含むことを特徴とする請求項5に記載の基板構造体。
- 前記シード層は、0より大きく100nm以下の範囲の厚みを有することを特徴とする請求項1に記載の基板構造体。
- 前記バッファ層は、0より大きく3μm以下の範囲の厚みを有することを特徴とする請求項1に記載の基板構造体。
- 基板と、
前記基板上に具備されてホウ素又はリンを含む物質で形成される少なくとも1層のシード層と、
前記シード層上の少なくとも1層のバッファ層と、
前記バッファ層上の第1型トランジスタ用第1層と、
前記第1型トランジスタ用第1層と離隔されるように配置されて前記シード層上、バッファ層上、又は前記基板上に配置される第2型トランジスタ用第2層と、
前記第1型トランジスタ用第1層と前記第2型トランジスタ用第2層との間の絶縁層と、を備えることを特徴とするCMOS素子。 - 前記シード層は、B、BGe、BSiGe、P、PGe、PSiGe、B:Ge、B:SiGe、P:Ge、又はP:SiGeを含む少なくとも1層を含むことを特徴とする請求項10に記載のCMOS素子。
- 前記バッファ層は、Ge、SiGe、又はGeSnを含む少なくとも1層を含むことを特徴とする請求項10に記載のCMOS素子。
- 前記基板は、シリコン基板であることを特徴とする請求項10に記載のCMOS素子。
- 前記シード層は、0より大きく100nm以下の範囲の厚みを有することを特徴とする請求項10に記載のCMOS素子。
- 前記バッファ層は、0より大きく3μm以下の範囲の厚みを有することを特徴とする請求項10に記載のCMOS素子。
- 前記第1型トランジスタ用第1層は、InGaAs、InP、InSb、InGaSb、GaSb、及びInAsのうちの少なくとも一つを含むことを特徴とする請求項10に記載のCMOS素子。
- 前記前記第2型トランジスタ用第2層は、Geを含むことを特徴とする請求項10に記載のCMOS素子。
- 前記第1型トランジスタは、n型MOSFETであり、
前記第2型トランジスタは、p型MOSFETであることを特徴とする請求項10に記載のCMOS素子。 - 基板上に、ホウ素又はリンを含むシード層を形成する段階と、
前記シード層上にバッファ層を形成する段階と、
前記バッファ層上に第1型トランジスタ用物質層を積層する段階と、
前記第1型トランジスタ用物質層をエッチングして第1型トランジスタ用第1層及び第1パターンを形成する段階と、
前記第1型トランジスタ用第1層及び前記第1パターン上に絶縁層を形成する段階と、
前記絶縁層をエッチングして選択的成長のための第2パターンを形成する段階と、
前記第2パターンに第2型トランジスタ用第2層を選択的成長させる段階と、を有することを特徴とするCMOS素子の製造方法。 - 前記シード層は、B、BGe、BSiGe、P、PGe、PSiGe、B:Ge、B:SiGe、P:Ge、又はP:SiGeを含む少なくとも1層を含むことを特徴とする請求項19に記載のCMOS素子の製造方法。
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