JP6523504B2 - ファン−アウト半導体パッケージ - Google Patents
ファン−アウト半導体パッケージ Download PDFInfo
- Publication number
- JP6523504B2 JP6523504B2 JP2018029725A JP2018029725A JP6523504B2 JP 6523504 B2 JP6523504 B2 JP 6523504B2 JP 2018029725 A JP2018029725 A JP 2018029725A JP 2018029725 A JP2018029725 A JP 2018029725A JP 6523504 B2 JP6523504 B2 JP 6523504B2
- Authority
- JP
- Japan
- Prior art keywords
- core member
- fan
- semiconductor package
- disposed
- out semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 210
- 239000003566 sealing material Substances 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 30
- 238000002161 passivation Methods 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 18
- 239000008393 encapsulating agent Substances 0.000 claims description 7
- 230000000149 penetrating effect Effects 0.000 claims description 7
- 230000007423 decrease Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 184
- 239000011162 core material Substances 0.000 description 75
- 229920005989 resin Polymers 0.000 description 25
- 239000011347 resin Substances 0.000 description 25
- 239000010408 film Substances 0.000 description 23
- 238000007789 sealing Methods 0.000 description 19
- 239000000758 substrate Substances 0.000 description 18
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- 239000011810 insulating material Substances 0.000 description 14
- 239000004020 conductor Substances 0.000 description 11
- 239000011800 void material Substances 0.000 description 11
- 229910000679 solder Inorganic materials 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 239000003365 glass fiber Substances 0.000 description 9
- 239000011256 inorganic filler Substances 0.000 description 9
- 229910003475 inorganic filler Inorganic materials 0.000 description 9
- 239000004744 fabric Substances 0.000 description 8
- 239000011521 glass Substances 0.000 description 8
- 230000006870 function Effects 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 229920005992 thermoplastic resin Polymers 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 208000032365 Electromagnetic interference Diseases 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000740 bleeding effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000012778 molding material Substances 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910000859 α-Fe Inorganic materials 0.000 description 2
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 238000010344 co-firing Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/073—Apertured devices mounted on one or more rods passed through the apertures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02377—Fan-in arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
図1は電子機器システムの例を概略的に示すブロック図である。
一般に、半導体チップには、数多くの微細電気回路が集積されているが、それ自体が半導体完成品としての役割を果たすことはできず、外部からの物理的又は化学的衝撃により損傷する可能性がある。したがって、半導体チップ自体をそのまま用いるのではなく、半導体チップをパッケージングして、パッケージ状態で電子機器などに用いている。
図3はファン−イン半導体パッケージのパッケージング前後を概略的に示した断面図である。
図7はファン−アウト半導体パッケージの概略的な形態を示した断面図である。
1010 メインボード
1020 チップ関連部品
1030 ネットワーク関連部品
1040 その他の部品
1050 カメラ
1060 アンテナ
1070 ディスプレイ
1080 電池
1090 信号ライン
1100 スマートフォン
1101 本体
1110 メインボード
1120 部品
1130 カメラ
2200 ファン−イン半導体パッケージ
2220 半導体チップ
2221 本体
2222 接続パッド
2223 パッシベーション膜
2240 連結部材
2241 絶縁層
2242 再配線層
2243 ビア
2250 パッシベーション層
2260 アンダーバンプ金属層
2270 半田ボール
2280 アンダーフィル樹脂
2290 モールディング材
2500 メインボード
2301 インターポーザ基板
2302 インターポーザ基板
2100 ファン−アウト半導体パッケージ
2120 半導体チップ
2121 本体
2122 接続パッド
2140 連結部材
2141 絶縁層
2142 再配線層
2143 ビア
2150 パッシベーション層
2160 アンダーバンプ金属層
2170 半田ボール
100 半導体パッケージ
100A〜100C ファン−アウト半導体パッケージ
110 コア部材
111、111a、111b、111c 絶縁層
112a、112b、112c、112d 配線層
113、113a、113b、113c ビア
GA1、GA2 溝部
120 半導体チップ
121 本体
122 接続パッド
123 パッシベーション膜
130 封止材
140 連結部材
141 絶縁層
142 再配線層
143 ビア
150 パッシベーション層
151 開口部
160 アンダーバンプ金属層
170 電気接続構造体
Claims (22)
- 貫通孔を有するコア部材と、
前記貫通孔に配置され、接続パッドが配置された活性面、及び前記活性面の反対側に配置された非活性面を有する半導体チップと、
前記コア部材及び前記半導体チップの少なくとも一部を封止し、前記貫通孔の少なくとも一部を充填する封止材と、
前記コア部材及び前記半導体チップの活性面上に配置され、前記接続パッドと電気的に連結された再配線層を含む連結部材と、を含み、
前記コア部材の前記連結部材が配置された下側には、前記貫通孔の壁面から前記コア部材の外側面までを貫通する溝部が存在する、ファン−アウト半導体パッケージ。 - 前記封止材は前記溝部の少なくとも一部を充填する、請求項1に記載のファン−アウト半導体パッケージ。
- 前記溝部は、前記コア部材の下側の四隅にそれぞれ存在する第1〜第4溝部を含む、請求項1または2に記載のファン−アウト半導体パッケージ。
- 前記コア部材の外側部の下側には、前記コア部材の枠に沿って前記コア部材の下側を貫通する第5溝部が存在し、
前記第1〜第4溝部はそれぞれ、前記第5溝部と連結されている、請求項3に記載のファン−アウト半導体パッケージ。 - 前記コア部材の前記貫通孔はテーパー状を有する、請求項1から4のいずれか一項に記載のファン−アウト半導体パッケージ。
- 前記半導体チップは、前記活性面上に配置され、前記接続パッドの少なくとも一部を覆うパッシベーション膜を含み、
前記封止材は、前記パッシベーション膜と前記連結部材との間の空間の少なくとも一部を充填する、請求項1から5のいずれか一項に記載のファン−アウト半導体パッケージ。 - 前記コア部材は、前記連結部材と接する第1絶縁層と、前記連結部材と接し、前記第1絶縁層に埋め込まれた第1配線層と、前記第1絶縁層の前記第1配線層が埋め込まれた側の反対側上に配置された第2配線層と、を含み、
前記第1及び第2配線層はそれぞれ、前記接続パッドと電気的に連結されている、請求項1から6のいずれか一項に記載のファン−アウト半導体パッケージ。 - 前記コア部材は、前記第1絶縁層上に配置され、前記第2配線層を覆う第2絶縁層と、前記第2絶縁層上に配置された第3配線層と、をさらに含み、
前記第3配線層は、前記接続パッドと電気的に連結されている、請求項7に記載のファン−アウト半導体パッケージ。 - 前記溝部は前記第1絶縁層の下側に形成される、請求項8に記載のファン−アウト半導体パッケージ。
- 前記第1絶縁層の下面は前記第1配線層の下面と段差を有する、請求項8または9に記載のファン−アウト半導体パッケージ。
- 前記コア部材は、第1絶縁層と、前記第1絶縁層の両面に配置された第1配線層及び第2配線層と、を含み、
前記第1配線層及び第2配線層はそれぞれ、前記接続パッドと電気的に連結されている、請求項1から6のいずれか一項に記載のファン−アウト半導体パッケージ。 - 前記コア部材は、前記第1絶縁層上に配置され、前記第1配線層を覆う第2絶縁層と、前記第2絶縁層上に配置された第3配線層と、前記第1絶縁層上に配置され、前記第2配線層を覆う第3絶縁層と、前記第3絶縁層上に配置された第4配線層と、をさらに含み、
前記第3配線層及び第4配線層はそれぞれ、前記接続パッドと電気的に連結されている、請求項11に記載のファン−アウト半導体パッケージ。 - 前記溝部は前記第2絶縁層の下側に形成される、請求項12に記載のファン−アウト半導体パッケージ。
- 前記第1絶縁層は前記第2及び第3絶縁層よりも厚い、請求項12または13に記載のファン−アウト半導体パッケージ。
- 連結部材と、
前記連結部材上に配置された電子部品と、
前記連結部材上に配置されたコア部材であって、前記電子部品が配置される貫通孔を有し、前記連結部材と向かい合い、前記コア部材の下面に沿って前記貫通孔から前記コア部材の外面に向かう外側方向に延長されて形成された複数の溝部を含む、コア部材と、を含む、ファン−アウト半導体パッケージ。 - 前記コア部材は、前記連結部材と向かい合い、前記コア部材の下面の外側に沿って形成された周囲溝部をさらに含む、請求項15に記載のファン−アウト半導体パッケージ。
- 前記コア部材の前記貫通孔は、平面方向を基準に、前記連結部材と向かい合う前記コア部材の下側における下部領域が前記コア部材の前記下側の反対側の上側における上部領域よりも小さい、請求項15または16に記載のファン−アウト半導体パッケージ。
- 前記電子部品は、前記連結部材と向かい合い、複数の接続パッドを有する活性面を含み、
前記連結部材は、前記複数の接続パッドと電気的に連結された再配線層を含む、請求項15から17のいずれか一項に記載のファン−アウト半導体パッケージ。 - 上面及び下面を有し、再配線層、及び前記再配線層と電気的に連結され、前記下面から突出した電気接続構造体を含む連結部材と、
前記連結部材の上面上に配置され、下面に前記連結部材の前記再配線層と電気的に連結された複数の接続パッドが配置され、前記連結部材と向かい合う半導体チップと、
前記連結部材の上面上に配置されたコア部材であって、前記半導体チップが配置される貫通孔を有し、前記連結部材の前記再配線層と電気的に連結される配線層を含み、前記連結部材と向かい合い、前記貫通孔のそれぞれの内側コーナーから前記コア部材のそれぞれの外側コーナーに向かって外側方向に延長されて形成された第1〜第4溝部を含む、コア部材と、
前記半導体チップ及び前記コア部材上に配置され、前記半導体チップと前記コア部材との間の少なくとも一部を充填し、前記第1〜第4溝部のそれぞれの少なくとも一部を充填する封止材と、を含む、ファン−アウト半導体パッケージ。 - 前記コア部材は、前記連結部材と向かい合い、前記コア部材の外面に沿って延長され、前記第1〜第4溝部と連結される外側溝部をさらに含み、
前記封止材は、実質的に前記第1〜第4溝部を充填し、前記外側溝部の少なくとも一部を充填する、請求項19に記載のファン−アウト半導体パッケージ。 - 前記貫通孔は前記連結部材に向かう方向に面積が小さくなるテーパー状を有する、請求項20に記載のファン−アウト半導体パッケージ。
- 前記コア部材は複数の絶縁層を含み、
前記複数の絶縁層のうちいずれか一つは、他の絶縁層のそれぞれよりも厚さが厚く、前記他の絶縁層のそれぞれと異なる物質を含む、請求項19から21のいずれか一項に記載のファン−アウト半導体パッケージ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2017-0118705 | 2017-09-15 | ||
KR1020170118705A KR102380821B1 (ko) | 2017-09-15 | 2017-09-15 | 팬-아웃 반도체 패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2019054226A JP2019054226A (ja) | 2019-04-04 |
JP6523504B2 true JP6523504B2 (ja) | 2019-06-05 |
Family
ID=65721128
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018029725A Active JP6523504B2 (ja) | 2017-09-15 | 2018-02-22 | ファン−アウト半導体パッケージ |
Country Status (5)
Country | Link |
---|---|
US (2) | US10373887B2 (ja) |
JP (1) | JP6523504B2 (ja) |
KR (1) | KR102380821B1 (ja) |
CN (1) | CN109509726B (ja) |
TW (1) | TWI670807B (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102380821B1 (ko) * | 2017-09-15 | 2022-03-31 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
KR102551747B1 (ko) | 2018-09-13 | 2023-07-06 | 삼성전자주식회사 | 반도체 패키지 |
KR102570902B1 (ko) * | 2018-11-23 | 2023-08-25 | 삼성전자주식회사 | 반도체 패키지 |
KR102643424B1 (ko) * | 2019-12-13 | 2024-03-06 | 삼성전자주식회사 | 반도체 패키지 |
KR20210087751A (ko) * | 2020-01-03 | 2021-07-13 | 삼성전자주식회사 | 반도체 패키지 |
KR20210087752A (ko) * | 2020-01-03 | 2021-07-13 | 삼성전자주식회사 | 반도체 패키지 |
JP7465714B2 (ja) | 2020-04-30 | 2024-04-11 | 京セラ株式会社 | 半導体封止用エポキシ樹脂組成物及び半導体装置 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09162320A (ja) * | 1995-12-08 | 1997-06-20 | Shinko Electric Ind Co Ltd | 半導体パッケージおよび半導体装置 |
JPH11163229A (ja) * | 1997-11-26 | 1999-06-18 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2000124237A (ja) * | 1998-10-12 | 2000-04-28 | Matsushita Electronics Industry Corp | 半導体素子搭載用基板とそれを用いた樹脂封止型半導体装置およびその製造方法 |
JP2001007260A (ja) * | 1999-06-25 | 2001-01-12 | Nec Corp | 半導体装置及びその製造方法 |
KR100355796B1 (ko) | 1999-10-15 | 2002-10-19 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지용 리드프레임 및 이를 봉지하기 위한 금형 구조 |
US6607942B1 (en) * | 2001-07-26 | 2003-08-19 | Taiwan Semiconductor Manufacturing Company | Method of fabricating as grooved heat spreader for stress reduction in an IC package |
US7042071B2 (en) * | 2002-10-24 | 2006-05-09 | Matsushita Electric Industrial Co., Ltd. | Leadframe, plastic-encapsulated semiconductor device, and method for fabricating the same |
JP2006059992A (ja) * | 2004-08-19 | 2006-03-02 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板の製造方法 |
TWI355695B (en) | 2007-10-02 | 2012-01-01 | Advanced Semiconductor Eng | Flip chip package process |
EP2259668A4 (en) * | 2008-03-27 | 2011-12-14 | Ibiden Co Ltd | METHOD FOR PRODUCING A MULTILAYER CONDUCTOR PLATE |
JP5193898B2 (ja) * | 2009-02-12 | 2013-05-08 | 新光電気工業株式会社 | 半導体装置及び電子装置 |
US8138014B2 (en) * | 2010-01-29 | 2012-03-20 | Stats Chippac, Ltd. | Method of forming thin profile WLCSP with vertical interconnect over package footprint |
JP5826532B2 (ja) * | 2010-07-15 | 2015-12-02 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
JP5789431B2 (ja) | 2011-06-30 | 2015-10-07 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US20130249101A1 (en) * | 2012-03-23 | 2013-09-26 | Stats Chippac, Ltd. | Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units |
WO2013176426A1 (ko) * | 2012-05-25 | 2013-11-28 | 주식회사 네패스 | 반도체 패키지, 그 제조 방법 및 패키지 온 패키지 |
KR102076044B1 (ko) * | 2013-05-16 | 2020-02-11 | 삼성전자주식회사 | 반도체 패키지 장치 |
US9646955B2 (en) * | 2014-09-05 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages and methods of forming packages |
KR20170043427A (ko) * | 2015-10-13 | 2017-04-21 | 삼성전기주식회사 | 전자부품 패키지 및 그 제조방법 |
KR101933408B1 (ko) * | 2015-11-10 | 2018-12-28 | 삼성전기 주식회사 | 전자부품 패키지 및 이를 포함하는 전자기기 |
KR101681031B1 (ko) * | 2015-11-17 | 2016-12-01 | 주식회사 네패스 | 반도체 패키지 및 그 제조방법 |
KR102380821B1 (ko) * | 2017-09-15 | 2022-03-31 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
-
2017
- 2017-09-15 KR KR1020170118705A patent/KR102380821B1/ko active IP Right Grant
-
2018
- 2018-02-12 TW TW107104931A patent/TWI670807B/zh active
- 2018-02-13 US US15/895,604 patent/US10373887B2/en active Active
- 2018-02-22 JP JP2018029725A patent/JP6523504B2/ja active Active
- 2018-04-16 CN CN201810336638.0A patent/CN109509726B/zh active Active
-
2019
- 2019-07-24 US US16/521,255 patent/US10658260B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN109509726B (zh) | 2022-04-05 |
US20190088566A1 (en) | 2019-03-21 |
US10658260B2 (en) | 2020-05-19 |
US10373887B2 (en) | 2019-08-06 |
TWI670807B (zh) | 2019-09-01 |
KR102380821B1 (ko) | 2022-03-31 |
US20190348339A1 (en) | 2019-11-14 |
JP2019054226A (ja) | 2019-04-04 |
TW201916269A (zh) | 2019-04-16 |
KR20190030972A (ko) | 2019-03-25 |
CN109509726A (zh) | 2019-03-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10283439B2 (en) | Fan-out semiconductor package including electromagnetic interference shielding layer | |
US10475748B2 (en) | Fan-out semiconductor package | |
TWI645526B (zh) | 扇出型半導體裝置 | |
JP6523504B2 (ja) | ファン−アウト半導体パッケージ | |
US10504836B2 (en) | Fan-out semiconductor package | |
US10833041B2 (en) | Fan-out semiconductor package | |
CN109727930B (zh) | 扇出型半导体封装模块 | |
TW202023105A (zh) | 天線模組 | |
JP6568610B2 (ja) | ファン−アウト半導体パッケージ | |
TW201929106A (zh) | 扇出型半導體封裝以及包含該封裝的封裝堆疊 | |
JP2019033245A (ja) | 半導体パッケージ連結システム | |
JP6770031B2 (ja) | ファン−アウト半導体パッケージ | |
KR102145203B1 (ko) | 팬-아웃 반도체 패키지 | |
TW201813031A (zh) | 扇出型半導體封裝 | |
US10312195B2 (en) | Fan-out semiconductor package | |
US20200105694A1 (en) | Open pad structure and semiconductor package comprising the same | |
JP2019087731A (ja) | ファン−アウト半導体パッケージ | |
TW201926616A (zh) | 扇出型半導體封裝 | |
TWI685934B (zh) | 扇出型半導體封裝 | |
TWI667750B (zh) | 扇出型半導體封裝 | |
KR102595864B1 (ko) | 반도체 패키지 | |
KR102070085B1 (ko) | 반도체 패키지 기판의 휨 감소 방법 및 휨이 감소된 반도체 패키지 기판 | |
KR102589685B1 (ko) | 반도체 패키지 | |
KR20200134012A (ko) | 기판 구조체 및 이를 포함하는 반도체 패키지 | |
KR20200099806A (ko) | 반도체 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20190402 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20190425 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6523504 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: R3D03 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20190705 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |