JP6510174B2 - 半導体装置およびその作製方法 - Google Patents
半導体装置およびその作製方法 Download PDFInfo
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- JP6510174B2 JP6510174B2 JP2014034495A JP2014034495A JP6510174B2 JP 6510174 B2 JP6510174 B2 JP 6510174B2 JP 2014034495 A JP2014034495 A JP 2014034495A JP 2014034495 A JP2014034495 A JP 2014034495A JP 6510174 B2 JP6510174 B2 JP 6510174B2
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- Prior art keywords
- oxide semiconductor
- semiconductor layer
- transistor
- insulating film
- oxide
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Description
以下では、電界効果移動度が高く、信頼性が高いトランジスタについて説明する。
以下では、多層膜を有するトランジスタの構造および作製方法について説明する。
まず、トップゲートトップコンタクト型のトランジスタの一例について説明する。
以下では、トランジスタ構造(1)の作製方法の一例について説明する。
次に、トランジスタ構造(1)とは異なるトップゲートトップコンタクト型のトランジスタの一例について説明する。
以下では、トランジスタ構造(2)の作製方法の一例について説明する。
次に、ボトムゲートトップコンタクト型のトランジスタの一例について説明する。
以下では、トランジスタ構造(3)の作製方法の一例について説明する。
次に、トランジスタ構造(3)とは異なるボトムゲートトップコンタクト型のトランジスタの一例について説明する。
以下では、トランジスタ構造(4)の作製方法の一例について説明する。
以下では、上述したトランジスタを用いた応用製品について説明する。
上述したトランジスタは、さまざまな電子機器に搭載されるマイクロコンピュータに適用することができる。
図14は、上述したトランジスタを少なくとも一部に用いたCPUの具体的な構成を示すブロック図である。
本項では、上述したトランジスタを適用した表示装置について説明する。
まずはEL素子を用いた表示装置(EL表示装置ともいう。)について説明する。
次に、液晶素子を用いた表示装置(液晶表示装置ともいう。)について説明する。
図17(A)において、テレビジョン装置8000は、筐体8001に表示部8002が組み込まれており、表示部8002により映像を表示し、スピーカー部8003から音声を出力することが可能である。上述した表示装置を表示部8002に用いることが可能である。
102 下地絶縁膜
104 ゲート電極
106a 酸化物半導体層
106b 酸化物半導体層
106c 酸化物半導体層
112 ゲート絶縁膜
116a ソース電極
116b ドレイン電極
118 保護絶縁膜
200 基板
202 下地絶縁膜
204 ゲート電極
206a 酸化物半導体層
206b 酸化物半導体層
206c 酸化物半導体層
212 ゲート絶縁膜
216a ソース電極
216b ドレイン電極
218 保護絶縁膜
234 導電膜
236 酸化物半導体層
242 絶縁膜
300 基板
304 ゲート電極
306a 酸化物半導体層
306b 酸化物半導体層
306c 酸化物半導体層
312 ゲート絶縁膜
316a ソース電極
316b ドレイン電極
318 保護絶縁膜
318a 酸化シリコン層
318b 酸化シリコン層
318c 窒化シリコン層
400 基板
404 ゲート電極
406a 酸化物半導体層
406b 酸化物半導体層
406c 酸化物半導体層
412 ゲート絶縁膜
416a ソース電極
416b ドレイン電極
418 保護絶縁膜
445 絶縁膜
449 配線
451 半導体基板
453 素子分離領域
456 配線
457 ゲート絶縁膜
459 ゲート電極
460 半導体膜
461a 不純物領域
461b 不純物領域
465 絶縁膜
466c 電極
467 絶縁膜
469a コンタクトプラグ
469b コンタクトプラグ
470 絶縁膜
471 絶縁膜
472 絶縁膜
473a 配線
473b 配線
474 電極
475 絶縁膜
500 マイクロコンピュータ
501 直流電源
502 バスライン
503 パワーゲートコントローラ
504 パワーゲート
505 CPU
506 揮発性記憶部
507 不揮発性記憶部
508 インターフェース
509 検出部
511 光センサ
512 アンプ
513 ADコンバータ
514 光電変換素子
516 トランジスタ
517 トランジスタ
518 トランジスタ
519 トランジスタ
530 発光素子
700 基板
719 発光素子
720 絶縁膜
721 絶縁膜
731 端子
732 FPC
733a 配線
734 シール材
735 駆動回路
736 駆動回路
737 画素
741 トランジスタ
742 キャパシタ
743 スイッチ素子
744 信号線
750 画素
751 トランジスタ
752 キャパシタ
753 液晶素子
754 走査線
755 信号線
781 電極
782 発光層
783 電極
784 隔壁
791 電極
792 絶縁膜
793 液晶層
794 絶縁膜
795 スペーサ
796 電極
797 基板
1141 スイッチング素子
1142 メモリセル
1143 メモリセル群
1189 ROMインターフェース
1190 基板
1191 ALU
1192 ALUコントローラ
1193 インストラクションデコーダ
1194 インタラプトコントローラ
1195 タイミングコントローラ
1196 レジスタ
1197 レジスタコントローラ
1198 バスインターフェース
1199 ROM
8000 テレビジョン装置
8001 筐体
8002 表示部
8003 スピーカー部
8100 警報装置
8101 マイクロコンピュータ
8200 室内機
8201 筐体
8202 送風口
8203 CPU
8204 室外機
8300 電気冷凍冷蔵庫
8301 筐体
8302 冷蔵室用扉
8303 冷凍室用扉
8304 CPU
9700 電気自動車
9701 二次電池
9702 制御回路
9703 駆動装置
9704 処理装置
Claims (4)
- 第1の酸化物半導体層と、
前記第1の酸化物半導体層上の第2の酸化物半導体層と、
前記第2の酸化物半導体層上に接する領域を有する、ソース電極およびドレイン電極と、
前記ソース電極上に接する領域、前記ドレイン電極上に接する領域、および前記第2の酸化物半導体層上に接する領域を有する第3の酸化物半導体層と、
前記第3の酸化物半導体層上のゲート絶縁膜と、
前記ゲート絶縁膜上のゲート電極と、を有し、
前記第2の酸化物半導体層は、前記第1の酸化物半導体層および前記第3の酸化物半導体層よりも、酸素欠損量が多く、
前記第1の酸化物半導体層は、前記第2の酸化物半導体層より厚く、
前記第2の酸化物半導体層は、前記第3の酸化物半導体層より厚いことを特徴とする半導体装置。 - 請求項1において、
前記ゲート電極は、チャネル幅方向において、前記第1の酸化物半導体層乃至前記第3の酸化物半導体層の端部を越えて延在し、
前記ソース電極及び前記ドレイン電極はそれぞれ、チャネル長方向において、前記第1の酸化物半導体層乃至前記第3の酸化物半導体層の端部を越えて延在し、
前記ソース電極及び前記ドレイン電極はそれぞれ、チャネル幅方向において、前記第1の酸化物半導体層乃至前記第3の酸化物半導体層の端部を越えて延在し、
前記第3の酸化物半導体層は、前記チャネル幅方向において、前記第1の酸化物半導体層の側面と接する領域と、前記第2の酸化物半導体層の側面と接する領域とを有することを特徴とする半導体装置。 - 第1の酸化物半導体層を形成し、
前記第1の酸化物半導体層上に第2の酸化物半導体層を形成し、
前記第2の酸化物半導体層上にソース電極およびドレイン電極を形成し、
前記ソース電極上に接する領域、前記ドレイン電極上に接する領域、および前記第2の酸化物半導体層上に接する領域を有する第3の酸化物半導体層を形成し、
前記第3の酸化物半導体層上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上にゲート電極を形成する半導体装置の作製方法であって、
前記第1の酸化物半導体層および前記第3の酸化物半導体層は、スパッタリング法により、酸素を含む雰囲気で形成し、
前記第2の酸化物半導体層は、スパッタリング法により、酸素を含まない雰囲気で形成し、
前記第1の酸化物半導体層は、前記第2の酸化物半導体層より厚く、
前記第2の酸化物半導体層は、前記第3の酸化物半導体層より厚いことを特徴とする半導体装置の作製方法。 - 請求項3において、
前記第1の酸化物半導体層乃至前記第3の酸化物半導体層を、同一のターゲットを用いて形成することを特徴とする半導体装置の作製方法。
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