JP6505726B2 - 半導体チップを相互接続するためのインタポーザを提供するための方法及び装置 - Google Patents

半導体チップを相互接続するためのインタポーザを提供するための方法及び装置 Download PDF

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JP6505726B2
JP6505726B2 JP2016549259A JP2016549259A JP6505726B2 JP 6505726 B2 JP6505726 B2 JP 6505726B2 JP 2016549259 A JP2016549259 A JP 2016549259A JP 2016549259 A JP2016549259 A JP 2016549259A JP 6505726 B2 JP6505726 B2 JP 6505726B2
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glass substrate
ppm
interposer
cte2
cte1
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JP2017505998A5 (enExample
JP2017505998A (ja
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チャンドラ チャパラヤ，サティシュ
チャンドラ チャパラヤ，サティシュ
クリストファー ポラード，スコット
クリストファー ポラード，スコット
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Corning Inc
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Corning Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/692—Ceramics or glasses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/823—Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Joining Of Glass To Other Materials (AREA)
JP2016549259A 2014-01-31 2015-01-29 半導体チップを相互接続するためのインタポーザを提供するための方法及び装置 Expired - Fee Related JP6505726B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201461934366P 2014-01-31 2014-01-31
US61/934,366 2014-01-31
PCT/US2015/013405 WO2015116749A1 (en) 2014-01-31 2015-01-29 Methods and apparatus for providing an interposer for interconnecting semiconductor chips

Publications (3)

Publication Number Publication Date
JP2017505998A JP2017505998A (ja) 2017-02-23
JP2017505998A5 JP2017505998A5 (enExample) 2018-03-22
JP6505726B2 true JP6505726B2 (ja) 2019-04-24

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JP2016549259A Expired - Fee Related JP6505726B2 (ja) 2014-01-31 2015-01-29 半導体チップを相互接続するためのインタポーザを提供するための方法及び装置

Country Status (7)

Country Link
US (2) US9472479B2 (enExample)
EP (1) EP3100300A1 (enExample)
JP (1) JP6505726B2 (enExample)
KR (1) KR20160114710A (enExample)
CN (1) CN106165088B (enExample)
TW (1) TWI653713B (enExample)
WO (1) WO2015116749A1 (enExample)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9472479B2 (en) * 2014-01-31 2016-10-18 Corning Incorporated Methods and apparatus for providing an interposer for interconnecting semiconductor chips
KR101681410B1 (ko) * 2015-04-20 2016-11-30 삼성전기주식회사 커패시터 부품
US9780044B2 (en) * 2015-04-23 2017-10-03 Palo Alto Research Center Incorporated Transient electronic device with ion-exchanged glass treated interposer
JPWO2017010063A1 (ja) * 2015-07-10 2018-07-12 凸版印刷株式会社 配線基板及びその製造方法
US20170179066A1 (en) * 2015-12-18 2017-06-22 Russell S. Aoki Bulk solder removal on processor packaging
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US10892219B2 (en) 2016-07-01 2021-01-12 Intel Corporation Molded embedded bridge for enhanced EMIB applications
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
TWI782939B (zh) 2016-12-29 2022-11-11 美商英帆薩斯邦德科技有限公司 具有整合式被動構件的接合結構
US20180190583A1 (en) * 2016-12-29 2018-07-05 Invensas Bonding Technologies, Inc. Bonded structures with integrated passive component
WO2018169968A1 (en) 2017-03-16 2018-09-20 Invensas Corporation Direct-bonded led arrays and applications
US10784191B2 (en) 2017-03-31 2020-09-22 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
DE202018006778U1 (de) 2017-06-15 2023-01-19 Chiaro Technology Limited Brustpumpensystem
CN111051256A (zh) * 2017-07-31 2020-04-21 康宁股份有限公司 具有非玻璃芯体和玻璃包封物的层压制品及其方法
TWI653919B (zh) * 2017-08-10 2019-03-11 晶巧股份有限公司 高散熱等線距堆疊晶片封裝結構和方法
US10622311B2 (en) 2017-08-10 2020-04-14 International Business Machines Corporation High-density interconnecting adhesive tape
US11011503B2 (en) 2017-12-15 2021-05-18 Invensas Bonding Technologies, Inc. Direct-bonded optoelectronic interconnect for high-density integrated photonics
CA3086376A1 (en) * 2017-12-21 2019-06-27 Corning Incorporated Multi-layer insulated glass unit comprising a low cte glass layer
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11256004B2 (en) 2018-03-20 2022-02-22 Invensas Bonding Technologies, Inc. Direct-bonded lamination for improved image clarity in optical devices
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US11114308B2 (en) 2018-09-25 2021-09-07 International Business Machines Corporation Controlling of height of high-density interconnection structure on substrate
US11195789B2 (en) * 2018-11-30 2021-12-07 International Business Machines Corporation Integrated circuit module with a structurally balanced package using a bottom side interposer
US10707169B1 (en) 2018-12-28 2020-07-07 Intel Corporation Ceramic interposers for on-die interconnects
US11148935B2 (en) 2019-02-22 2021-10-19 Menlo Microsystems, Inc. Full symmetric multi-throw switch using conformal pinched through via
KR102573196B1 (ko) 2019-03-07 2023-08-30 앱솔릭스 인코포레이티드 패키징 기판 및 이를 포함하는 반도체 장치
CN113261092B (zh) 2019-03-07 2024-09-10 爱玻索立克公司 封装基板及包括其的半导体装置
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
JP7228697B2 (ja) 2019-03-12 2023-02-24 アブソリックス インコーポレイテッド パッケージング基板及びこれを含む半導体装置
US12198994B2 (en) 2019-03-12 2025-01-14 Absolics Inc. Packaging substrate and method for manufacturing same
EP3916772A4 (en) 2019-03-12 2023-04-05 Absolics Inc. PACKAGING SUBSTRATE AND SEMICONDUCTOR DEVICE WITH IT
US11981501B2 (en) 2019-03-12 2024-05-14 Absolics Inc. Loading cassette for substrate including glass and substrate loading method to which same is applied
EP3910667B1 (en) 2019-03-29 2025-08-13 Absolics Inc. Packaging glass substrate for semiconductor, packaging substrate for semiconductor, and semiconductor device
KR102600154B1 (ko) 2019-06-12 2023-11-07 삼성전자주식회사 반도체 패키지
JP7104245B2 (ja) 2019-08-23 2022-07-20 アブソリックス インコーポレイテッド パッケージング基板及びこれを含む半導体装置
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
GB202004395D0 (en) 2020-03-26 2020-05-13 Chiaro Technology Ltd Lima
KR20230107620A (ko) * 2020-11-16 2023-07-17 코닝 인코포레이티드 관통 유리 비아가 있는 3d 인터포저 - 구리와 유리 표면 사이의 접착력을 높이는 방법 및 그 물품
KR102948403B1 (ko) 2021-05-03 2026-04-02 삼성전자주식회사 반도체 패키지
JP2024532146A (ja) * 2021-08-18 2024-09-05 テスラ，インコーポレイテッド 異種多層構造体
TWI896903B (zh) 2021-08-30 2025-09-11 美商愛玻索立克公司 封裝基板、半導體封裝、封裝基板製備方法以及半導體封裝製備方法
KR20240090512A (ko) 2021-10-19 2024-06-21 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 멀티-다이 스태킹에서의 적층된 인덕터
US12476176B2 (en) * 2022-03-29 2025-11-18 Intel Corporation Glass core substrate printed circuit board for warpage reduction
GB2622196A (en) 2022-08-31 2024-03-13 Chiaro Technology Ltd Measurement system
GB2622570B (en) 2022-08-31 2024-12-11 Chiaro Technology Ltd Breast pump
TWI834336B (zh) * 2022-10-12 2024-03-01 欣興電子股份有限公司 封裝結構及其製作方法
CN115677213B (zh) * 2022-11-16 2024-07-26 湖南兆湘光电高端装备研究院有限公司 化学强化层压玻璃制品及其制备方法
KR102738263B1 (ko) 2023-03-14 2024-12-05 주식회사 아크 수동 소자가 내장된 ｍｅｍｓ구조의 기판 및 반도체 패키지
WO2026034489A1 (ja) * 2024-08-05 2026-02-12 大日本印刷株式会社 貫通電極基板、素子付き貫通電極基板、接続基板および半導体装置
CN121443101B (zh) * 2025-12-30 2026-04-10 厦门云天半导体科技有限公司 玻璃中介层堆叠基板及半导体封装结构

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4221047A (en) * 1979-03-23 1980-09-09 International Business Machines Corporation Multilayered glass-ceramic substrate for mounting of semiconductor device
US5209798A (en) * 1991-11-22 1993-05-11 Grunman Aerospace Corporation Method of forming a precisely spaced stack of substrate layers
US6399892B1 (en) * 2000-09-19 2002-06-04 International Business Machines Corporation CTE compensated chip interposer
JP2003342064A (ja) * 2002-05-28 2003-12-03 Kyocera Corp ガラスセラミック焼結体および多層配線基板
US7226654B2 (en) * 2003-07-29 2007-06-05 Kyocera Corporation Laminated wiring board and its mounting structure
JP2005050882A (ja) * 2003-07-29 2005-02-24 Kyocera Corp 積層型配線基板および電気装置並びにその実装構造
US7221050B2 (en) * 2004-09-02 2007-05-22 Intel Corporation Substrate having a functionally gradient coefficient of thermal expansion
US8780576B2 (en) * 2011-09-14 2014-07-15 Invensas Corporation Low CTE interposer
US8865507B2 (en) * 2011-09-16 2014-10-21 Sionyx, Inc. Integrated visible and infrared imager devices and associated methods
US9472479B2 (en) * 2014-01-31 2016-10-18 Corning Incorporated Methods and apparatus for providing an interposer for interconnecting semiconductor chips

Also Published As

Publication number Publication date
TWI653713B (zh) 2019-03-11
KR20160114710A (ko) 2016-10-05
US9917045B2 (en) 2018-03-13
WO2015116749A1 (en) 2015-08-06
CN106165088B (zh) 2019-03-01
US9472479B2 (en) 2016-10-18
JP2017505998A (ja) 2017-02-23
US20150221571A1 (en) 2015-08-06
TW201535622A (zh) 2015-09-16
US20170025341A1 (en) 2017-01-26
EP3100300A1 (en) 2016-12-07
CN106165088A (zh) 2016-11-23

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