JP2017505998A5 - - Google Patents

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Publication number
JP2017505998A5
JP2017505998A5 JP2016549259A JP2016549259A JP2017505998A5 JP 2017505998 A5 JP2017505998 A5 JP 2017505998A5 JP 2016549259 A JP2016549259 A JP 2016549259A JP 2016549259 A JP2016549259 A JP 2016549259A JP 2017505998 A5 JP2017505998 A5 JP 2017505998A5
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JP
Japan
Prior art keywords
glass substrate
ppm
cte2
cte1
main surface
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JP2016549259A
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English (en)
Japanese (ja)
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JP2017505998A (ja
JP6505726B2 (ja
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Priority claimed from PCT/US2015/013405 external-priority patent/WO2015116749A1/en
Publication of JP2017505998A publication Critical patent/JP2017505998A/ja
Publication of JP2017505998A5 publication Critical patent/JP2017505998A5/ja
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Publication of JP6505726B2 publication Critical patent/JP6505726B2/ja
Expired - Fee Related legal-status Critical Current
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JP2016549259A 2014-01-31 2015-01-29 半導体チップを相互接続するためのインタポーザを提供するための方法及び装置 Expired - Fee Related JP6505726B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201461934366P 2014-01-31 2014-01-31
US61/934,366 2014-01-31
PCT/US2015/013405 WO2015116749A1 (en) 2014-01-31 2015-01-29 Methods and apparatus for providing an interposer for interconnecting semiconductor chips

Publications (3)

Publication Number Publication Date
JP2017505998A JP2017505998A (ja) 2017-02-23
JP2017505998A5 true JP2017505998A5 (enExample) 2018-03-22
JP6505726B2 JP6505726B2 (ja) 2019-04-24

Family

ID=52463211

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016549259A Expired - Fee Related JP6505726B2 (ja) 2014-01-31 2015-01-29 半導体チップを相互接続するためのインタポーザを提供するための方法及び装置

Country Status (7)

Country Link
US (2) US9472479B2 (enExample)
EP (1) EP3100300A1 (enExample)
JP (1) JP6505726B2 (enExample)
KR (1) KR20160114710A (enExample)
CN (1) CN106165088B (enExample)
TW (1) TWI653713B (enExample)
WO (1) WO2015116749A1 (enExample)

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US11256004B2 (en) 2018-03-20 2022-02-22 Invensas Bonding Technologies, Inc. Direct-bonded lamination for improved image clarity in optical devices
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US11114308B2 (en) 2018-09-25 2021-09-07 International Business Machines Corporation Controlling of height of high-density interconnection structure on substrate
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US10707169B1 (en) * 2018-12-28 2020-07-07 Intel Corporation Ceramic interposers for on-die interconnects
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US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
JP7228697B2 (ja) 2019-03-12 2023-02-24 アブソリックス インコーポレイテッド パッケージング基板及びこれを含む半導体装置
EP3916772A4 (en) 2019-03-12 2023-04-05 Absolics Inc. PACKAGING SUBSTRATE AND SEMICONDUCTOR DEVICE WITH IT
CN113424304B (zh) 2019-03-12 2024-04-12 爱玻索立克公司 装载盒及对象基板的装载方法
WO2020185023A1 (ko) 2019-03-12 2020-09-17 에스케이씨 주식회사 패키징 기판 및 이의 제조방법
KR102515304B1 (ko) 2019-03-29 2023-03-29 앱솔릭스 인코포레이티드 반도체용 패키징 유리기판, 반도체용 패키징 기판 및 반도체 장치
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KR20220089715A (ko) 2019-08-23 2022-06-28 앱솔릭스 인코포레이티드 패키징 기판 및 이를 포함하는 반도체 장치
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
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KR20220150137A (ko) 2021-05-03 2022-11-10 삼성전자주식회사 반도체 패키지
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