TWI621230B - 用來控制積體電路封裝扭曲的可移除式基板 - Google Patents

用來控制積體電路封裝扭曲的可移除式基板 Download PDF

Info

Publication number
TWI621230B
TWI621230B TW105118763A TW105118763A TWI621230B TW I621230 B TWI621230 B TW I621230B TW 105118763 A TW105118763 A TW 105118763A TW 105118763 A TW105118763 A TW 105118763A TW I621230 B TWI621230 B TW I621230B
Authority
TW
Taiwan
Prior art keywords
substrate
integrated circuit
package
die
circuit die
Prior art date
Application number
TW105118763A
Other languages
English (en)
Other versions
TW201705414A (zh
Inventor
澤圭 姜
約瑟夫 米納卡佩利
Original Assignee
輝達公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 輝達公司 filed Critical 輝達公司
Publication of TW201705414A publication Critical patent/TW201705414A/zh
Application granted granted Critical
Publication of TWI621230B publication Critical patent/TWI621230B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3675Cooling facilitated by shape of device characterised by the shape of the housing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0271Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83417Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/83424Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92222Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92225Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06589Thermal management, e.g. cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00015Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

本發明的一個具體實施例揭示一種用來封裝一積體電路晶粒之技術,本技術包含透過一第一複數個焊錫凸塊結構,將該積體電路晶粒的一第一表面貼合至一第一基板,並且將一第二基板貼合至該積體電路晶粒的一第二表面。該技術進一步包含透過一第二複數個焊錫凸塊結構,將該第一基板貼合至一第三基板,並且在將該第一基板貼合至該第三基板之後,從該積體電路晶粒的該第二表面移除該第二基板。該技術進一步包含在該積體電路晶粒的該第二表面上放置一散熱器。

Description

用來控制積體電路封裝扭曲的可移除式基板
本發明的具體實施例一般係關於積體電路製造與封裝,尤其係關於用來控制積體電路封裝扭曲的可移除式基板。
積體電路(IC,Integrated circuit)製造為多步驟程序,包含像是製圖、沈積、蝕刻以及金屬化這些處理。通常在最終處理步驟內,結果IC晶粒分離並封裝。IC封裝具有許多用途,包含提供與該晶粒的電介面、提供可將熱量從晶粒移除的熱媒介,及/或提供晶粒在後續使用與處理期間的機械保護。
一種IC封裝技術稱為「覆晶」封裝,在覆晶封裝當中,在金屬化處理完成之後,焊錫凸塊結構(例如焊球、墊等等)都沈積在該晶粒上,並且該晶粒與該晶圓分離(例如透過分割、切割等等)。然後,將該晶粒翻轉並定位在一基板上,如此讓焊錫凸塊對準該基板上形成的電連接。熱量會透過焊錫回流過程而重複熔化焊錫凸塊,並且將晶粒附接至該基板。該晶粒/基板組合可進一步填滿不導電黏著劑,強化晶粒與基板之間的機械連接。
IC製造技術能夠生產具有提高電晶體密度的較大型晶粒,因此IC封裝技術會遭遇到要提供可支援必要電連接數量的封裝之挑戰。尤其是,隨著晶粒尺寸以及至該晶粒的電連接數量提高,該封裝的尺寸通常會增加。進一步,隨著封裝尺寸增加,該晶粒與封裝材料的熱屬性變成更重要的因素。
該晶粒與封裝材料的一個相關熱屬性為熱膨脹係數(CTE,coefficient of thermal expansion)。例如在覆晶封裝中,在焊錫回流處理期間, 該晶粒在溫度升高之下附接至該基板。在冷卻時,該晶粒的CTE與該基板的CTE間之不匹配會導致該基板扭曲,因此降低該IC封裝的平整性,並且避免形成與該IC封裝的電連接。此外,該IC封裝的扭曲通常會讓該晶粒與該基板之間的提供的電連接退化,因此經歷顯著扭曲的IC封裝通常會因為超出規格需求而拋棄。
為了降低該IC封裝的扭曲,某些傳統封裝技術將一基板永久貼合(通稱為「蓋子」)至該IC封裝,例如:在許多技術中,厚度小於1公釐的蓋子貼合在該IC封裝內含的一或多個IC晶粒頂端上。然後在該蓋子的頂端上放置一散熱器,用來發散該(等)IC晶粒操作期間所產生的熱量。
此技術的一項缺點為該蓋子將該(等)IC晶粒與該散熱器隔開,如此降低透過該散熱器從該IC封裝移除熱量的速率。因此,雖然將該蓋子貼合至該IC封裝會降低該IC封裝的扭曲程度,不過該蓋子會導致該(等)IC晶粒過熱及/或降低該(等)IC晶粒的總體效能。
如先前所例示,應該使用能夠更有效率降低IC封裝扭曲程度的技術。
本發明的一個具體實施例公佈一種用來封裝一積體電路晶粒之方法,本方法包含透過一第一複數個焊錫凸塊結構,將該積體電路晶粒的一第一表面貼合至一第一基板;以及將一第二基板貼合至該積體電路晶粒的一第二表面。該方法進一步包含透過一第二複數個焊錫凸塊結構,將該第一基板貼合至一第三基板;以及將該第一基板貼合至該第三基板之後,從該積體電路晶粒的該第二表面移除該第二基板。該方法進一步包含在該積體電路晶粒的該第二表面上放置一散熱器。
本說明書所說明該等技術的至少一項優點為降低該IC封裝的扭曲量,在該IC封裝與該封裝要貼合的一電路板之間可形成更可靠的電連接。進一步,本說明書所說明的該等技術減少該IC晶粒與該散熱器之間的熱介面數量,並且可讓該散熱器只透過薄的熱介面材料層就可接合至該IC晶粒。因此,透過該散熱器改善該IC封裝的冷卻。
100‧‧‧傳統積體電路封裝
110‧‧‧IC晶粒
120‧‧‧基板
130‧‧‧第一複數個焊球
140‧‧‧第二複數個焊球
150‧‧‧共平面性
160‧‧‧坐落平面
200‧‧‧蓋子
205‧‧‧第一介面
206‧‧‧第二介面
215‧‧‧堅硬結構
235‧‧‧散熱器
300‧‧‧IC封裝
310‧‧‧IC晶粒
312‧‧‧表面
314‧‧‧熱介面材料
315‧‧‧堅硬結構
320‧‧‧基板
325‧‧‧電路板
330‧‧‧第一複數個焊錫凸塊結構
335‧‧‧散熱器
340‧‧‧第二複數個焊錫凸塊結構
350‧‧‧剛性基板
355‧‧‧表面
如此上面簡單彙總可詳細了解本發明上述特色的方式,本發明的更特定說明則參照具體實施例,某些具體實施例說明於附圖內。不過應注意,附圖只說明本發明的典型具體實施例,因此並不對發明領域產生限制,本發明承認其他等效具體實施例。
第一A圖和第一B圖例示具有傳統組態的積體電路(IC)封裝之示意圖;第二A圖和第二B圖例示一蓋子貼合至第一B圖中該IC封裝的一上表面之示意圖;第三A圖至第三F圖例示根據本發明的許多具體實施例,暫時將一剛性基板接合至一積體電路(IC)封裝,來降低該IC封裝扭曲量之技術示意圖;以及第四圖為根據本發明許多具體實施例,用於封裝一積體電路晶粒之方法步驟流程圖。
在以下描述中,揭示許多特定細節以對本發明具體實施例有更徹底之理解。但是,精通技術人士應該了解,在無一或多個該等特定細節之下還是可實施本發明具體實施例。
第一A圖和第一B圖例示具有傳統組態的積體電路(IC)封裝100之示意圖。傳統IC封裝100包含一IC晶粒110、一基板120、一第一複數個焊球130以及一第二複數個焊球140。第一複數個焊球130在機械與電氣上將IC晶粒110接合至基板120,並且提供IC晶粒110與基板120之間的電連接。第二複數個焊球140在機械與電氣上將傳統IC封裝100接合至一電路板(未顯示),並且提供傳統IC封裝100與該電路板之間的電連接。
如第一A圖內所示,將IC晶粒110貼合至基板120之前,第二複數個焊球140大體上共平面。在貼合期間,第一複數個焊球130與基板120上所形成的電連接對齊並接觸。然後將IC晶粒110以及基板120加熱至熟悉溫度,將焊球130熔化,並且在機械與電氣方面將IC晶粒110 接合至基板120。
將IC晶粒110貼合至基板120之後,傳統IC封裝100冷卻至室溫(例如大約23℃)。然而如第一B圖內所示,由於IC晶粒110的熱膨脹係數(CTE)與基板120的CTE之間不匹配,當傳統IC封裝100冷卻時基板120及/或IC晶粒110會扭曲。結果,貼合至基板120底部表面的第二複數個焊球1405之共平面性150降低。
共平面性為用來說明物體位於相同平面內的程度之用詞。當該用詞用在IC封裝領域內,共平面性可定義為該最高焊錫凸塊結構的高度與坐落平面160的高度間之差異。例如第一B圖內所示,利用中央焊球140的高度與最右與最左焊球140所在坐落平面160的高度間之差異,來決定傳統IC封裝100的共平面性150。當焊球在坐落平面160之上的高度增加,代表共平面性降低。
共平面性降低可避免一或多個焊錫凸塊結構與一基板或其上要固接一IC封裝的電路板形成機械及/或電氣適當連接。再者,因為IC封裝共平面性通常需要滿足特定需求,以便確定與其他裝置組件正確的機械與電氣連接性,共平面性顯著降低會降低IC封裝組合產量。
第二A圖和第二B圖例示一蓋子200貼合至第一B圖中IC封裝100的一上表面之示意圖。在傳統封裝技術中,利用將一蓋子200永久貼合至該IC封裝的表面,可消弭IC封裝共平面性內之變化(例如由於CTE不匹配)。例如:具有厚度小於1公釐的蓋子200通常貼合至一或多個IC晶粒110及/或一堅硬結構215,以便提供額外剛性並降低IC封裝100的扭曲量。然後在蓋子200的頂端上放置一散熱器235,用來發散IC晶粒110操作期間所產生的熱量。
雖然蓋子200消弭IC封裝100的扭曲,不過蓋子200也會作為一分隔物,降低熱量從IC晶粒110傳輸至散熱器235的速率。再者,在IC晶粒110與散熱器235之間貼合蓋子200會產生兩個不同的熱介面-IC晶粒110與蓋子200之間的一第一介面205以及蓋子200與散熱器235之間的一第二介面206。一般而言,熱量必須傳輸通過的熱介面數量增加,會降低熱量從IC晶粒110透若散熱器235移除之速率。
為了解決傳統封裝技術的這些與其他缺陷,在許多具體實施例內,一剛性基板暫時連結至該IC封裝,以降低該封裝的扭曲量並改善該等焊錫凸塊結構連結至該基板的共平面性。然後,在該剛性基板已連結至該IC封裝時,該IC封裝貼合至一電路板(例如一主機板)或其他種基板。在該IC封裝已貼合至該電路板或其他基板之後,從該IC封裝移除該剛性基板,並且將一散熱器放置在該IC封裝內含的該(等)IC晶粒上。
這優點在於,暫時將一剛性基板連結至該IC封裝來降低該IC封裝的扭曲量,可使在該IC封裝與該IC封裝要貼合的一電路板或其他基板之間可形成更可靠的電連接。進一步,在該IC封裝貼合至該電路板之後可讓該剛性基板從該IC封裝移除,如此該散熱器只透過薄的熱介面材料層連結至該(等)IC晶粒。因此,可改善該IC封裝的冷卻。底下結合第三A圖至第四圖,更詳細說明這種IC封裝處理技術。
第三A圖至第三F圖例示根據本發明的許多具體實施例,暫時將一剛性基板350接合至一積體電路(IC)封裝300,來降低該IC封裝扭曲量之技術示意圖。如所示,IC封裝300包含一IC晶粒310、一基板320、一第一複數個焊錫凸塊結構330以及一第二複數個焊錫凸塊結構340。
如第三A圖以及第三B圖內所示,利用將第一複數個焊錫凸塊結構330與基板320對齊,並將IC晶粒310下降到基板320上,而將IC晶粒310貼合至基板320。然後將IC晶粒310以及基板320加熱至相似的溫度(例如焊錫回流溫度),將焊錫凸塊結構330熔化,並且在機械與電氣方面將IC晶粒310接合至基板320。將IC晶粒310貼合至基板板320之後,IC封裝300冷卻至室溫,導致基板320及/或IC晶粒310扭曲(例如由於CTE不匹配),如第三B圖內所示。
為了在將IC封裝300接合至一電路板之前,減少基板320及/或IC晶粒310的扭曲量,一剛性基板350暫時連結至IC封裝300的一表面312,如第三C圖內所示。在某些具體實施例內,使用一暫時黏著劑,將剛性基板350接合至位於IC封裝300內的一堅硬結構315之一表面355,以及接合至IC晶粒310本身的表面312。例如:剛性基板350可接合至位於IC晶粒310周邊四周的一硬環。在其他具體實施例內,剛性基板350接 合至堅硬結構315或IC封裝300內含的一或多個IC晶粒310。仍舊在其他具體實施例內,剛性基板350透過任何其他技術可行的方式,暫時接合至IC封裝300的一或多個組件,以降低IC封裝300的扭曲量。
如第三D圖內所示,當剛性基板350已接合至IC封裝300時,利用將IC晶粒310及/或基板320加熱至第二複數個焊錫凸塊結構340的熔點,而將IC封裝300貼合至一電路板325(或其他種基板)。然後讓IC封裝300冷卻(例如冷卻至室溫),並且從IC封裝300的表面移除剛性基板350,如第三E圖內所示。此外,在移除剛性基板350之後,選擇性清潔IC封裝300的表面312(例如IC晶粒310、堅硬結構315等等的表面),來移除殘留的黏著劑。然後將一散熱器335貼合至IC封裝300的表面312,如第三F圖內所示。
在將散熱器335置於IC封裝300之前先移除剛性基板350可讓散熱器350接合至IC晶粒310,如此散熱器335和IC晶粒310直接接觸,或只由薄熱介面材料層分隔(例如包含導熱粒子的熱化合物)。此外,在將散熱器335置於IC封裝300之前先移除剛性基板350可減少IC晶粒310與散熱器335之間的熱介面數量。例如:在第三F圖內所示的組態中,IC晶粒310和散熱器335透過單層熱介面材料314接合在一起,改善熱量從IC晶粒310傳輸至散熱器335的效能,如此提高IC封裝300的整體冷卻效率。
此外,因為剛性基板350只是暫時接合至IC封裝300,所以剛性基板350的厚度可大於1公釐(例如大約5公釐或更厚),提高剛性並且進一步降低IC封裝300的扭曲量。相較之下,將一蓋子200永久貼合至傳統IC封裝100的傳統技術需要蓋子200的厚度小於大約1公釐,以確定IC封裝100的整體高度不超過封裝期間必須放置IC封裝100的處理設備之淨空需求。
在許多具體實施例內,剛性基板350可包含一可重複使用材料,例如陶瓷(例如玻璃)或金屬合金(例如鋼),可承受第二複數個焊錫凸塊結構340回流所需的溫度(例如大約200℃)而不軟化及/或熔化。進一步,在許多具體實施例內,剛性基板350透過暫時黏著劑接合至堅硬結構315及/ 或IC晶粒310,該黏著劑可承受第二複數個焊錫凸塊結構340回流所需的溫度。可用來將剛性基板350接合至IC封裝300的暫時黏著劑之範例包含化學活化黏著劑以及光活化黏著劑,例如聚合物型黏著劑。
在某些具體實施例內,剛性基板350包含一透明或半透明材料,例如玻璃,並且該暫時黏著劑包含一光活化黏著劑。在這種具體實施例內,利用讓光活化黏著劑(例如聚醯胺黏著劑)暴露在光線下,像是用紫外線照射穿透剛性基板350並照射在光活化黏著劑上,則可從IC封裝300移除剛性基板350。在這種具體實施例內,光線會破壞光活化黏著劑的聚合鍵結,導致剛性基板350從IC封裝300釋放出來。
在其他具體實施例內,剛性基板350可透過化學活化黏著劑接合至IC封裝300。在這種具體實施例內,利用將該暫時黏著劑暴露在化學物之下,例如溶解該暫時黏著劑及/或弱化與該暫時黏著劑相關連的聚合鍵結之溶劑,則可從IC封裝300移除剛性基板350。
散熱器335包含一導熱材料,例如銅或鋁。基板320及/或電路板325可包含有機材料及/或傳導材料,例如:基板320及/或電路板325可包含以一或多聚合層層壓的導電線路之一或多層來形成一基板,例如印刷電路板(PCB)。
第四圖為根據本發明許多具體實施例,用於封裝一積體電路晶粒之方法步驟流程圖。雖然已經結合第三A圖至第三F圖的結構來描述該等方法步驟,不過精通技術人士將了解,透過該等方法步驟(以任何順序)形成的任何結構都在本發明範疇內。
如所示,方法400從步驟410開始,其中IC晶粒310的第一表面透過第一複數個焊錫凸塊結構330貼合至基板320。在步驟420上,剛性基板350貼合至IC晶粒310和堅硬結構315的第二表面之至少一者。如上述,在許多具體實施例內,剛性基板350可透過暫時黏著劑,例如光活化及/或化學活化黏著劑,貼合至IC晶粒310及/或堅硬結構315的該第二表面。
接下來在步驟430上,基板320透過第二複數個焊錫凸塊結構340,貼合至電路板325或其他種基板。在步驟440上,在基板320已經 貼合至電路板325或其他基板之後,從IC晶粒310及/或堅硬結構315的該第二表面移除剛性基板350。在許多具體實施例內,利用讓該暫時黏著劑暴露在光線下,例如紫外線雷射,及/或利用將該暫時黏著劑暴露在一或多種化學化合物下,例如溶劑,來執行從IC晶粒310及/或堅硬結構315的該第二表面移除剛性基板350。
在步驟450上,選擇性清潔IC晶粒310及/或堅硬結構315的該第二表面,來移除殘留黏著劑。然後在步驟460上,將散熱器335置於IC晶粒310的第二表面上。在某些具體實施例內,散熱器335直接置於IC晶粒310的第二表面上,而在其他具體實施例內,在散熱器335與IC晶粒310之間只放置一層薄的熱介面材料。然後方法400結束。
總結來說,一剛性基板暫時連結至該IC封裝,以降低該封裝的扭曲量,並改善該等焊錫凸塊結構連結至該基板的共平面性。然後,在該剛性基板已連結至該IC封裝時,該IC封裝貼合至一電路板。在該IC封裝已貼合至該電路板之後,從該IC封裝移除該剛性基板,並且將一散熱器放置在該IC封裝內含的一或多個IC晶粒上。
本說明書所說明該等技術的至少一項優點為降低該IC封裝的扭曲量,在該IC封裝與該封裝要貼合的一電路板或其他基板之間可形成更可靠的電連接。進一步,本說明書所說明的該等技術減少該IC晶粒與該散熱器之間的熱介面數量,並且可讓該散熱器只透過薄的熱介面材料層就可接合至該IC晶粒。因此,透過該散熱器改善該IC封裝的冷卻。
許多具體實施例的描述已經為了說明而呈現,但非要將本發明受限在所公布形式中。在不脫離所描述具體實施例之範疇與精神的前提下,本技術之一般技術者將瞭解許多修正例以及變化例。
本具體實施例的態樣可具體實施為系統、方法或電腦程式產品。因此,本發明可為完整硬體具體實施例、完整軟體具體實施例(包含韌體、常駐軟體、微碼等)或軟體與硬體的組合具體實施例之樣態,在此通稱為「電路」、「模組」或「系統」。更進一步,本發明的樣態可採用具有媒體內具體實施電腦可讀取程式碼的一或多電腦可讀取媒體內具體實施之電腦程式產品之形式。
本說明書可運用任何一或多個電腦可讀取媒體的組合。該電腦可讀取媒體可為電腦可讀取信號媒體或電腦可讀取儲存媒體。電腦可讀取媒體例如可為,但不受限於電、磁、光學、電磁、紅外線或半導體系統、設備或裝置或上述任何合適的組合。電腦可讀取儲存媒體的更多特定範例(非專屬清單)包含:具有一或多條線的電連接、可攜式電腦磁碟、硬碟、隨機存取記憶體(RAM)、唯讀記憶體(ROM)、可抹除可程式唯讀記憶體(EPROM或快閃記憶體)、光纖、可攜式小型光碟唯讀記憶體(CD-ROM)、光學儲存裝置、磁性儲存裝置或前述任何合適的組合。在本文件的內文中,電腦可讀取儲存媒體可為:可包含或儲存程式,來讓指令執行系統、設備或裝置使用或相連之任何有形媒體。
上面藉由參考根據本發明具體實施例的方法、設備(系統)和電腦程式產品之流程圖和/或方塊圖來描述本發明樣態。應瞭解,流程圖和/或方塊圖中的每一方塊以及流程圖和/或方塊圖中方塊的組合都可由電腦程式指令來實施。這些電腦程式指令可提供給一般用途電腦、特殊用途電腦或其他可程式資料處理設備的處理器來產生像是指令的機器,其透過電腦或其他可程式資料處理設備的處理器、用於實施流程圖和/或方塊圖中方塊所指定功能/動作之裝置所執行。這種處理器可為,並非限制,一般用途處理器、特殊用途處理器、應用專屬處理器或場可編輯處理器。
圖式內的流程圖和方塊圖說明根據本發明許多具體實施例的系統、方法和電腦程式產品可能實施之架構、功能和操作。如此,流程圖或方塊圖內每一方塊都可代表模組、區段或程式碼部分,這部分程式碼可包括一或多個可執行指令來實施特定邏輯功能。也應注意,在某些替代實施當中,方塊內提到的功能可以不依照圖式內順序來執行。例如:兩連續顯示的方塊實際上可同時執行,或可顛倒順序執行,這取決於所牽涉到的功能。亦應注意,使用執行特殊功能或動作的特殊用途硬體系統或特殊用途硬體與電腦指令的組合,實施方塊圖和/或流程圖的每一方塊以及方塊圖和/或流程圖內方塊的組合。
在此已經參考特定具體實施例說明本發明。不過精通此技術的人士將會了解,在不背離申請專利範圍內公佈之本發明廣泛精神以及領 域下,可進行許多修改與變更。例如並且無限制,雖然本說明書中許多說明參照特定基板、黏著劑與IC晶粒之類型,不過精通技術人士將了解,本說明書中描述的系統及技術可適用於其他種基板、黏著劑與IC晶粒。因此前述說明與圖式僅供參考而不做限制。
雖然上述指向本發明的具體實施例,不過可想出不背離本發明基本領域以及底下申請專利範圍的其他與進一步具體實施例。

Claims (20)

  1. 一種用於封裝一積體電路晶粒之方法,該方法包括:透過一第一複數個焊錫凸塊結構,將該積體電路晶粒的一第一表面貼合至一第一基板;將一第二基板貼合至該積體電路晶粒的一第二表面;透過一第二複數個焊錫凸塊結構,將該第一基板貼合至一第三基板;將該第一基板貼合至該第三基板之後,從該積體電路晶粒的該第二表面移除該第二基板;以及在該積體電路晶粒的該第二表面上放置一散熱器。
  2. 如申請專利範圍第1項之方法,其中將該第二基板貼合至該積體電路晶粒的該第二表面包括在該第二基板與該積體電路晶粒的該第二表面之間放置一暫時黏著劑。
  3. 如申請專利範圍第2項之方法,其中從該積體電路晶粒的該第二表面移除該第二基板包括將該暫時黏著劑暴露在第一波長的光線之下。
  4. 如申請專利範圍第3項之方法,其中該第一波長的光線在該紫外線範圍之內。
  5. 如申請專利範圍第4項之方法,其中該第二基板包括一半透明基板。
  6. 如申請專利範圍第5項之方法,其中該第二基板包括玻璃。
  7. 如申請專利範圍第5項之方法,其中該暫時黏著劑包括一聚醯胺。
  8. 如申請專利範圍第2項之方法,其中從該積體電路晶粒的該第二表面移除該第二基板包括將該暫時黏著劑暴露在一化學化合物之下。
  9. 如申請專利範圍第2項之方法,其中該第二基板包括具有軟化點超過大約攝氏200度的一金屬合金。
  10. 如申請專利範圍第2項之方法,其中該第二基板包括一陶瓷。
  11. 如申請專利範圍第2項之方法,其中該暫時黏著劑可承受至少攝氏200度的溫度,而不會從該積體電路晶粒的該第二表面釋出該第二基板。
  12. 如申請專利範圍第1項之方法,在將該第二基板貼合至該積體電路晶粒的該第二表面之後,該等複數個焊錫凸塊結構大體上共平面。
  13. 如申請專利範圍第1項之方法,其中該第三基板包括一電路板。
  14. 一種用於封裝一積體電路晶粒之方法,該方法包括:透過一第一複數個焊錫凸塊結構,將該積體電路晶粒的一第一表面貼合至一第一基板;將該第二基板的一表面貼合至位於該積體電路晶粒附近的一堅硬結構,其中該第二基板的該表面與該積體電路晶粒的一第二表面彼此相向;透過一第二複數個焊錫凸塊結構,將該第一基板貼合至一電路板;將該第一基板貼合至該電路板之後,從該堅硬結構移除該第二基板;以及在該積體電路晶粒的該第二表面上放置一散熱器。
  15. 如申請專利範圍第14項之方法,其中將該第二基板貼合至該堅硬結構包括在該第二基板與該堅硬結構之間放置一暫時黏著劑。
  16. 如申請專利範圍第15項之方法,其中該第二基板包括一半透明基板,並且從該堅硬結構移除該第二基板包含將該暫時黏著劑暴露在一第一波長光線之下。
  17. 如申請專利範圍第16項之方法,其中該第一波長的光線在該紫外線範圍之內。
  18. 如申請專利範圍第15項之方法,其中從該堅硬結構移除該第二基板包括將該暫時黏著劑暴露在一化學化合物之下。
  19. 如申請專利範圍第15項之方法,其中該暫時黏著劑可承受至少攝氏200度的溫度,而不會從該積體電路晶粒的該第二表面釋出該第二基板。
  20. 如申請專利範圍第14項之方法,其中該堅硬結構位於該積體電路晶粒的周邊四周。
TW105118763A 2015-06-25 2016-06-15 用來控制積體電路封裝扭曲的可移除式基板 TWI621230B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/751,023 2015-06-25
US14/751,023 US9425171B1 (en) 2015-06-25 2015-06-25 Removable substrate for controlling warpage of an integrated circuit package

Publications (2)

Publication Number Publication Date
TW201705414A TW201705414A (zh) 2017-02-01
TWI621230B true TWI621230B (zh) 2018-04-11

Family

ID=56683270

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105118763A TWI621230B (zh) 2015-06-25 2016-06-15 用來控制積體電路封裝扭曲的可移除式基板

Country Status (2)

Country Link
US (2) US9425171B1 (zh)
TW (1) TWI621230B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11362044B2 (en) 2017-03-14 2022-06-14 Mediatek Inc. Semiconductor package structure
US11171113B2 (en) 2017-03-14 2021-11-09 Mediatek Inc. Semiconductor package structure having an annular frame with truncated corners
US11264337B2 (en) 2017-03-14 2022-03-01 Mediatek Inc. Semiconductor package structure
US11387176B2 (en) 2017-03-14 2022-07-12 Mediatek Inc. Semiconductor package structure
US10784211B2 (en) 2017-03-14 2020-09-22 Mediatek Inc. Semiconductor package structure
US11304290B2 (en) * 2017-04-07 2022-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods
EP3671831A1 (en) * 2018-12-18 2020-06-24 MediaTek Inc Semiconductor package structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6472762B1 (en) * 2001-08-31 2002-10-29 Lsi Logic Corporation Enhanced laminate flipchip package using a high CTE heatspreader
TW201132260A (en) * 2009-11-02 2011-09-16 Ati Technologies Ulc Circuit board with variable topography solder interconnects
CN103681374A (zh) * 2012-09-10 2014-03-26 矽品精密工业股份有限公司 封装件的制法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5656552A (en) * 1996-06-24 1997-08-12 Hudak; John James Method of making a thin conformal high-yielding multi-chip module
JP2001185653A (ja) * 1999-10-12 2001-07-06 Fujitsu Ltd 半導体装置及び基板の製造方法
US6617683B2 (en) * 2001-09-28 2003-09-09 Intel Corporation Thermal performance in flip chip/integral heat spreader packages using low modulus thermal interface material
AU2003284065A1 (en) * 2002-10-11 2005-05-05 Chien-Min Sung Carbonaceous heat spreader and associated methods
WO2004070790A2 (en) * 2003-02-03 2004-08-19 United Test And Assembly Center Ltd. Molded high density electronic packaging structure for high performance applications
US7126822B2 (en) * 2003-03-31 2006-10-24 Intel Corporation Electronic packages, assemblies, and systems with fluid cooling
US20060035413A1 (en) * 2004-01-13 2006-02-16 Cookson Electronics, Inc. Thermal protection for electronic components during processing
US7947533B2 (en) * 2007-10-01 2011-05-24 Narase Soodprasert Void free soldering semiconductor chip attachment method for wafer scale chip size
US20090152713A1 (en) * 2007-12-18 2009-06-18 Ioan Sauciuc Integrated circuit assembly including thermal interface material comprised of oil or wax
US8241964B2 (en) * 2010-05-13 2012-08-14 Stats Chippac, Ltd. Semiconductor device and method of embedding bumps formed on semiconductor die into penetrable adhesive layer to reduce die shifting during encapsulation
US9728481B2 (en) * 2011-09-07 2017-08-08 Nvidia Corporation System with a high power chip and a low power chip having low interconnect parasitics
US20130119529A1 (en) * 2011-11-15 2013-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having lid structure and method of making same
US9613830B2 (en) * 2011-12-30 2017-04-04 Deca Technologies Inc. Fully molded peripheral package on package device
US9576930B2 (en) * 2013-11-08 2017-02-21 Taiwan Semiconductor Manufacturing Co., Ltd. Thermally conductive structure for heat dissipation in semiconductor packages
US9287233B2 (en) * 2013-12-02 2016-03-15 Taiwan Semiconductor Manufacturing Co., Ltd. Adhesive pattern for advance package reliability improvement
US9615483B2 (en) * 2014-09-12 2017-04-04 Intel Corporation Techniques and configurations associated with a package load assembly

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6472762B1 (en) * 2001-08-31 2002-10-29 Lsi Logic Corporation Enhanced laminate flipchip package using a high CTE heatspreader
TW201132260A (en) * 2009-11-02 2011-09-16 Ati Technologies Ulc Circuit board with variable topography solder interconnects
CN103681374A (zh) * 2012-09-10 2014-03-26 矽品精密工业股份有限公司 封装件的制法

Also Published As

Publication number Publication date
US9425171B1 (en) 2016-08-23
TW201705414A (zh) 2017-02-01
US20160379939A1 (en) 2016-12-29

Similar Documents

Publication Publication Date Title
TWI621230B (zh) 用來控制積體電路封裝扭曲的可移除式基板
KR101805477B1 (ko) 저가의 패키지 휘어짐 해결 방법
TWI442485B (zh) 半導體裝置之製造方法
US8378480B2 (en) Dummy wafers in 3DIC package assemblies
CN102844861B (zh) 对用于裸片翘曲减少的组装的ic封装衬底的tce补偿
US7626251B2 (en) Microelectronic die assembly having thermally conductive element at a backside thereof and method of making same
WO2014129351A1 (ja) 半導体装置とその製造方法
US20090096085A1 (en) Thermally Enhanced Wafer Level Package
US8334174B2 (en) Chip scale package and fabrication method thereof
TW202006907A (zh) 半導體裝置
TWI652774B (zh) 電子封裝件之製法
US8440503B1 (en) Methods for performing reflow in bonding processes
US9362256B2 (en) Bonding process for a chip bonding to a thin film substrate
CN106373898A (zh) 半导体器件及其封装方法
JP2014107554A (ja) 積層型半導体パッケージ
JP2005026311A (ja) ダイシングフィルム、フリップチップ実装方法、及び半導体装置
JP2013197263A (ja) 半導体装置の製造方法
US8444043B1 (en) Uniform solder reflow fixture
US20130032270A1 (en) Thermal compression bonding with separate bond heads
JP4887170B2 (ja) 半導体装置の製造方法
TWI581385B (zh) 偏位積體電路封裝互連
US20220278069A1 (en) Structure and formation method of chip package with protective lid
TWM500997U (zh) Led覆晶封裝結構
JP2008016606A (ja) 半導体装置及びその製造方法
TWI721898B (zh) 半導體封裝結構