TWI442485B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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Publication number
TWI442485B
TWI442485B TW100130014A TW100130014A TWI442485B TW I442485 B TWI442485 B TW I442485B TW 100130014 A TW100130014 A TW 100130014A TW 100130014 A TW100130014 A TW 100130014A TW I442485 B TWI442485 B TW I442485B
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TW
Taiwan
Prior art keywords
resin
semiconductor
substrate
resin sealing
sealing body
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TW100130014A
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English (en)
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TW201214585A (en
Inventor
Takao Sato
Masayuki Miura
Taku Kamoto
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Toshiba Kk
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Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of TW201214585A publication Critical patent/TW201214585A/zh
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Publication of TWI442485B publication Critical patent/TWI442485B/zh

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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Description

半導體裝置之製造方法
本文所描述之實施例係關於一種半導體裝置之製造方法。
本申請案係基於且主張2010年8月25日申請之日本專利申請案第2010-188524號的優先權的權益，該申請案之全文以引用的方式併入本文。
行動電話等小型、薄型之便攜式電子機器係半導體裝置之裝載區域之面積狹小，且高度亦較低。因此，尋求一種如於基板之兩面安裝有半導體晶片之兩面安裝型之半導體裝置之類的薄型半導體裝置。薄型半導體裝置可以例如以下方式製作。首先，於特定支持基板上形成配線層後，於配線層之表面上安裝半導體晶片。將半導體晶片進行樹脂密封，獲得樹脂密封體後，藉由將支持基板去除而製作薄型半導體裝置。兩面安裝型半導體裝置係藉由亦於配線層之背面安裝半導體晶片而製作。
於上述半導體裝置之製造步驟中，支持基板之去除步驟變得重要。於支持基板之去除步驟中，要求一面可使支持基板重複使用，一面不使半導體晶片或配線層中產生不良，可短時間簡便地去除支持基板。對於如此之方面，提出有藉由剪斷包含形成於支持基板與配線層之間之熱塑性樹脂等之剝離層，而使包含配線層、半導體晶片與密封樹脂層之電路構成體自支持基板中分離之方法。
於形成於支持基板上之配線層上，通常安裝有複數個半導體晶片。將複數個半導體晶片成批地樹脂密封，製作樹脂密封體。藉由將樹脂密封體之配線層連同密封樹脂層一併切斷，而使電路構成體(半導體裝置)單片化。包含複數個半導體晶片之樹脂密封體，要求抑制自支持基板剝離時產生之翹曲。產生於樹脂密封體之翹曲亦容易殘存於單片化之電路構成體中。產生於電路構成體(半導體裝置)之翹曲成為將電路構成體安裝於基板等時導致黏著性或連接性下降之因素。
根據1個實施形態，本發明係提供一種半導體裝置之製造方法，其包含如下步驟：於支持基板上形成剝離層；於剝離層上形成包含複數個裝置形成區域與切割區域之配線層；以於複數個裝置形成區域分別配置半導體晶片之方式，於配線層上安裝複數個半導體晶片；於配線層上形成覆蓋複數個半導體晶片之密封樹脂層，獲得包含配線層與複數個半導體晶片之樹脂密封體；使樹脂密封體自支持基板中分離；基於切割區域切斷樹脂密封體，使包含配線層、半導體晶片與密封樹脂層之電路構成體單片化。於如此之半導體裝置之製造方法中，當使樹脂密封體自支持基板中分離時、或於使樹脂密封體自支持基板中分離後，一面利用保持體平坦地保持樹脂密封體整體，一面對樹脂密封體進行加熱，並一面維持由保持體平坦地保持樹脂密封體之狀態，一面於冷卻後解除保持體對上述樹脂密封體之保持狀態。
本半導體裝置之製造方法可抑制成批地密封有複數個半導體晶片之樹脂密封體之翹曲。
(第1實施形態)
參照圖式，對第1實施形態之半導體裝置之製造方法進行說明。
圖1A~圖1D、圖2A~圖2C、圖3A~圖3C、圖4A~圖4C、及圖5A~圖5C係表示第1實施形態之半導體裝置之製造步驟的圖。首先，如圖1A所示，準備8英吋之Si晶圓等作為支持基板1。於支持基板1上形成剝離層2。支持基板1亦可為玻璃基板、藍寶石基板、樹脂基板等。
剝離層2係由例如聚苯乙烯系樹脂、甲基丙烯酸系樹脂、聚乙烯系樹脂、聚丙烯系樹脂、纖維素系樹脂、聚醯亞胺系樹脂等熱塑性樹脂形成。剝離層2之厚度較佳為1~20 μm之範圍，進而，更佳為3~15 μm之範圍。若剝離層2之厚度未達1 μm，則存在支持基板1之分離步驟中難以良好地剪斷剝離層2之虞。即便使剝離層2較厚地形成，其厚度達到20 μm左右即為充分。若剝離層2之厚度厚於20 μm，則導致製造成本之增加。
其次，如圖1B所示，於剝離層2上形成配線層3。配線層3係包含複數個裝置形成區域X與設置於其等之間之切割區域D。配線層3係具有圖3A所示之構造，且例如以如下方式形成。首先，於剝離層2上形成構成配線層3之第1有機絕緣膜4A。繼而，對第1有機絕緣膜4A實施曝光顯影處理，形成開口部。開口部係以與配置於配線層3之第1面(自支持基板1之剝離面)3a之連接墊對應之方式形成。
其次，形成構成配線層3之金屬配線。例如，於第1有機絕緣膜4A上形成電鍍籽晶層5，並於該電鍍籽晶層5上形成抗蝕膜，實施曝光顯影處理後，將電鍍籽晶層5作為電極進行電解電鍍，從而形成金屬配線6。金屬配線6係由Cu、Al、Ag、Au等形成。於將抗蝕膜、及露出於第1有機絕緣膜4A上之電鍍籽晶層5去除後，形成使配線層3之第2面3b側之相當於連接墊之部分開口之第2有機絕緣膜4B。金屬配線6之一部分係於開口內露出，且該部分構成貫通有機絕緣膜4之連接墊6a。
金屬配線6之連接墊6a係分別於配線層3之第1及第2面3a、3b露出。連接墊6a之第2面3b側之露出部係作為與安裝在配線層3上之半導體晶片連接之連接部發揮作用。連接墊6a之第1面3a側之露出部係作為與其他半導體晶片或配線基板等連接之連接部發揮作用。圖3A係表示單層之金屬配線6，但亦可由2層或2層以上之金屬配線構成配線層3。有機絕緣膜4係與金屬配線6之層數對應地形成。此處所述之配線層3之形成步驟係為一例，亦可應用其他形成步驟形成配線層3。
繼而，如圖1C所示，於配線層3上安裝複數個半導體晶片7。半導體晶片7係分別配置於配線層3之裝置形成區域X上。半導體晶片7之安裝步驟係例如圖3B所示，應用倒裝晶片(FC)連接實施。即，半導體晶片7係包含含有Sn-Ag合金等的金屬凸塊8。半導體晶片7係以金屬凸塊8與連接墊6a之於第2面3b側露出之部分連接之方式安裝。配線層3與半導體晶片7之連接並不限定於FC連接，亦可應用打線接合進行電性連接。
如圖1D及圖3C所示，於配線層3之第2面3b上形成密封樹脂層9。密封樹脂層9係藉由模具成型等而形成。密封樹脂層9係如圖3C所示，根據需要於半導體晶片7與配線層3之間隙填充底膠樹脂10後形成。密封樹脂層9係以成批地覆蓋安裝在配線層3上之複數個半導體晶片7之方式形成。即，複數個半導體晶片7係以晶圓級成批地被樹脂密封。以此之方式製作成批地密封有安裝在配線層3上之複數個半導體晶片7之樹脂密封體11。
繼而，如圖2A及圖4A所示，將包含支持基板1、與介隔剝離層2形成於該支持基板1上之樹脂密封體11之積層體加熱至特定溫度，並一面使作為剝離層2之熱塑性樹脂層軟化，一面使支持基板1與樹脂密封體11於大致平行之方向上相對地移動。藉由利用產生於支持基板1與樹脂密封體11之間之剪斷力，剪斷已軟化之剝離層2，而使樹脂密封體11自支持基板1中分離。此時，可不僅藉由支持基板1與樹脂密封體11之大致平行之移動，而且藉由亦於上下方向上以若干之比例移動，而促進樹脂密封體11之分離。
作為剝離層2之熱塑性樹脂層之加熱溫度較佳為例如220~260℃之範圍。若為如此溫度之加熱處理，則不會導致半導體晶片7之熱損壞、及FC連接部或配線層3之變形等，可使支持基板1短時間內簡便地分離。進而，已分離之支持基板1可重複使用。為了更容易地進行經加熱處理之支持基板1與樹脂密封體11之分離，較佳為，構成剝離層2之熱塑性樹脂之黏度於250℃下為100 Pa‧s以下。
樹脂密封體11與支持基板1之分離步驟係首先如圖5A所示，利用第1及第2保持體12、13分別平坦地保持樹脂密封體11與支持基板1。第1及第2保持體12、13係包含平坦地保持樹脂密封體11或支持基板1之吸附保持機構。可藉由利用第1保持體12吸附保持樹脂密封體11，而更平坦地保持樹脂密封體11。樹脂密封體11與支持基板1之保持機構亦可為機械地保持該等之端面之機構。
吸附保持樹脂密封體11之第1保持體12中內具有加熱器(未圖示)作為將剝離層2加熱至特定溫度之機構，且可藉由控制加熱器之輸出，而以特定溫度梯度加熱及冷卻樹脂密封體11。亦於吸附保持支持基板1之第2保持體13視需要內具有加熱器(未圖示)。可使第1保持體12與第2保持體13相對地於平行方向及上下方向上移動，藉此，可使支持基板1與樹脂密封體11於大致平行之方向、進而於上下方向上移動。
於使樹脂密封體11自支持基板1中之分離步驟中，利用第1及第2保持體12、13分別平坦地保持樹脂密封體11與支持基板1後，將樹脂密封體11加熱至剝離層2軟化之溫度。於該狀態下，藉由使第1及第2保持體12、13相對地移動，使樹脂密封體11與支持基板1之間產生剪斷力，而將因加熱而軟化之剝離層2剪斷。如此，藉由對剝離層2一面加熱一面剪斷，而使樹脂密封體11自支持基板1中分離。
剝離層2之加熱機構並不限定於上述普通之加熱器，亦可使用雷射等。於該種情形時，較佳為，由例如TEMPAX玻璃之類的可透過雷射且相較熱塑性樹脂容易蓄積雷射熱量之材料構成支持基板1。即便應用雷射加熱之情形時，亦於將樹脂密封體11加熱至剝離層2軟化之溫度後，使第1及第2保持體12、13相對地移動，使樹脂密封體11與支持基板1之間產生剪斷力，從而剪斷剝離層2。
作為剝離層2之加熱源，亦可使用鹵素燈、氙氣燈、IR加熱器等非接觸且可加熱被加熱物之熱源。亦可藉由使用如此之加熱源，加熱樹脂密封體11或支持基板1、或者該兩者，而使作為剝離層2之熱塑性樹脂層軟化分離。較佳為，此時使用之支持基板1使用賦予玻璃與碳系材料者、或者賦予SUS與碳系材料者等有效地利用自熱源輻射之可見光或紅外線等光之穿透性或來自熱源之熱能之蓄熱性等特徵之材料。
自支持基板1中分離之樹脂密封體11係如圖5B所示，一面維持由第1保持體12平坦地保持之狀態一面進行冷卻。於剪斷剝離層2，使樹脂密封體11分離之情形時，於配線層3之第1面3a中殘存有剝離層2之殘渣層2a。樹脂密封體11之冷卻步驟係自分離步驟起連續地加熱至密封樹脂層9之玻璃轉移點以上之溫度後，冷卻至低於玻璃轉移點之溫度，或暫時解除保持狀態，再次由保持體12平坦地保持經冷卻之樹脂密封體11，進行上述加熱及冷卻。無論何種情形，均可獲得樹脂密封體11之翹曲抑制效果。較佳為，使樹脂密封體11之加熱溫度為相較密封樹脂之玻璃轉移點高5~15℃之溫度。藉此，可有效地矯正樹脂密封體11之翹曲。
繼而，基於特定之冷卻步驟將樹脂密封體11冷卻後，如圖5C所示，解除第1保持體12對樹脂密封體11之保持狀態。使加熱至密封樹脂層9之玻璃轉移點以上之溫度之樹脂密封體11一面維持由第1保持體12平坦地保持之狀態，一面冷卻至低於密封樹脂層9之玻璃轉移點之溫度，並於冷卻後解除樹脂密封體11之保持狀態。藉此，可抑制於剪斷剝離層2時基於樹脂密封體11所受之應力等之樹脂密封體11之翹曲。
於樹脂密封體11之冷卻步驟中，較佳為，將第1保持體12對樹脂密封體11之保持狀態維持於低於構成密封樹脂層9之密封樹脂(例如環氧樹脂)之玻璃轉移點(Tg)之溫度、例如相較玻璃轉移點低10℃之溫度。可藉由於如此之溫度之前利用第1保持體12平坦地持續保持樹脂密封體11，而有效地獲得樹脂密封體11之翹曲矯正效果。因此，可抑制解除第1保持體12之保持狀態後之樹脂密封體11之翹曲。用作密封樹脂之環氧樹脂之玻璃轉移點係為130~170℃左右，且常溫下之彈性模數為20~30 GPa左右。
較佳為，樹脂密封體11之冷卻步驟以至少通過密封樹脂之玻璃轉移點(Tg)之溫度區(Tg前後之溫度區)之溫度梯度(冷卻速度)達到1~10℃/分鐘之範圍之方式進行控制。經加熱之密封樹脂層9之形狀係因冷卻時之溫度條件而變化。若受到通過密封樹脂之玻璃轉移點時之冷卻條件影響，通過玻璃轉移點之溫度區之溫度梯度(冷卻速度)過大，則無法充分地釋放產生於密封樹脂層9內之應力(產生翹曲之應力)。因此，存在於解除第1保持體12之保持狀態下之樹脂密封體11內殘存有翹曲之虞。
因此，較佳為，使樹脂密封體11冷卻時之通過密封樹脂之玻璃轉移點之溫度區之溫度梯度為10℃/分鐘以下。然而，若冷卻時之溫度梯度較小，則相應地冷卻步驟所需之時間變得長時間化，導致半導體裝置之製造成本增加。因此，較佳為，使通過密封樹脂之玻璃轉移點之溫度區之溫度梯度為1℃/分鐘以上。即便冷卻時之溫度梯度未達1℃/分鐘，密封樹脂層9之翹曲之矯正效果亦無法再提高，導致冷卻步驟之長時間化、進而半導體裝置之製造成本之增加變得顯著。通過玻璃轉移點之溫度區之溫度梯度在提高生產效率方面，更佳為儘可能地接近10℃/分鐘。
對使加熱後之密封樹脂層9緩冷之情形與急冷之情形下之翹曲量進行評價之結果示於圖6。緩冷之評價係將密封樹脂(環氧樹脂/Tg=150℃前後)於吸附台上加熱至200℃，並於密封樹脂軟化之狀態下放置5分鐘後吸附，且一面維持吸附一面以3℃/分鐘進行緩冷矯正時，比較矯正前之翹曲量與矯正後之翹曲量。急冷之評價係將相同之密封樹脂於加熱板上加熱至200℃，並於密封樹脂軟化之狀態下放置5分鐘後，將密封樹脂移至吸附台上，一面吸附一面以100℃/分鐘進行急冷矯正時，比較矯正前之翹曲量與矯正後之翹曲量。根據圖6可明確獲悉於緩冷之情形時翹曲之矯正效果較高。
1~10℃/分鐘之冷卻速度亦可應用於剝離層2之自加熱溫度起直至常溫之冷卻步驟整體，但若使冷卻步驟整體之冷卻速度為上述範圍，則半導體裝置之生產效率下降。進而，密封樹脂層9之翹曲受到通過密封樹脂之玻璃轉移點之溫度區之冷卻速度之影響。因此，即便於僅使通過玻璃轉移點之溫度區之冷卻速度為1~10℃/分鐘之範圍之情形時，亦可獲得翹曲之矯正效果。因此，如圖7所示，較佳為，相對於通過玻璃轉移點Tg之溫度區(第2溫度區T2)之溫度梯度(例如1~10℃/分鐘)，使其以前之溫度區(第1溫度區T1)與其以後之溫度區(第3溫度區T3)之溫度梯度變大。
於圖7之溫度分佈中，較佳為，使第2溫度區T2為相對玻璃轉移點Tg高5~15℃之溫度至相對玻璃轉移點Tg低5~15℃之溫度之範圍。較佳為，使第2溫度區T2之冷卻速度(溫度梯度)如上所述為1~10℃/分鐘之範圍。較佳為，使第1溫度區T1為自剝離層2之加熱溫度起直至相較玻璃轉移點Tg高5~15℃之溫度之範圍。較佳為，使第3溫度區T3為自相較玻璃轉移點Tg低5~15℃之溫度起直至常溫之範圍。較佳為，使該等溫度區T1、T3之冷卻速度(溫度梯度)為10~50℃/分鐘之範圍。
於樹脂密封體11之冷卻步驟中，如上所述，可藉由將通過玻璃轉移點Tg之溫度區(第2溫度區T2)進行緩冷(例如1~10℃/分鐘之溫度梯度)，並使其前後之溫度區(第1及第3溫度區T1、T3)之溫度梯度大於第2溫度區T2，而一面有效地矯正樹脂密封體11之翹曲，一面抑制半導體裝置之生產效率之下降。即，可低成本且高效率地製作翹曲較少之可靠之樹脂密封體11、進而製作半導體裝置。
剪斷剝離層2後之樹脂密封體11係控制例如內置於第1保持體12中之加熱器之輸出，以特定之溫度分佈進行冷卻。然而，亦存在因樹脂密封體11而無法獲得充分之冷卻速度之情形。對於如此之方面，如圖8所示，可藉由使維持著由第1保持體12之保持狀態之樹脂密封體11接觸於散熱體14，而提高冷卻效率。由於配線層3之第1面3a中殘存有剝離層2之殘渣層2a，故而，較佳為，為了防止熔融狀態之殘渣層2a對散熱體14之附著，而於散熱體14之表面預先設置脫模層(氟系樹脂之塗佈層或脫模膜等)15。
散熱體14係由具有與冷卻速度相應之熱導率之構件形成。例如，內置加熱器之保持體(加熱台)12通常由導熱性較高之鋁(熱導率=240 W/m‧K)形成。可藉由使樹脂密封體11接觸於包含熱導率低於上述保持體(加熱台)12之構件之散熱體14進行冷卻，而實現適度之冷卻速度(緩冷速度)。作為此種構件，可列舉氧化鋁(熱導率=36 W/m‧K)、不鏽鋼(熱導率=27 W/m‧K)、石英玻璃(熱導率=1.4 W/m‧K)、聚矽氧橡膠(熱導率=0.2 W/m‧K)等。散熱體14係包含未圖示之散熱機構，藉此，可進行溫度控制。
可藉由使樹脂密封體11接觸於包含熱導率相對較低之構件之散熱體14進行冷卻，而有效地獲得例如圖7之第2溫度區T2中之緩冷速度。圖7之第1及第3溫度區T1、T3中之冷卻速度可藉由使樹脂密封體11接觸於例如包含熱導率較高之鋁等之散熱體14而實現。如此般，可藉由準備複數個包含熱導率不同之構件之散熱體14，並使樹脂密封體11與對應於冷卻速度之散熱體14接觸，而一面控制樹脂密封體11之冷卻速度一面有效地進行冷卻。可藉由組合加熱器之輸出控制或對散熱體14之接觸與開放，而更有效地冷卻樹脂密封體11。
冷卻後之樹脂密封體11係如圖4B所示，於配線層3之第1面3a上產生剝離層2之殘渣層2a，故而，利用丙酮或丙二醇甲基醚乙酸酯(PGMEA)等溶劑去除。進而，將配線層3之第1面3a上露出之電鍍籽晶層5蝕刻去除。藉此，使連接墊(Cu墊等)6a於配線層3之第1面3a上露出。
樹脂密封體11自支持基板1之分離步驟並不限定於使包含上述熱塑性樹脂層之剝離層2軟化剪斷之方法，亦可應用形成Cu等金屬層作為剝離層，並機械地剝離該剝離層之接合界面之方法；利用溶劑溶解包含有機物之剝離層之方法；及利用濕式蝕刻或乾式蝕刻去除剝離層之方法等。進而，亦可應用由光硬化型樹脂(UV硬化型樹脂等)形成剝離層，並且介隔包含玻璃之支持基板1照射UV光進行分離之方法；或者，由光分解型樹脂形成剝離層，並且介隔包含玻璃之支持基板1照射雷射光或紫外光，將剝離層分解分離之方法等。
於應用不伴隨加熱之分離步驟之情形時，使樹脂密封體11自支持基板1分離後，利用保持體12平坦地保持樹脂密封體11。於此狀態下，加熱至密封樹脂層9之玻璃轉移點以上之溫度後，再冷卻至低於玻璃轉移點之溫度。繼之，於冷卻後解除保持體12對樹脂密封體11之保持狀態。如此般，即便與分離步驟分開單獨地實施樹脂密封體11之加熱步驟及冷卻步驟(平坦化步驟)之情形時，亦可矯正並抑制樹脂密封體11之翹曲。冷卻步驟中之具體條件(冷卻時之溫度梯度或應用該溫度梯度之溫度區等)係如上所述。
繼而，藉由利用刀片16沿著切割區域D切斷翹曲經矯正之密封樹脂體11，而如圖2C及圖4C所示，使包含配線層3、半導體晶片7與密封樹脂層9之電路構成體(半導體裝置)17分別單片化。以如此方式獲得之半導體裝置17因成批密封有複數個半導體晶片7之樹脂密封體11之翹曲得到抑制，故可於翹曲等較少之可靠之狀態下獲得。因此，可提高半導體裝置17對基板之安裝性等。
由上述製造步驟製作之半導體裝置17係例如圖9所示，安裝於封裝基板18，藉此，製作半導體封裝體19。半導體裝置17與封裝基板18係藉由形成於配線層3之連接墊6a上之金屬凸塊20而連接。半導體裝置17因翹曲之產生得到抑制，故而，可提高對封裝基板18之安裝性。半導體封裝體19亦可以如下方式製作，即，將半導體裝置17黏著於封裝基板18，並利用打線接合將配線層3與封裝基板18電性連接。於如此之情形時，可提高半導體裝置17對封裝基板18之黏著性。
半導體裝置17亦可用作圖10所示之兩面安裝型之半導體封裝體21之構成零件。於圖10所示之兩面安裝型之半導體封裝體21中，在露出於配線層3之第1面3a上之連接墊6a形成有配線22。第2半導體晶片23之金屬凸塊24係FC連接於配線22。於第2半導體晶片23與配線層3之間填充有底膠樹脂25。由於配線層3之第2面3b上安裝有第1半導體晶片7，因此，將第1及第2半導體晶片7、23安裝於配線層3之兩面。
即便於如此之兩面安裝構造中，亦可抑制半導體裝置17之翹曲，因此，可提高第1半導體晶片7與第2半導體晶片23之連接性。安裝於配線層3之兩面上之第1及第2半導體晶片7、23係安裝於封裝基板26上。第1及第2半導體晶片7、23與封裝基板26係經由接線27電性連接。藉由利用形成於封裝基板26上之密封樹脂層28將安裝於配線層3之兩面上之第1及第2半導體晶片7、23整體密封，而構成半導體封裝體21。
(第2實施形態)
參照圖式，對第2實施形態之半導體裝置之製造方法進行說明。圖11A~圖11C、及圖12A~圖12B係表示第2實施形態之半導體裝置之製造步驟的圖。首先，如圖11A所示，準備包含複數個裝置形成區域X與設置於其等之間之切割區域D之配線基板31。其次，如圖11B所示，於配線基板31上安裝複數個半導體晶片32。半導體晶片32係分別配置於配線基板31之裝置形成區域X。
半導體晶片32之安裝步驟係應用例如倒裝晶片(FC)連接而實施。配線基板31與半導體晶片32之連接並不限定於FC連接，亦可應用打線接合而電性連接。繼而，如圖11C所示，於配線基板31上形成密封樹脂層33。密封樹脂層33係藉由模具成型等而形成。密封樹脂層33係以成批地覆蓋安裝於配線基板31上之複數個半導體晶片32之方式形成。以此方式，製作成批地密封安裝於配線基板31上之複數個半導體晶片32之樹脂密封體34。
其次，如圖12A所示，利用保持體35平坦地保持樹脂密封體34。保持體35係包含平坦地保持樹脂密封體34之吸附保持機構。可藉由利用保持體35吸附保持樹脂密封體34，而更平坦地保持樹脂密封體34。樹脂密封體34之保持機構亦可為機械地進行夾持之機構。於保持體35中內具有加熱器(未圖示)，且可藉由控制加熱器之輸出，而以特定之溫度梯度加熱及冷卻樹脂密封體34。加熱機構亦可為上述雷射、鹵素燈、氙氣燈、及IR加熱器等。
繼而，將由保持體35平坦地保持之樹脂密封體34加熱至密封樹脂層33之玻璃轉移點以上之溫度後，一面維持保持狀態一面冷卻至低於玻璃轉移點之溫度。樹脂密封體34之加熱條件或冷卻條件較佳為與第1實施形態相同。較佳為，將樹脂密封體34加熱至相較密封樹脂之玻璃轉移點高5~15℃之溫度。於樹脂密封體34之冷卻步驟中，較佳為，使通過密封樹脂之玻璃轉移點之溫度區之溫度梯度為10℃/分鐘以下。較佳為，使到達通過上述玻璃轉移點之溫度區以前之溫度區、及通過玻璃轉移點之溫度區以後之溫度區中的溫度梯度大於通過玻璃轉移點之溫度區的溫度梯度。較佳為，其他條件亦與第1實施形態相同。
基於特定之冷卻條件將樹脂密封體34冷卻後，如圖12B所示，解除保持體35對樹脂密封體34之保持狀態。如此般，可藉由使樹脂密封體34一面由保持體35平坦地保持一面進行加熱及冷卻，而矯正及抑制樹脂密封體34之翹曲。此後，切斷樹脂密封體34，使半導體裝置單片化。單片化之半導體裝置可用於各種封裝等。
(第3實施形態)
參照圖式，對第3實施形態之半導體裝置之製造方法進行說明。圖13A~圖13C、及圖14A~圖14C係表示第3實施形態之半導體裝置之製造步驟的圖。圖13A~圖13C及圖14A~圖14C係表示1個半導體裝置之製造步驟，但第3實施形態之製造方法亦可同樣地應用於使用包含複數個裝置形成區域之半導體基板之製造步驟。於該情形時，除了最終藉由沿著切割區域將半導體基板切斷，而使半導體裝置單片化以外，均應用相同之製造步驟。
首先，如圖13A所示，於半導體基板41之第1面41a側形成配線層42。配線層42係包含形成於半導體基板41之第1面41a上之導體層43、與作為貫通電極之導體填充層44。導體填充層44係藉由在設置於半導體基板41之槽內填充導電材料，或者進行電鍍而形成。繼而，以覆蓋配線層42之方式，於半導體基板41之第1面41a上形成絕緣樹脂層45。絕緣樹脂層45係作為配線層42之保護膜發揮作用者。
其次，如圖13B所示，於半導體基板41之第1面41a上介隔著絕緣樹脂層45黏著支持基板46。支持基板46係藉由黏著劑層47而與半導體基板41黏著。較佳為，黏著劑層47包含含有熱塑性樹脂之黏著劑，以便於後續步驟之分離步驟中進行加熱時容易剝離。如下所述，於將加熱、冷卻步驟與分離步驟分開單獨地實施之情形時，亦可使用紫外線硬化型樹脂等黏著劑。
如圖13C所示，藉由利用機械研磨或蝕刻等切削半導體基板41之第2面41b，而使半導體基板41薄板化。半導體基板41之第2面41b係以導體填充層44露出之方式進行切削。藉此，形成貫通半導體基板41之貫通電極44A。於半導體基板41之第2面41b上，以使貫通電極44A露出之方式形成絕緣膜48。
其次，如圖14A所示，利用第1保持體49平坦地保持半導體基板41，並且利用第2保持體50平坦地保持支持基板46。第1及第2保持體49、50係包含平坦地保持半導體基板41或支持基板46之吸附保持機構。於第1保持體49中內具有加熱器(未圖示)，且可藉由控制加熱器之輸出，而以特定之溫度梯度加熱及冷卻半導體基板41。加熱機構亦可為上述雷射、鹵素燈、氙氣燈、及IR加熱器等。第2保持體50中亦視需要而內具加熱機構等。
繼而，將由第1保持體49平坦地保持之半導體基板41加熱至黏著劑層47軟化可使支持基板46剝離之溫度。藉由於該狀態下，使第1及第2保持體49、50相對地移動，而使半導體基板41自支持基板46中分離。自支持基板46中分離之半導體基板41係如圖14B所示，一面維持由第1保持體49平坦地保持之狀態一面進行冷卻。
半導體基板41之冷卻步驟係自分離步驟連續地加熱至絕緣樹脂層45之玻璃轉移點以上之溫度後，再冷卻至低於玻璃轉移點之溫度。或者，亦可暫時解除第1保持體49對半導體基板41之保持狀態進行冷卻後，再次利用保持體49平坦地保持半導體基板41，並進行上述加熱步驟及冷卻步驟。無論何種情形，均可獲得抑制半導體基板41之翹曲之效果。
較佳為，使半導體基板41之加熱條件或冷卻條件與第1實施形態相同。較佳為，將半導體基板41加熱至相較絕緣樹脂之玻璃轉移點高5~15℃之溫度。於半導體基板41之冷卻步驟中，較佳為，使通過絕緣樹脂之玻璃轉移點之溫度區之溫度梯度為10℃/分鐘以下。較佳為，使到達通過上述玻璃轉移點之溫度區以前之溫度區、及通過玻璃轉移點之溫度區以後之溫度區中的溫度梯度大於通過玻璃轉移點之溫度區的溫度梯度。較佳為，亦使其他條件與第1實施形態相同。
如圖14C所示，藉由基於特定之冷卻步驟將半導體基板41冷卻後，解除第1保持體49對半導體基板41之保持狀態，而獲得半導體裝置51。可藉由使半導體基板41一面由保持體49平坦地保持一面進行加熱及冷卻，而矯正及抑制半導體裝置51之翹曲。半導體基板41並不限定於包含主動元件者，亦可為僅包含配線者。進而，第3實施形態之製造步驟亦可應用於半導體基板41上裝載其他主動晶片或主動晶片之構造。
雖然已僅藉由實例來描述特定之實施例，但本實施例並非欲限制本發明之範疇。而且，於此所描述之新穎之方法可以各種形式來實施；此外，可以本方法所描述之形式且於不偏離本發明之精神的前提下，進行各種省略、變更及修改。隨附申請專利範圍及其等效體包含此種形式或修改，且屬於本發明之範圍及精神。
1．．．持基板
2．．．剝離層
2a．．．殘渣層
3．．．配線層
3a．．．配線層3之第1面
3b．．．配線層3之第2面
4．．．有機絕緣膜
4A．．．第1有機絕緣膜
4B．．．第2有機絕緣膜
5．．．電鍍籽晶層
6．．．金屬配線
6a．．．連接墊
7．．．半導體晶片
8．．．金屬凸塊
9．．．密封樹脂層
10．．．底膠樹脂
11．．．樹脂密封體
12．．．第1保持體
13．．．第2保持體
14．．．散熱體
15．．．脫模層
16．．．刀片
17．．．電路構成體
18．．．封裝基板
19．．．半導體封裝體
20．．．金屬凸塊
21．．．兩面安裝型之半導體封裝體
22．．．配線
23．．．第2半導體晶片
24．．．金屬凸塊
25．．．底膠樹脂
26．．．封裝基板
27．．．接線
28．．．密封樹脂層
31．．．配線基板
32．．．半導體晶片
33．．．密封樹脂層
34．．．樹脂密封體
35．．．保持體
41．．．半導體基板
41a．．．半導體基板41之第1面
41b．．．半導體基板41之第2面
42．．．配線層
43．．．導體層
44．．．導體填充層
44A．．．貫通電極
45．．．絕緣樹脂層
46．．．支持基板
47．．．黏著劑層
48．．．絕緣膜
49．．．第1保持體
50．．．第2保持體
D．．．切割區域
X．．．裝置形成區域
圖1A~圖1D係表示第1實施形態之半導體裝置之製造方法中的自剝離層之形成步驟起至密封樹脂層之形成步驟為止之剖面圖。
圖2A~圖2C係表示第1實施形態之半導體裝置之製造方法中的自樹脂密封體之分離步驟起至樹脂密封體之切斷步驟為止之剖面圖。
圖3A~圖3C係將圖1A~圖1C所示之半導體裝置之製造步驟中的自配線層之形成步驟起至密封樹脂層之形成步驟為止放大進行表示之剖面圖。
圖4A~圖4C係將圖2A~圖2C所示之半導體裝置之製造步驟中的自樹脂密封體之分離步驟起至剝離層之去除步驟為止放大進行表示之剖面圖。
圖5A~圖5C係表示圖2A~圖2C所示之半導體裝置之製造步驟中的自樹脂密封體之分離步驟起至樹脂密封體之冷卻步驟為止之剖面圖。
圖6係表示將樹脂密封體進行緩冷後之翹曲量與將樹脂密封體進行急冷之情形進行比較評價之結果的圖。
圖7係表示樹脂密封體之冷卻步驟中之溫度分佈之一例的圖。
圖8係表示樹脂密封體之冷卻步驟之其他例之剖面圖。
圖9係表示使用有第1實施形態中製作之半導體裝置之半導體封裝體之一例的剖面圖。
圖10係表示使用有第1實施形態中製作之半導體裝置之兩面安裝型半導體封裝體之一例的剖面圖。
圖11A~圖11C係表示第2實施形態之半導體裝置之製造方法中的自配線基板之準備步驟起至密封樹脂層之形成步驟為止之剖面圖。
圖12A及圖12B係表示第2實施形態之半導體裝置之製造方法中之樹脂密封體之冷卻步驟之剖面圖。
圖13A~圖13C係表示第3實施形態之半導體裝置之製造方法中的自配線層之形成步驟起至切削半導體基板之步驟為止之剖面圖。
圖14A~圖14C係表示第3實施形態之半導體裝置之製造方法中的自半導體基板之分離步驟起至半導體基板之冷卻步驟為止之剖面圖。
1．．．支持基板
2．．．剝離層
3．．．配線層
7．．．半導體晶片
9．．．密封樹脂層
11．．．樹脂密封體
D．．．切割區域
X．．．裝置形成區域

Claims (20)

  1. 一種半導體裝置之製造方法，其包含如下步驟：於支持基板上形成剝離層；於上述剝離層上形成包含複數個裝置形成區域及切割區域之配線層；以於上述複數個裝置形成區域中分別配置半導體晶片之方式，於上述配線層上安裝複數個半導體晶片；於上述配線層上形成覆蓋上述複數個半導體晶片之密封樹脂層，獲得包含上述配線層與上述複數個半導體晶片之樹脂密封體；使上述樹脂密封體自上述支持基板分離；及基於上述切割區域切斷上述樹脂密封體，使包含上述配線層、上述半導體晶片與上述密封樹脂層之電路構成體單片化；於使上述樹脂密封體自上述支持基板分離時，或者使上述樹脂密封體自上述支持基板分離後，一面利用保持體平坦地保持上述樹脂密封體整體一面進行加熱，且一面維持由上述保持體平坦地保持上述樹脂密封體之狀態，一面於冷卻後解除上述保持體對上述樹脂密封體之保持狀態。
  2. 如請求項1之半導體裝置之製造方法，其中上述樹脂密封體係整體地由第1保持體平坦地保持，且上述支持基板係由第2保持體保持，藉由一面對上述樹脂密封體及上述剝離層進行加熱，一面使上述第1保持體與上述第2保持體相對地移動，而使上述樹脂密封體自上述支持基板分離。
  3. 如請求項2之半導體裝置之製造方法，其中上述剝離層係包含熱塑性樹脂，且藉由剪斷經加熱之上述剝離層，而使上述樹脂密封體自上述支持基板分離。
  4. 如請求項1之半導體裝置之製造方法，其中上述樹脂密封體係自上述支持基板分離，且使自上述支持基板分離之上述樹脂密封體一面整體地由上述保持體平坦地保持，一面進行加熱。
  5. 如請求項4之半導體裝置之製造方法，其中藉由剪斷上述剝離層、溶解上述剝離層、利用蝕刻去除上述剝離層、利用光使上述剝離層硬化、或者利用光使上述剝離層分解，而使上述樹脂密封體自上述支持基板分離。
  6. 如請求項1之半導體裝置之製造方法，其中上述樹脂密封體係加熱至高於上述密封樹脂之玻璃轉移點5~15℃之溫度。
  7. 如請求項6之半導體裝置之製造方法，其中上述樹脂密封體係冷卻至低於上述玻璃轉移點之溫度後，解除由上述保持體之保持狀態。
  8. 如請求項7之半導體裝置之製造方法，其中將通過上述玻璃轉移點之溫度區之溫度梯度設為1~10℃/分鐘之範圍。
  9. 如請求項7之半導體裝置之製造方法，其中使到達通過上述玻璃轉移點之溫度區以前之溫度區、及通過上述玻璃轉移點之溫度區以後之溫度區中的溫度梯度大於通過上述玻璃轉移點之溫度區的溫度梯度。
  10. 如請求項1之半導體裝置之製造方法，其中使由上述保持體保持之上述樹脂密封體接觸散熱體進行冷卻。
  11. 一種半導體裝置之製造方法，其包含如下步驟：準備包含複數個裝置形成區域與切割區域之配線基板；以於上述複數個裝置形成區域中分別配置半導體晶片之方式，於上述配線基板上安裝複數個半導體晶片；於上述配線基板上形成覆蓋上述複數個半導體晶片之密封樹脂層，獲得包含上述配線基板與上述複數個半導體晶片之樹脂密封體；一面利用保持體平坦地保持上述樹脂密封體整體，一面對上述樹脂密封體進行加熱；一面維持由上述保持體平坦地保持上述樹脂密封體之狀態，一面於冷卻後解除上述保持體對上述樹脂密封體之保持狀態；基於上述切割區域切斷上述樹脂密封體，使包含上述配線基板、上述半導體晶片與上述密封樹脂層之電路構成體單片化。
  12. 如請求項11之半導體裝置之製造方法，其中將上述樹脂密封體加熱至高於上述密封樹脂之玻璃轉移點5~15℃之溫度。
  13. 如請求項12之半導體裝置之製造方法，其中將上述樹脂密封體冷卻至低於上述玻璃轉移點之溫度後，解除上述保持體之保持狀態。
  14. 如請求項13之半導體裝置之製造方法，其中將通過上述玻璃轉移點之溫度區之溫度梯度設為1~10℃/分鐘之範圍。
  15. 如請求項13之半導體裝置之製造方法，其中使到達通過上述玻璃轉移點之溫度區以前之溫度區、及通過上述玻璃轉移點之溫度區以後之溫度區中的溫度梯度大於通過上述玻璃轉移點之溫度區的溫度梯度。
  16. 一種半導體裝置之製造方法，其包含如下步驟：準備包含第1面與第2面之半導體基板；於上述半導體基板之上述第1面側形成包含貫通電極之配線層；以覆蓋上述配線層之方式，於上述半導體基板上形成絕緣樹脂層；利用黏著劑層使支持基板介隔上述絕緣樹脂層而與上述半導體基板黏著；切削上述半導體基板之上述第2面，使上述半導體基板薄板化；及使上述半導體基板自上述支持基板分離；於使上述半導體基板自上述支持基板分離時，或者於使上述半導體基板自上述支持基板分離後，使上述半導體基板一面整體由保持體平坦地保持一面進行加熱，且一面維持由上述保持體平坦地保持上述半導體基板之狀態，一面於冷卻後解除上述保持體對上述半導體基板之保持狀態。
  17. 如請求項16之半導體裝置之製造方法，其中上述半導體基板係整體由第1保持體平坦地保持，且上述支持基板係由第2保持體保持，藉由一面對上述半導體基板及上述黏著劑層進行加熱，一面使上述第1保持體與上述第2保持體相對地移動，而使上述半導體基板自上述支持基板分離。
  18. 如請求項16之半導體裝置之製造方法，其中上述半導體基板係加熱至高於上述絕緣樹脂之玻璃轉移點5~15℃之溫度。
  19. 如請求項18之半導體裝置之製造方法，其中將上述半導體基板冷卻至低於上述玻璃轉移點之溫度後，解除上述保持體之保持狀態。
  20. 如請求項19之半導體裝置之製造方法，其係將通過上述玻璃轉移點之溫度區之溫度梯度設為1~10℃/分鐘之範圍。
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130040779A (ko) * 2010-03-31 2013-04-24 에베 그룹 에. 탈너 게엠베하 양면에 칩이 장착되는 웨이퍼를 제작하기 위한 방법
US20140151095A1 (en) * 2012-12-05 2014-06-05 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and method for manufacturing the same
JP2015103572A (ja) * 2013-11-21 2015-06-04 日東電工株式会社 両面セパレータ付き封止用シート、及び、半導体装置の製造方法
JPWO2015199030A1 (ja) * 2014-06-26 2017-05-25 凸版印刷株式会社 配線基板、半導体装置及び半導体装置の製造方法
JP6447075B2 (ja) * 2014-12-10 2019-01-09 凸版印刷株式会社 配線基板、半導体装置及び半導体装置の製造方法
JP6455197B2 (ja) * 2015-02-06 2019-01-23 凸版印刷株式会社 配線基板、半導体装置及び半導体装置の製造方法
TWI671831B (zh) * 2015-09-30 2019-09-11 日商富士軟片股份有限公司 半導體元件的製造方法
US11224927B2 (en) * 2015-11-25 2022-01-18 International Business Machines Corporation Circuit card attachment for enhanced robustness of thermal performance
US20190057936A1 (en) * 2015-12-18 2019-02-21 Intel Corporation Transmissive composite film for application to the backside of a microelectronic device
JP2017176460A (ja) * 2016-03-30 2017-10-05 富士フイルム株式会社 針状凸部を有するシートの製造方法
TW201821280A (zh) * 2016-09-30 2018-06-16 日商富士軟片股份有限公司 積層體以及半導體元件的製造方法
JP7012824B2 (ja) * 2017-09-13 2022-01-28 ジェニュイン ソリューションズ ピーティーイー リミテッド ポリマー樹脂モールド化合物ベースの基板の切断方法およびそのシステム
US11309177B2 (en) * 2018-11-06 2022-04-19 Stmicroelectronics S.R.L. Apparatus and method for manufacturing a wafer
EP3974491A4 (en) * 2019-05-22 2022-07-27 Showa Denko Materials Co., Ltd. METHOD OF MAKING A SEMICONDUCTOR DEVICE
US20210035795A1 (en) * 2019-07-30 2021-02-04 Applied Materials, Inc. Methods and apparatus for substrate warpage correction
IT201900015416A1 (it) 2019-09-03 2021-03-03 St Microelectronics Srl Apparecchio per la crescita di una fetta di materiale semiconduttore, in particolare di carburo di silicio, e procedimento di fabbricazione associato

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4029910B2 (ja) * 1994-03-18 2008-01-09 日立化成工業株式会社 半導体パッケ−ジの製造法及び半導体パッケ−ジ
EP1213756A3 (en) * 1994-03-18 2005-05-25 Hitachi Chemical Co., Ltd. Fabrication process of semiconductor package and semiconductor package
JPH0917816A (ja) * 1995-06-29 1997-01-17 Nec Kyushu Ltd 半導体装置の製造方法
JP3423897B2 (ja) * 1999-04-01 2003-07-07 宮崎沖電気株式会社 半導体装置の製造方法
JP2001217354A (ja) * 2000-02-07 2001-08-10 Rohm Co Ltd 半導体チップの実装構造、および半導体装置
US7102367B2 (en) * 2002-07-23 2006-09-05 Fujitsu Limited Probe card and testing method of semiconductor chip, capacitor and manufacturing method thereof
JP4471563B2 (ja) * 2002-10-25 2010-06-02 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2005123463A (ja) * 2003-10-17 2005-05-12 Seiko Epson Corp 半導体装置及びその製造方法、半導体装置モジュール、回路基板並びに電子機器
JP4794354B2 (ja) * 2006-05-23 2011-10-19 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
US8232185B2 (en) * 2007-04-05 2012-07-31 Hitachi Chemical Company, Ltd. Method for manufacturing semiconductor chip, adhesive film for semiconductor, and composite sheet using the film
JPWO2008126717A1 (ja) * 2007-04-06 2010-07-22 日立化成工業株式会社 半導体用接着フィルム、複合シート及びこれらを用いた半導体チップの製造方法
KR100934558B1 (ko) * 2007-10-08 2009-12-29 제일모직주식회사 실란커플링제와 선반응된 페놀형 경화수지를 포함하는반도체 조립용 접착 필름 조성물 및 이에 의한 접착 필름
JP2010010644A (ja) 2008-05-27 2010-01-14 Toshiba Corp 半導体装置の製造方法
JP2010192867A (ja) * 2009-01-20 2010-09-02 Renesas Electronics Corp 半導体集積回路装置および半導体集積回路装置の製造方法
JP5423020B2 (ja) * 2009-02-03 2014-02-19 セイコーエプソン株式会社 半導体装置、半導体装置の製造方法、及び電子機器
JP5675504B2 (ja) * 2010-08-06 2015-02-25 ルネサスエレクトロニクス株式会社 半導体装置、電子装置、及び半導体装置の製造方法

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