JP2009158764A5 - - Google Patents
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- Publication number
- JP2009158764A5 JP2009158764A5 JP2007336212A JP2007336212A JP2009158764A5 JP 2009158764 A5 JP2009158764 A5 JP 2009158764A5 JP 2007336212 A JP2007336212 A JP 2007336212A JP 2007336212 A JP2007336212 A JP 2007336212A JP 2009158764 A5 JP2009158764 A5 JP 2009158764A5
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- JP
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- Prior art keywords
- bumps
- distribution density
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- semiconductor substrate
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- 239000004065 semiconductor Substances 0.000 claims 46
- 239000000758 substrate Substances 0.000 claims 33
- 238000000034 method Methods 0.000 claims 5
- 230000002093 peripheral effect Effects 0.000 claims 5
- 238000004519 manufacturing process Methods 0.000 claims 3
- 230000004888 barrier function Effects 0.000 claims 2
- 239000002184 metal Substances 0.000 claims 2
- 238000005498 polishing Methods 0.000 claims 1
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007336212A JP5157427B2 (ja) | 2007-12-27 | 2007-12-27 | 積層型半導体装置、半導体基板及び積層型半導体装置の製造方法。 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007336212A JP5157427B2 (ja) | 2007-12-27 | 2007-12-27 | 積層型半導体装置、半導体基板及び積層型半導体装置の製造方法。 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009158764A JP2009158764A (ja) | 2009-07-16 |
| JP2009158764A5 true JP2009158764A5 (enExample) | 2011-05-12 |
| JP5157427B2 JP5157427B2 (ja) | 2013-03-06 |
Family
ID=40962449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007336212A Active JP5157427B2 (ja) | 2007-12-27 | 2007-12-27 | 積層型半導体装置、半導体基板及び積層型半導体装置の製造方法。 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5157427B2 (enExample) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5271562B2 (ja) * | 2008-02-15 | 2013-08-21 | 本田技研工業株式会社 | 半導体装置および半導体装置の製造方法 |
| US8012802B2 (en) * | 2010-02-04 | 2011-09-06 | Headway Technologies, Inc. | Method of manufacturing layered chip package |
| KR101242614B1 (ko) | 2010-12-17 | 2013-03-19 | 에스케이하이닉스 주식회사 | 반도체 집적회로 |
| JP5780498B2 (ja) * | 2011-01-25 | 2015-09-16 | 独立行政法人国立高等専門学校機構 | Cmos論理icパッケージの検査方法および検査装置 |
| KR20130016466A (ko) | 2011-08-08 | 2013-02-18 | 삼성전자주식회사 | 반도체 패키지 |
| JP2013183120A (ja) * | 2012-03-05 | 2013-09-12 | Elpida Memory Inc | 半導体装置 |
| JP6021378B2 (ja) | 2012-03-29 | 2016-11-09 | オリンパス株式会社 | 基板および半導体装置 |
| JP6616143B2 (ja) * | 2015-09-28 | 2019-12-04 | ラピスセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
| CN108288590B (zh) * | 2017-01-09 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | 凸块封装方法 |
| JP2023045675A (ja) | 2021-09-22 | 2023-04-03 | キオクシア株式会社 | 半導体装置及び半導体装置の製造方法 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002076247A (ja) * | 2000-08-25 | 2002-03-15 | Matsushita Electric Ind Co Ltd | 積層型半導体装置およびその製造方法 |
| TWI425604B (zh) * | 2004-07-26 | 2014-02-01 | 倫巴士公司 | 半導體裝置 |
-
2007
- 2007-12-27 JP JP2007336212A patent/JP5157427B2/ja active Active
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