JP5157427B2 - 積層型半導体装置、半導体基板及び積層型半導体装置の製造方法。 - Google Patents

積層型半導体装置、半導体基板及び積層型半導体装置の製造方法。 Download PDF

Info

Publication number
JP5157427B2
JP5157427B2 JP2007336212A JP2007336212A JP5157427B2 JP 5157427 B2 JP5157427 B2 JP 5157427B2 JP 2007336212 A JP2007336212 A JP 2007336212A JP 2007336212 A JP2007336212 A JP 2007336212A JP 5157427 B2 JP5157427 B2 JP 5157427B2
Authority
JP
Japan
Prior art keywords
bumps
dummy
semiconductor substrate
distribution density
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2007336212A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009158764A (ja
JP2009158764A5 (enExample
Inventor
和也 岡本
新吾 松岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nikon Corp
Original Assignee
Nikon Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nikon Corp filed Critical Nikon Corp
Priority to JP2007336212A priority Critical patent/JP5157427B2/ja
Publication of JP2009158764A publication Critical patent/JP2009158764A/ja
Publication of JP2009158764A5 publication Critical patent/JP2009158764A5/ja
Application granted granted Critical
Publication of JP5157427B2 publication Critical patent/JP5157427B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP2007336212A 2007-12-27 2007-12-27 積層型半導体装置、半導体基板及び積層型半導体装置の製造方法。 Active JP5157427B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007336212A JP5157427B2 (ja) 2007-12-27 2007-12-27 積層型半導体装置、半導体基板及び積層型半導体装置の製造方法。

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007336212A JP5157427B2 (ja) 2007-12-27 2007-12-27 積層型半導体装置、半導体基板及び積層型半導体装置の製造方法。

Publications (3)

Publication Number Publication Date
JP2009158764A JP2009158764A (ja) 2009-07-16
JP2009158764A5 JP2009158764A5 (enExample) 2011-05-12
JP5157427B2 true JP5157427B2 (ja) 2013-03-06

Family

ID=40962449

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007336212A Active JP5157427B2 (ja) 2007-12-27 2007-12-27 積層型半導体装置、半導体基板及び積層型半導体装置の製造方法。

Country Status (1)

Country Link
JP (1) JP5157427B2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108288590A (zh) * 2017-01-09 2018-07-17 中芯国际集成电路制造(上海)有限公司 凸块封装方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5271562B2 (ja) * 2008-02-15 2013-08-21 本田技研工業株式会社 半導体装置および半導体装置の製造方法
US8012802B2 (en) * 2010-02-04 2011-09-06 Headway Technologies, Inc. Method of manufacturing layered chip package
KR101242614B1 (ko) 2010-12-17 2013-03-19 에스케이하이닉스 주식회사 반도체 집적회로
JP5780498B2 (ja) * 2011-01-25 2015-09-16 独立行政法人国立高等専門学校機構 Ｃｍｏｓ論理ｉｃパッケージの検査方法および検査装置
KR20130016466A (ko) 2011-08-08 2013-02-18 삼성전자주식회사 반도체 패키지
JP2013183120A (ja) * 2012-03-05 2013-09-12 Elpida Memory Inc 半導体装置
JP6021378B2 (ja) 2012-03-29 2016-11-09 オリンパス株式会社 基板および半導体装置
JP6616143B2 (ja) * 2015-09-28 2019-12-04 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
JP2023045675A (ja) 2021-09-22 2023-04-03 キオクシア株式会社 半導体装置及び半導体装置の製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002076247A (ja) * 2000-08-25 2002-03-15 Matsushita Electric Ind Co Ltd 積層型半導体装置およびその製造方法
TWI425604B (zh) * 2004-07-26 2014-02-01 倫巴士公司 半導體裝置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108288590A (zh) * 2017-01-09 2018-07-17 中芯国际集成电路制造(上海)有限公司 凸块封装方法
CN108288590B (zh) * 2017-01-09 2020-03-10 中芯国际集成电路制造(上海)有限公司 凸块封装方法

Also Published As

Publication number Publication date
JP2009158764A (ja) 2009-07-16

Similar Documents

Publication Publication Date Title
JP5157427B2 (ja) 積層型半導体装置、半導体基板及び積層型半導体装置の製造方法。
US12463133B2 (en) Semiconductor structure and manufacturing method thereof
CN110970407B (zh) 集成电路封装件和方法
US10128223B2 (en) Semiconductor device and manufacturing method thereof
CN101752270B (zh) 堆叠集成电路半导体晶粒的形成方法
JP4409455B2 (ja) 半導体装置の製造方法
US10483239B2 (en) Semiconductor device including dual pad wire bond interconnection
TW202114111A (zh) 封裝
KR20160066120A (ko) 적층 구조를 갖는 반도체 소자 및 그 제조방법
JP5172751B2 (ja) 三次元積層型半導体集積回路の製造方法
JP2008235401A (ja) 半導体装置及びその製造方法
TW202245200A (zh) 半導體元件
CN103718286A (zh) 热压键合期间用于保护tsv末端的保护层
WO2021168953A1 (zh) 一种键合结构及其制造方法
CN108206169A (zh) 包含在裸芯边缘处的裸芯接合垫的半导体装置
JP2003086762A (ja) 半導体装置及びその製造方法
US20250006676A1 (en) Semiconductor package and method of manufacturing the semiconductor package
WO2021097730A1 (zh) 一种多芯片堆叠封装及制作方法
US11222865B2 (en) Semiconductor device including vertical bond pads
US11842979B2 (en) Semiconductor device and method of manufacturing the same
US20230377938A1 (en) Chip bonding method
US8384215B2 (en) Wafer level molding structure
JP6496389B2 (ja) 半導体装置及びその製造方法
JP6142800B2 (ja) 半導体装置及びその製造方法
JP2022102370A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20101227

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110121

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110318

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20111005

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120821

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121019

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20121113

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20121126

R150 Certificate of patent or registration of utility model

Ref document number: 5157427

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20151221

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20151221

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250