CN108206169A - 包含在裸芯边缘处的裸芯接合垫的半导体装置 - Google Patents

包含在裸芯边缘处的裸芯接合垫的半导体装置 Download PDF

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Publication number
CN108206169A
CN108206169A CN201611187727.0A CN201611187727A CN108206169A CN 108206169 A CN108206169 A CN 108206169A CN 201611187727 A CN201611187727 A CN 201611187727A CN 108206169 A CN108206169 A CN 108206169A
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China
Prior art keywords
naked core
bare chip
main surface
semiconductor bare
semiconductor
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Granted
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CN201611187727.0A
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CN108206169B (zh
Inventor
严俊荣
陈治强
陈昌恩
吴明霞
莫金理
S.巴贾思
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Shandi Trading Shanghai Co ltd
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SanDisk SemiConductor Shanghai Co Ltd
SanDisk Information Technology Shanghai Co Ltd
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Application filed by SanDisk SemiConductor Shanghai Co Ltd, SanDisk Information Technology Shanghai Co Ltd filed Critical SanDisk SemiConductor Shanghai Co Ltd
Priority to CN201611187727.0A priority Critical patent/CN108206169B/zh
Priority to US15/630,712 priority patent/US10128218B2/en
Priority to KR1020170111848A priority patent/KR102019551B1/ko
Priority to US15/907,600 priority patent/US10483239B2/en
Publication of CN108206169A publication Critical patent/CN108206169A/zh
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Publication of CN108206169B publication Critical patent/CN108206169B/zh
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Abstract

公开了一种半导体装置，其形成为具有位于半导体裸芯边缘处的裸芯接合垫。裸芯接合垫可以部分地形成在晶片上的半导体裸芯之间的切口区域中。当晶片被切片时，裸芯接合垫沿着其长度被切断，留下裸芯接合垫的一部分在切片的半导体裸芯的边缘处暴露。使得裸芯接合垫在裸芯的边缘处最小化了裸芯被堆叠为封装体时裸芯之间的偏移。

Description

包含在裸芯边缘处的裸芯接合垫的半导体装置
技术领域
本技术的示例涉及包含在裸芯边缘处的裸芯接合垫的半导体装置。
背景技术
对于便携消费级电子产品的需求的强劲增长驱动了对大容量存储装置的需求。非易失性半导体存储器装置(比如闪存存储卡)被广泛使用，以迎合信息存储和交换的日益增长的需求。其便携性、多功能性以及坚固的设计，连同其高可靠性以及大容量，已经使得这样的存储器装置理想地应用于多种多样的电子装置，包含例如数码相机、数字音乐播放器、视频游戏控制器、PDA以及移动电话。
半导体存储器典型地被设置在半导体封装体内，半导体封装体保护半导体存储器，并且允许存储器与主机装置之间的通信。半导体封装体的示例包含系统级封装(SiP)或多芯片模块(MCM)，其中多个裸芯被安装和互连在小足印(footprint)的基板上。
半导体裸芯通常以偏移阶梯式配置堆叠在封装体中，使得堆叠体中的每个裸芯的裸芯接合垫对于引线键合是可达到的。已经发现，随着堆叠体中的裸芯数目增加，在一个或多个裸芯的远端(与包含裸芯接合垫的近端相反)处已经检测到堆叠体中的一个或多个上部裸芯的翘曲。在偏移阶梯式裸芯堆叠体中，裸芯的远端悬垂在下面的裸芯之上，并且不被支承。这导致堆叠体的顶部处的一个或多个裸芯的远端向上弯曲离开裸芯堆叠体。
发明内容
概括起来，本技术的示例涉及一种半导体晶片，其包括：第一主表面；与第一主表面相反的第二主表面；多个半导体裸芯，其包括形成在晶片的第一主表面中的集成电路；切口区域，其包括切口线的第一集和第二集，切口线的第一集和第二集提供指定区域，在指定区域内，沿着多条切片线将多个半导体裸芯中的半导体裸芯彼此分离；以及多个裸芯接合垫，裸芯接合垫包括延伸到切口线的第一集中并且跨过多条切片线中的一条切片线的至少一部分。
在其他示例中，本技术涉及一种由半导体晶片形成的半导体裸芯，半导体裸芯包括：第一主表面；与第一主表面相反的第二主表面；集成电路，其形成为相邻于第一主表面且在有源区域内；以及多个裸芯接合垫，其至少部分地形成在有源区域之外。
在其他示例中，本技术涉及一种半导体封装体，其包括：基板；安装到基板的多个堆叠的存储器裸芯，堆叠的存储器裸芯中的半导体裸芯包括：集成电路，其形成相邻于第一主表面且在有源区域内；多个裸芯接合垫，其至少部分地形成在有源区域之外，并且在有源区域之外的半导体裸芯的边缘处具有切断的边缘；以及控制器裸芯，其电连接到堆叠的存储器裸芯，用于控制将数据传输到堆叠的存储器裸芯，以及从堆叠的存储器裸芯传输数据。
在另一示例中，本技术涉及一种由半导体晶片形成的半导体裸芯，半导体裸芯包括：第一主表面；与第一主表面相反的第二主表面；集成电路，其形成为相邻于第一主表面且在有源区域内；以及垫装置，其用于将信号传输到集成电路和从集成电路传输信号，垫装置在半导体裸芯的边缘处具有切断的边缘。
在另一示例中，本技术涉及一种由半导体晶片形成的半导体裸芯，半导体裸芯包括：第一主表面；第二主表面，所述第二主表面与所述第一主表面相反；集成电路，位于所述第一主表面内；以及多个裸芯接合垫，在所述半导体裸芯的边缘处具有切断边缘。
附图说明
图1是根据本发明的实施例形成半导体裸芯的流程图。
图2是示出了晶片的第一主表面的半导体晶片的正视图。
图3是晶片的一部分的放大图，示出了形成在晶片的切口区域中的裸芯接合垫。
图4和图5是示出了根据第一实施例的晶片内的裸芯接合垫和内部部件的截面边视图和俯视图。
图6和图7是示出了根据第二实施例的晶片内的裸芯接合垫和内部部件的截面边视图和俯视图。
图8和图9是示出了根据第三实施例的晶片内的裸芯接合垫和内部部件的截面边视图和俯视图。
图10和图11是示出了根据第四实施例的晶片内的裸芯接合垫和内部部件的截面边视图和俯视图。
图12和图13图示了研磨激光工艺之前的用于切片半导体晶片的隐形切片。
图14图示了根据本技术的第一实施例的包含具有边缘接合垫的裸芯的完成的半导体裸芯。
图15图示了根据本技术的可替代的实施例的包含具有边缘接合垫的裸芯的完成的半导体裸芯。
图16和图17是根据本技术的实施例的包含半导体裸芯的半导体封装体的立体和截面边视图。
图18-图20是根据本技术的可替代的实施例的包含半导体裸芯的半导体封装体的立体图。
具体实施方式
现将参考附图描述本技术，其在实施例中，涉及一种半导体裸芯，半导体裸芯形成为在半导体裸芯的边缘处具有裸芯接合垫。在实施例中，裸芯接合垫可以部分地在形成在晶片上的半导体裸芯之间的切口区域中。当晶片被切片时(例如在研磨工艺之前的隐形切片中)，裸芯接合垫被切断，留下裸芯接合垫的一部分暴露于切片的半导体裸芯的边缘处。当被堆叠到封装体中时，在裸芯的边缘处具有裸芯接合垫最小化裸芯之间的偏移。除了最小化裸芯堆叠体的足印之外，最小化裸芯偏移也最小化裸芯堆叠体的顶部处的一个或多个裸芯的翘曲。
应当理解，本发明能够以不同形式实施，而不应当理解为限制为本文提出的实施例。相反地，提供这些实施例使得本公开将变得彻底而完整，并将本发明彻底传达给那些本领域技术人员。事实上，本发明意图涵盖这些实施例的替代、改变和等效，其被包含在由所附权利要求限定的本发明的范围和精神内。此外，本发明的下面的详细说明中，提出了许多具体细节，以提供本发明的彻底理解。然而，本领域普通技术的人员将明白，可以在没有这样的具体细节的情况下实践本发明。
如本文中使用的，术语“顶部”和“底部”，“上”和“下”以及“垂直”和“水平”及其形式，可能作为示例使用，并且仅作为示例性目的，而并不意图限定本发明的描述，因为参考的项目可以在位置和取向上交换。同样，如本文中使用的，术语“实质上”和/或“大约”意味着具体的尺寸或参数可以在给定应用的可接受的制造公差范围内变化。在一个实施例中，可接受的制造公差是±0.25％。
现将参考图1的流程图以及图2-20的视图解释本发明的实施例。首先参考图1的流程图，半导体晶片100可以最初作为晶片材料的铸锭，其可以在步骤200中形成。在一个示例中，形成晶片100的铸锭可以是单晶硅，单晶硅根据切克劳斯基工艺(Czochralski，CZ)或者浮动区域工艺(floating zone，FZ)生长。然而在其他实施例中，晶片100可以由其他材料或其他工艺形成。
在步骤204中，半导体晶片100可以从铸锭切片，并且在第一主表面102(图2)和相反于表面102的第二主表面104(图12)两者上都抛光，以提供光滑表面。在步骤206中，第一主表面102可以经受各种工艺步骤，以将晶片100划分为相应的半导体裸芯106(其中一个在图2和图3中编号)，并且在第一主表面102上和/或中形成相应的半导体裸芯106的集成电路。这些各种工艺步骤可以包含沉积包含裸芯接合垫108(其中一个在图2中编号)的金属接触的金属化步骤，裸芯接合垫108暴露于第一主表面102上。金属化步骤还可以包含在晶片内沉积金属互连层和通孔。如下面参考图4-11所解释的，可以提供这些金属互连层和通孔，以将信号传输到集成电路和从集成电路传输信号，并且为集成电路提供结构性支承。
在图2中示出的在晶片100上的半导体裸芯106的数目仅为示例性目的，而在其他实施例中，晶片100可以包含比所示更多的半导体裸芯106。相似地，每个半导体裸芯106上的接合垫108的数目示出为示例性目的，而在其他实施例中，每个裸芯106可以包含比所示更多的裸芯接合垫。每个半导体裸芯106可以包含近端106a，近端106a包含接合垫108，以及与近端106a相反的远端106b。裸芯接合垫108可以由例如铝或其合金形成，但在其他实施例中，裸芯接合垫108可以由其他材料形成。在实施例中，集成电路可以工作为NAND闪存存储器半导体裸芯，尽管可以预期其他类型的集成电路。
在实施例中，每个裸芯接合垫108可以具有大约70μm的长度和宽度，尽管在其他实施例中，长度和宽度可以彼此成比例或不成比例地变化。根据本技术的方面，裸芯接合垫108可以至少部分地形成在划线区域或切口区域内，划线区域或切口区域设置在晶片100上的半导体裸芯106之间。图3是示出了晶片100的第一主表面102的一部分的立体图。晶片100可以包含切口区域112，切口区域112包括垂直地取向的切口线112a和水平地取向的切口线112b。切口区域112通常被保留为半导体裸芯的有源区域周围的边界，该处可进行切片，以将半导体裸芯从彼此以及晶片100分离。从而，切口区域112通常不形成为半导体裸芯106的可用于形成集成电路的有源区域的部分。
在一些传统切片技术(比如锯割)中，材料在切片过程中被从晶片移除，并且切片也不是精确地可控。从而，切口区域112通常大于需要进行实际切片的区域。一些晶片制造技术提供例如70μm的切口线宽度，而其他晶片制造技术提供例如170μm的切口线宽度。在不同的实施例中，切口线112a、切口线112b可以具有这些或其他的宽度。
如下面解释的，本技术的实施例使用研磨前的隐形切片，其为一种精确切片方法，其在切片晶片时移除少量的晶片或不移除晶片。图3还示出了垂直和水平切片线114，其指示了将沿其从晶片100切片裸芯106的线。如图所示，可以切片裸芯106，使得切口线112a、切口线112b的一部分保留作为每个半导体裸芯周围的边界。
根据本技术的方面，裸芯接合垫108的第一部分可以形成在半导体裸芯106的可用区域内，并且裸芯接合垫108的第二部分可以形成在水平切口线112b内。在实施例中，裸芯接合垫108延伸到水平切口线112b中的量可以变化，但其足够大，使得当从晶片100切片半导体裸芯106时，切片线114穿过裸芯接合垫108在水平切口线112b中的第二部分。在一个示例中，裸芯接合垫的一半可以延伸到水平切口线112b中。如果裸芯接合垫为70μm长，则35μm可以形成在水平切口线中。然而，提供此数量仅作为示例，并且如下面解释的，在其他实施例中，更多的裸芯接合垫108可以形成在水平切口线112b中。
从而，当半导体裸芯106被沿着切片线114从晶片100切片时，裸芯接合垫108中的每一个被切断，留下裸芯接合垫108的一部分暴露于每个半导体裸芯106的近端106a处的切片的边缘处。在切片之后，每个裸芯接合垫108的剩余部分可以在半导体裸芯106的远端106b中保持未被使用。
总体上，裸芯接合垫108的第二部分可以延伸进入水平切口线112b少于一半。在这样的实施例中，如图3所示，在切口线112b中，切割线114与远端106b相比更接近半导体裸芯的近端106a。在其他实施例中，裸芯接合垫108的第二部分可以延伸进入水平切口线112b多于一半。在这样的实施例中，如图5所示，切割线114可以更接近半导体裸芯近端106a，或切割线114可以在水平切口线112b的中间划下。
图4和图6是图3所示的示例半导体裸芯106的近端106a处的晶片100的截面侧视图和俯视图。每个半导体裸芯106可以包含集成电路120，集成电路120形成在基板层122上和/或中、半导体晶片的芯片区域内。在集成电路120形成之后，金属互连体124和通孔126的多层可以依次形成在电介质薄膜128的层中。如本领域已知的，可以使用光刻法或薄膜沉积工艺，将金属互连体124、通孔126以及电介质薄膜层128每次形成一层。光刻工艺可以包含例如：图案限定；等离子体、化学或干法蚀刻；以及抛光。薄膜沉积工艺可以包含例如溅射和/或化学气相沉积。金属互连体124可以由各种导电金属(包含例如本领域已知的铜和铜合金)形成，并且通孔可以衬有和/或填充有各种导电金属(包含例如本领域已知的钨、铜，以及铜合金)。
可以在上部电介质薄膜层128的顶部上形成钝化层130。可以蚀刻钝化层130，以形成裸芯接合垫108。每个裸芯接合垫108可以包含形成在衬垫134之上的接触层132。如本领域已知的，接触层132可以由例如铜、铝或其合金形成，并且衬垫134可以由例如钛/钛氮化物堆叠体(例如Ti/TiN/Ti)形成，尽管在其他实施例中，这些材料可以变化。接合垫108(接触层加衬垫)可以具有720nm的厚度，尽管在其他实施例中，此厚度可以更大或更小。
如本领域已知的，金属互连体124和通孔126可以被用来形成芯片区域内的导电节点140，其用于在裸芯接合垫108与集成电路120之间传输信号和电压。如本领域已知的，金属互连体124和通孔126还可以被用来形成密封环区域内的密封环142。密封环142可以围绕集成电路120和导电节点140，并且提供机械支承，以防止例如在晶片100的切片期间损坏集成电路120和导电节点140。
在图3-图5的实施例中，裸芯接合垫108部分地形成在晶片100上的芯片区域、密封环区域和水平切口线112b中。芯片区域和密封环区域在本文中可以统称为半导体裸芯106的有源区域。图5-图7还示出了切片线114，切片线114代表沿着其从晶片100切片半导体裸芯106的线。如图所示，当从晶片100切片时，切片线114切割穿过裸芯接合垫108，留下裸芯接合垫108的边缘暴露于每个半导体裸芯106的边缘处。裸芯接合垫108的此暴露的边缘在本文中可以称为边缘108a。在一个实施例中，可以在距裸芯接合垫的近端边缘1μm至5μm处切断裸芯接合垫108，尽管在其他实施例中，可以在距裸芯的近端边缘更近或更远处进行切片。
图6和图7是本技术的其他实施例的截面图和俯视图。在此实施例中，每个半导体裸芯106可以包含金属互连体124和通孔126，其如上所述的形成导电节点140和密封环142。然而，在此实施例中，裸芯接合垫108形成在钝化层130内、完全在晶片100上的水平切口线112b内。钝化层130的一部分也可以延伸到水平切口线112b中，尽管在其他实施例中不需要如此。在此实施例中，裸芯接合垫108可以具有与图6和图7的实施例中相同的长度，或者裸芯接合垫108可以具有不同的长度，例如较短。
图6和图7也示出切片线114，切片线114代表沿着其从晶片100切片半导体裸芯106的线。如图所示，当从晶片100切片时，切片线114切割穿过裸芯接合垫108，留下裸芯接合垫108的边缘108a暴露于每个半导体裸芯106的边缘处。
图8和图9是本技术的其他实施例的截面图和俯视图。在此实施例中，每个半导体裸芯可以包含如上所述的导电节点140和密封环142，以及如上所述的完全地形成在水平切口线112b内的裸芯接合垫108。然而，在图8和图9的实施例中，通过通孔144和金属互连体146将裸芯接合垫108电连接到导电节点140。如图所示，通孔144可以形成为向下延伸穿过全部电介质薄膜层128，并且进入基板层122中。金属互连体146可以形成在基板层122内，在通孔144与导电节点140的金属互连体之间延伸，在密封环142之下。在此实施例中，钝化层130可以或可以不延伸到水平切口线112b中。在此实施例中，裸芯接合垫108可以具有与图4和图5的实施例相同的长度，或者裸芯接合垫108可以具有不同的长度，例如较短。
图8和图9也示出切片线114，切片线114代表沿着其从晶片100切片半导体裸芯106的线。如图所示，当从晶片100切片时，切片线114切割穿过裸芯接合垫108，留下裸芯接合垫108的边缘108a暴露于每个半导体裸芯106的边缘处。
图10和图11是本技术的其他实施例的截面图和俯视图。在此实施例中，每个半导体裸芯可以包含如上所述的导电节点140和密封环142，并且裸芯接合垫108完全地形成在水平切口线112b内。然而，在此实施例中，裸芯接合垫108可以完全地形成在晶片100的主表面102之下。在此实施例中，钝化层130可以是晶片100的表面102上的连续(不间断的)层。裸芯接合垫108可以完全地形成在在钝化层130之下的电介质薄膜层128内。
在此实施例中，如下面解释的，裸芯接合垫108的暴露的边缘108a是裸芯接合垫108用于电连接到半导体封装体内的半导体裸芯106的仅有的部分。从而，裸芯接合垫108可以完全地形成在水平切口线112b内，具有比图4-图9的实施例中的裸芯接合垫108更短的长度。然而，图10和图11的实施例中的裸芯接合垫108可以具有与图4-图9的实施例中的裸芯接合垫108相同的长度。接触层132被示出为具有比前面描述的实施例更大的厚度，但接触层132的厚度可以可替代地与较早描述的实施例相同。
当沿着切片线114从晶片100切片半导体裸芯106时，裸芯接合垫108被切断，从而当从晶片100切片时，留下裸芯接合垫108的边缘108a暴露于每个半导体裸芯106的边缘处。然而，在此实施例中，裸芯接合垫108的边缘108a在半导体裸芯106的表面之下，主表面102和主表面104之间。
在图10和图11的实施例中，裸芯接合垫108可以包含如上所述的形成在衬垫134之上的接触层132。此外，如上面参考图10和图11描述的，可以通过通孔144和金属互连体146将裸芯接合垫108电连接到导电节点140，通孔144和金属互连体146形成为向下穿过一个或多个电介质层128，进入密封环142之下的基板层122。可替代地，在其他实施例中，可以在电介质薄膜层128内设置金属互连体124和通孔126，将芯接合垫108连接到密封环142之上的导电节点140。
在步骤206中形成集成电路120和金属导电层之后，在步骤210中可以将带的层层压到主表面102上。然后晶片100可以被翻转，并且在步骤212中切片。本技术的实施例使用研磨步骤之前的隐形切片来切片晶片100，其现将参考图12和图13进行解释。晶片100可以被支承在卡盘上或其他支承表面上(未示出)，第二主表面104背向支承表面。然后激光150可以以穿透晶片100的第二主表面104的波长(例如红外或近红外波长)发射脉冲激光束152。可以使用光学系统(例如包含一个或多个准直透镜156)，将脉冲激光束聚焦到晶片的表面104之下的点。当激光束在焦点处达到峰值功率密度时，晶片吸收能量，并且在晶片的表面之下产生针孔160。
激光可以在晶片的平面中沿着切口线112a和112b移动，并且在若干点处激发，使得若干紧密排布的针孔160形成在晶片的中间深度处(在晶片的第一主表面102和第二主表面104之间)。如图12和图13所示，针孔160的行和列限定将从晶片100切片的每个半导体裸芯106的最终形状。在图13中，激光150被示出为已经在晶片100的三个不同的深度处产生针孔160的层，但在其他实施例中，激光可以在一个或多个深度处形成针孔160的一个或多个层。虽然图13看起来示出了切片的半导体裸芯106，但尽管执行了隐形切片工艺，裸芯106可能仍是晶片100的一部分(并且当检查晶片100时，单独的针孔160将对肉眼不可见)。
在隐形切片步骤212之后，晶片100可以被切片或部分地切片。然后在步骤214中可以使用施加到第二主表面104的研磨轮(未示出)将晶片减薄。研磨轮可以将晶片100从例如780μm减薄到其最终厚度，例如大约25μm至36μm。应当理解，在其他实施例中，在背面研磨步骤之后，晶片100可以比此范围更薄或更厚。除了减薄晶片100之外，来自背面研磨步骤的振动可能导致针孔160处的裂纹朝向晶片100的第一主表面102和第二主表面104传播，以沿着切片线114完成在隐形切片之后、研磨步骤之前未完全切片的任何半导体裸芯的切片。
应当理解，在其他实施例中，可以通过除了研磨之前的隐形切片之外的其他方法切片晶片，包含例如锯割、激光或水射流切片方法。在这样的实施例中，可以在背面研磨步骤之前或之后切片晶片。
在完成切片步骤212和背面研磨步骤214之后，在步骤216中，可以将粘附于柔性切片带的裸芯粘附膜(DAF)的层施加到晶片100的第二主表面104上。然后在步骤218中，可以将晶片100翻转，并且支承在卡盘上或其他支承表面上，并且可以移除晶片100的第一主表面102上的层压带。一经在卡盘上，在步骤220中，可以沿着正交轴拉伸柔性切片带，以分离单独的半导体裸芯106，以允许单独的半导体裸芯106被抓放机器人移除，用于包含在半导体封装体中。应当预期，在背面研磨步骤214完成时，裸芯106未被完全切片。在此情况下，步骤220中的对切片带的拉伸将沿着切片线114完成半导体裸芯的切片。
图14示出了从晶片100分离之后的半导体裸芯106。裸芯106包含位于裸芯106的主表面102处的裸芯接合垫108，并且裸芯接合垫108的边缘108a暴露于半导体裸芯106的边缘106c处。图15示出了裸芯106的主表面102之下的裸芯接合垫108，并且裸芯接合垫108的边缘108a暴露于半导体裸芯106的边缘106c处。
图16和图17是根据上面描述的实施例制造的包含具有位于边缘106a处的裸芯接合垫108的半导体裸芯106的半导体封装体170的透视图和截面边视图。此实施例可以使用例如图4-图9中所示的任意半导体裸芯。图16和图17示出了引线键合到彼此以及基板172的若干半导体裸芯106。尽管示出了四个半导体裸芯106，应当理解，封装体170可以包含各种数目的半导体裸芯，包含例如2、4、8、16、32以及64个半导体裸芯。在其他实施例中，封装体170可以包含其他数目的半导体裸芯。
可以经由半导体裸芯中的每一个的底部表面上的DAF，将半导体裸芯106物理地安装到彼此以及基板172。经由引线键合体174(其中一个在图18和图19中的每一个中编号)，在基板172中将半导体裸芯106电耦接到彼此。可以根据若干方案形成引线键合体174。然而，在一个实施例中，引线键合体劈刀(未示出)在第一裸芯106-1的第一裸芯接合垫108上形成球凸块176。从该处，引线键合体劈刀付出导线，并且在基板172的接触垫178上形成缝接合体。然后引线键合体劈刀可以断开导线，向上移动到第二裸芯106-2的第一裸芯接合垫，并且形成球凸块176。从该处，引线键合体劈刀付出导线，并且在裸芯106-1的第一裸芯接合垫上的球凸块176的顶部上形成缝接合体。此过程继续在裸芯堆叠体向上，直到裸芯106-1、106-2、106-3以及106-4的第一裸芯接合垫108被引线键合到彼此以及基板172。然后对于封装体170中的裸芯106上的裸芯接合垫中的每一个重复此过程。如提到的，在其他实施例中，可以通过其他方法形成引线键合体174。
当完成引线键合体以及封装体170的制造时，裸芯接合垫108可以经由引线键合体174将信号传输到裸芯106内的集成电路120，以及从裸芯106内的集成电路120传输信号。图16和图17中所示的半导体封装体170还可以包含控制器裸芯175(比如ASIC)，如图17所示，引线键合到基板172，用于控制半导体裸芯106。如图17所示，可以通过将半导体裸芯和引线键合体包封在模塑料179中，完成封装体170。
本技术的其他特征是，能够以距下面的裸芯上的裸芯接合垫的小的间隔来堆叠每个裸芯。例如，裸芯106-2可以堆叠为远离裸芯106-1上的裸芯接合垫108的行0至5μm。在其他实施例中，此间隔可以比其更大。通常，裸芯接合垫与安装在其上的裸芯之间已经存在更大间隔，例如60μm。减小此间隔进一步允许裸芯重叠和裸芯堆叠体的总体足印的减小。
根据本技术的方面，与具有从近端边缘间隔设置的接合垫的常规半导体裸芯相比，在边缘处具有接合垫108的裸芯106允许以相对于彼此的较小的偏移来堆叠裸芯。例如，通过在半导体裸芯106-1的边缘106c处设置裸芯接合垫108，裸芯106-2可以被安装为更接近半导体裸芯106-1的边缘106c，导致半导体裸芯106-1与106-2之间的较小的偏移。封装体170中每个半导体裸芯的此较小的偏移复合，导致具有大量裸芯的封装体的显著的偏移和空间减小。例如，常规裸芯接合垫可以形成为距裸芯边缘100μm至120μm。从而，每个裸芯的偏移可以被减少例如100μm至120μm。此外，在包含例如16个半导体裸芯的裸芯堆叠体中，偏移的裸芯堆叠体的总体足印可以被减小1.6mm至1.9mm。除了裸芯堆叠体的足印的减小之外，较小的偏移减小或消除背景部分中所述的裸芯翘曲的问题。
图18-图20是根据上述实施例制造的半导体封装体180的立体图，并且包含在裸芯的边缘处具有裸芯接合垫108的半导体裸芯106。此实施例可以使用例如图6-图13所示的任何半导体裸芯。图18-图20示出了实质上堆叠为方块的若干个半导体裸芯106，彼此无偏移，形成例如芯片级封装体。尽管示出了四个半导体裸芯106，应当理解，封装体180可以包含各种数目的半导体裸芯，包含例如2、4、8、16、32以及64个半导体裸芯。在其他实施例中，封装体180可以包含其他数目的半导体裸芯。在图18-图20的实施例中，裸芯边缘106c可以堆叠为形成平面表面182，具有暴露于表面182处的接合垫边缘108a。
如图19所示，电迹线184的导电图案可以形成在平面表面182上，将接合垫边缘108a中所选择的多者彼此连接。在一个实施例中，为了形成电迹线184，可以将电绝缘体(比如二氧化硅)的层溅射到平面表面182上，以防止电迹线184与半导体裸芯106电短路。可以通过例如激光或化学蚀刻处理电绝缘体层，以暴露平面表面182中的裸芯接合边缘108a。然后可以通过例如印刷、溅射或光刻工艺，将电迹线184施加到绝缘体层上。导电迹线可以由绝缘体层上形成的例如钛、镍、铜或不锈钢来形成，但在其他实施例中，可以使用其他导电材料。图18中所示的特定导电图案仅作为示例，并且在其他实施例中可以变化。
参考图20的仰视图，可以将外部电连接体186(其中一个在图20中编号)施加到半导体封装体180的底部表面，以形成完成的封装体。例如，在半导体装置180作为BGA封装体被焊接到主机装置的母板上的情况下，外部电连接体可以是固定到半导体封装体180的底部表面上的重新分配垫(或其他接触垫)的焊料球。重新分配垫可以将电迹线184连接到外部电连接体186中的所选择的多者。
前述的发明的详细描述已经作为示例和说明被提出。其不意图穷举或将本发明限制为所公开的精确形式。根据上述教导，可以进行许多变化和改变。选择描述的实施例为了最佳地解释本发明的原理及其实际应用，从而使得其他本领域技术人员能够最佳地以各种实施例和适合所预期的特定用途的各种改变来利用本发明。本发明的范围意图由所附的权利要求限定。

Claims (24)

1.一种半导体晶片，包括：
第一主表面；
第二主表面，所述第二主表面与所述第一主表面相反；
多个半导体裸芯，所述多个半导体裸芯包括形成在所述晶片的第一主表面中的集成电路；
切口区域，所述切口区域包括切口线的第一集和第二集，所述切口线的第一集和第二集提供指定区域，在所述指定区域内，沿着多条切片线将所述多个半导体裸芯中的半导体裸芯彼此分离；以及
多个裸芯接合垫，所述裸芯接合垫包括至少一部分，所述一部分延伸到切口线的第一集中并且跨过所述多条切片线中的一条切片线。
2.如权利要求1所述的半导体晶片，其中所述多个裸芯接合垫完全地形成在所述切口线的第一集内。
3.如权利要求1所述的半导体晶片，其中所述多个裸芯接合垫部分地形成在所述切口线的第一集内。
4.如权利要求1所述的半导体晶片，其中所述多个裸芯接合垫在所述半导体晶片的第一主表面处暴露。
5.如权利要求1所述的半导体晶片，其中所述多个裸芯接合垫隐蔽在所述晶片的第一主表面之下。
6.如权利要求1所述的半导体晶片，其中所述多个裸芯接合垫设置在密封环之上，所述密封环形成在所述半导体晶片的表面之下。
7.一种由半导体晶片形成的半导体裸芯，所述半导体裸芯包括：
第一主表面；
第二主表面，所述第二主表面与所述第一主表面相反；
集成电路，所述集成电路相邻于所述第一主表面形成在有源区域内；以及
多个裸芯接合垫，所述多个裸芯接合垫至少部分地形成在所述有源区域之外。
8.如权利要求7所述的半导体裸芯，其中所述多个裸芯接合垫完全地形成在所述有源区域之外。
9.如权利要求7所述的半导体裸芯，其中所述多个裸芯接合垫在所述半导体裸芯的第一主表面处可见。
10.如权利要求7所述的半导体裸芯，其中所述多个裸芯接合垫在所述半导体裸芯的边缘处可见，并且隐蔽在所述半导体裸芯的第一主表面之下。
11.如权利要求7所述的半导体裸芯，其中所述多个裸芯接合垫设置在密封环之上，所述密封环形成在所述半导体晶片的表面之下。
12.如权利要求11所述的半导体裸芯，还包括金属互连体，所述金属互连体用于将所述多个裸芯接合垫电连接到所述集成电路，所述金属互连体位于所述密封环与所述半导体裸芯的第一主表面之间。
13.如权利要求11所述的半导体裸芯，还包括金属互连体，所述金属互连体用于将所述多个裸芯接合垫电连接到所述集成电路，所述金属互连体位于所述密封环与所述半导体裸芯的第二主表面之间。
14.如权利要求7所述的半导体裸芯，其中所述集成电路是用于闪存存储器的集成电路。
15.一种半导体封装体，包括：
基板；
安装到所述基板的多个堆叠的存储器裸芯，所述堆叠的存储器裸芯的半导体裸芯包括：
集成电路，所述集成电路形成为相邻于所述第一主表面且在有源区域内，
多个裸芯接合垫，所述多个裸芯接合垫至少部分地形成在所述有源区域之外，并且在所述有源区域之外的所述半导体裸芯的边缘处具有切断的边缘；以及
控制器裸芯，所述控制器裸芯电连接到所述堆叠的存储器裸芯，用于控制将数据传输到所述堆叠的存储器裸芯，以及从所述堆叠的存储器裸芯传输数据。
16.如权利要求15所述的半导体封装体，其中所述多个堆叠的存储器裸芯以偏移配置堆叠。
17.如权利要求16所述的半导体封装体，其中，与包含从所述边缘间隔设置的裸芯接合垫的半导体裸芯的堆叠体相比，在所述半导体裸芯的边缘处的所述裸芯接合垫允许所述半导体裸芯的偏移量的减少。
18.如权利要求16所述的半导体封装体，还包括引线键合体，所述引线键合体用于将所述多个堆叠的存储器裸芯彼此电连接，以及与所述基板电连接。
19.一种由半导体晶片形成的半导体裸芯，所述半导体裸芯包括：
第一主表面；
第二主表面，所述第二主表面与所述第一主表面相反；
集成电路，所述集成电路形成为相邻于所述第一主表面且在有源区域内；以及
垫装置，所述垫装置用于将信号传输到所述集成电路，以及从所述集成电路传输信号，所述垫装置在所述半导体裸芯的边缘处具有切断边缘。
20.如权利要求19所述的半导体裸芯，其中，与包含从所述边缘间隔设置的裸芯接合垫的半导体裸芯的堆叠体相比，所述垫装置允许所述半导体裸芯的偏移量的减少。
21.一种由半导体晶片形成的半导体裸芯，所述半导体裸芯包括：
第一主表面；
第二主表面，所述第二主表面与所述第一主表面相反；
集成电路，位于所述第一主表面内；以及
多个裸芯接合垫，在所述半导体裸芯的边缘处具有切断边缘。
22.如权利要求21所述的半导体裸芯，其中所述多个裸芯接合垫在所述半导体裸芯的第一主表面处可见。
23.如权利要求21所述的半导体裸芯，其中所述多个裸芯接合垫在所述半导体裸芯的边缘处可见，并且隐蔽在所述半导体裸芯的第一主表面之下。
24.如权利要求21所述的半导体裸芯，其中所述集成电路是用于闪存存储器的集成电路。
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