TWI456723B - 積體電路裝置及其製備方法 - Google Patents

積體電路裝置及其製備方法 Download PDF

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TWI456723B
TWI456723B TW100108226A TW100108226A TWI456723B TW I456723 B TWI456723 B TW I456723B TW 100108226 A TW100108226 A TW 100108226A TW 100108226 A TW100108226 A TW 100108226A TW I456723 B TWI456723 B TW I456723B
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integrated circuit
circuit device
wafer
block
conductive
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TW201234553A (en
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Jui Hsuan Chung
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Nanya Technology Corp
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    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Claims (18)

  1. 一種積體電路裝置，包含：一下晶圓，具有一第一介電區塊及一第一導電區塊，該第一導電區塊設置於該第一介電區塊之上，其中該第一導電區塊包含一基部及一環形側壁，該環形側壁設置於該基部之上；至少一堆疊晶圓，具有一第二介電區塊及一第二導電區塊，該第二導電區塊設置於該第二介電區塊之上，其中該堆疊晶圓係以一中間黏著層予以接合該下晶圓之上，且在該下晶圓及該堆疊晶圓之間沒有銲墊，其中該第二導電區塊係呈環形；以及至少一導電插塞，實質上以直線方式貫穿該堆疊晶圓且深入該下晶圓，其中該導電插塞設置於該第一導電區塊及該第二導電區塊之內。
  2. 根據申請專利範圍第1項所述之積體電路裝置，其中該第一導電區塊包含一阻障層及一種晶層。
  3. 根據申請專利範圍第1項所述之積體電路裝置，其中該第一介電區塊包含一基部及一環形側壁，該環形側壁設置於該基部之上。
  4. 根據申請專利範圍第1項所述之積體電路裝置，其中該第二介電區塊係呈環形。
  5. 根據申請專利範圍第1項所述之積體電路裝置，其中該下晶圓及該堆疊晶圓之間沒有銲料。
  6. 根據請求項1所述之積體電路裝置，其中該下晶圓另包含 一內連線通道，電氣連接於該導電插塞。
  7. 根據申請專利範圍第1項所述之積體電路裝置，其中該第一導電區塊沒有對齊該第二導電區塊。
  8. 根據申請專利範圍第1項所述之積體電路裝置，其中該第一介電區塊沒有對齊該第二介電區塊。
  9. 根據申請專利範圍第1項所述之積體電路裝置，其另包含一內連線層，設置於該下晶圓之上。
  10. 一種積體電路裝置之製備方法，包含下列步驟：形成一下晶圓，具有一第一凹部、設置於該第一凹部之中的一第一介電區塊及設置於該第一介電區塊之上的一第一導電區塊，其中該第一導電區塊包含一基部及一環形側壁，該環形側壁設置於該基部之上；形成至少一堆疊晶圓，具有一第二凹部、設置於該第一凹部之內的一第二介電區塊及設置於該第二介電區塊之上的一第二導電區塊，其中該第二導電區塊係呈環形；使用一中間黏著層接合該至少一堆疊晶圓至該下晶圓上，其中在該下晶圓及該堆疊晶圓之間沒有形成銲墊；進行一蝕刻製程以形成一通孔，實質上以直線方式貫穿該堆疊晶圓且深入該下晶圓，其中該通孔設置於該第一導電區塊及該第二導電區塊之內；以及使用導電材料填入該通孔以形成一導電插塞。
  11. 根據申請專利範圍第10項所述之積體電路裝置之製備方法，其中形成至少一堆疊晶圓包含進行一薄化步驟以局部 去除該堆疊晶圓之底部。
  12. 根據申請專利範圍第11項所述之積體電路裝置之製備方法，其中該薄化步驟曝露該第二介電區塊。
  13. 根據申請專利範圍第11項所述之積體電路裝置之製備方法，其中該薄化步驟曝露該第二凹部。
  14. 根據申請專利範圍第10項所述之積體電路裝置之製備方法，其中形成一下晶圓包含進行一薄化步驟以局部去除該下晶圓之底部。
  15. 根據申請專利範圍第14項所述之積體電路裝置之製備方法，其中該薄化步驟曝露該第一介電區塊。
  16. 根據申請專利範圍第14項所述之積體電路裝置之製備方法，其中該薄化步驟曝露該第一凹部。
  17. 根據申請專利範圍第10項所述之積體電路裝置之製備方法，其中使用一中間黏著層接合該至少一堆疊晶圓至該下晶圓上沒有使用銲料。
  18. 根據申請專利範圍第10項所述之積體電路裝置之製備方法，其另包含形成一內連線通道，電氣連接於該導電插塞。
TW100108226A 2011-02-01 2011-03-11 積體電路裝置及其製備方法 TWI456723B (zh)

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