WO2010116698A3 - Method of manufacturing semiconductor chip - Google Patents

Method of manufacturing semiconductor chip Download PDF

Info

Publication number
WO2010116698A3
WO2010116698A3 PCT/JP2010/002446 JP2010002446W WO2010116698A3 WO 2010116698 A3 WO2010116698 A3 WO 2010116698A3 JP 2010002446 W JP2010002446 W JP 2010002446W WO 2010116698 A3 WO2010116698 A3 WO 2010116698A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor layer
substrate
semiconductor chip
release layer
layer
Prior art date
Application number
PCT/JP2010/002446
Other languages
French (fr)
Other versions
WO2010116698A2 (en
Inventor
Takao Yonehara
Kiyofumi Sakaguchi
Nobuo Kawase
Kenji Nakagawa
Original Assignee
Canon Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Kabushiki Kaisha filed Critical Canon Kabushiki Kaisha
Priority to US13/262,830 priority Critical patent/US8871640B2/en
Publication of WO2010116698A2 publication Critical patent/WO2010116698A2/en
Publication of WO2010116698A3 publication Critical patent/WO2010116698A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of manufacturing a semiconductor chip including an integrated circuit and a through-electrode penetrating a semiconductor layer includes the steps of preparing a first substrate including a release layer and a semiconductor layer formed on the release layer; forming an integrated circuit in the semiconductor layer; forming, in the semiconductor layer, a hole or groove having a depth that does not reach the release layer; filling the hole or the groove with an electrical conductor; bonding a second substrate to the semiconductor layer to form a bonded structure; separating the bonded structure at the release layer to prepare the second substrate to which the semiconductor layer is transferred; and removing at least a portion of the reverse surface side of the semiconductor layer exposed by the separation to expose the bottom of the electrical conductor.
PCT/JP2010/002446 2009-04-06 2010-04-02 Method of manufacturing semiconductor chip WO2010116698A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/262,830 US8871640B2 (en) 2009-04-06 2010-04-02 Method of manufacturing semiconductor chip

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009092319A JP5409084B2 (en) 2009-04-06 2009-04-06 Manufacturing method of semiconductor device
JP2009-092319 2009-04-06

Publications (2)

Publication Number Publication Date
WO2010116698A2 WO2010116698A2 (en) 2010-10-14
WO2010116698A3 true WO2010116698A3 (en) 2011-01-06

Family

ID=42829930

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/002446 WO2010116698A2 (en) 2009-04-06 2010-04-02 Method of manufacturing semiconductor chip

Country Status (4)

Country Link
US (1) US8871640B2 (en)
JP (1) JP5409084B2 (en)
TW (1) TW201110311A (en)
WO (1) WO2010116698A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5943544B2 (en) * 2010-12-20 2016-07-05 株式会社ディスコ Manufacturing method of laminated device and laminated device
JP2012204589A (en) * 2011-03-25 2012-10-22 Disco Abrasive Syst Ltd Semiconductor device wafer bonding method
FR2980919B1 (en) * 2011-10-04 2014-02-21 Commissariat Energie Atomique DOUBLE LAYER REPORT METHOD
KR101946005B1 (en) * 2012-01-26 2019-02-08 삼성전자주식회사 Graphene device and method of manufacturing the same
EP3101687B1 (en) * 2014-01-27 2020-12-09 National Institute Of Advanced Industrial Science And Technology Package formation method and mems package
CN104198079A (en) * 2014-07-30 2014-12-10 肇庆爱晟电子科技有限公司 Quick response thermosensitive chip with high precision and reliability and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030108715A1 (en) * 2001-12-11 2003-06-12 Intel Corporation Method for bonding and debonding films using a high-temperature polymer
EP1432032A2 (en) * 2002-12-19 2004-06-23 Sel Semiconductor Energy Laboratory Co., Ltd. Semiconductor chip stack and method for manufacturing the same
US20090001602A1 (en) * 2007-06-26 2009-01-01 Qwan Ho Chung Stack package that prevents warping and cracking of a wafer and semiconductor chip and method for manufacturing the same

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06151701A (en) * 1992-11-09 1994-05-31 Sharp Corp Manufacture of semiconductor device
JP2001102523A (en) * 1999-09-28 2001-04-13 Sony Corp Thin-film device and manufacturing method therefor
JP3616872B2 (en) * 2000-09-14 2005-02-02 住友電気工業株式会社 Diamond wafer chip making method
JP4019305B2 (en) 2001-07-13 2007-12-12 セイコーエプソン株式会社 Thin film device manufacturing method
JP3893268B2 (en) * 2001-11-02 2007-03-14 ローム株式会社 Manufacturing method of semiconductor device
JP2003163459A (en) * 2001-11-26 2003-06-06 Sony Corp High frequency circuit block member, its manufacturing method, high frequency module device and its manufacturing method
JP2003229588A (en) 2002-02-01 2003-08-15 Canon Inc Method of manufacturing thin film semiconductor and method of manufacturing solar battery
JP4383274B2 (en) * 2004-06-30 2009-12-16 Ｎｅｃエレクトロニクス株式会社 Semiconductor device and semiconductor wafer manufacturing method
JP2006287118A (en) * 2005-04-04 2006-10-19 Canon Inc Semiconductor device and its manufacturing method
JP2008135553A (en) * 2006-11-28 2008-06-12 Fujitsu Ltd Substrate laminating method and semiconductor device in which substrates are laminated
JP2009092319A (en) 2007-10-10 2009-04-30 Osaka Gas Co Ltd Oil splash prevention device for cooker

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030108715A1 (en) * 2001-12-11 2003-06-12 Intel Corporation Method for bonding and debonding films using a high-temperature polymer
EP1432032A2 (en) * 2002-12-19 2004-06-23 Sel Semiconductor Energy Laboratory Co., Ltd. Semiconductor chip stack and method for manufacturing the same
US20090001602A1 (en) * 2007-06-26 2009-01-01 Qwan Ho Chung Stack package that prevents warping and cracking of a wafer and semiconductor chip and method for manufacturing the same

Also Published As

Publication number Publication date
TW201110311A (en) 2011-03-16
US8871640B2 (en) 2014-10-28
WO2010116698A2 (en) 2010-10-14
JP5409084B2 (en) 2014-02-05
JP2010245290A (en) 2010-10-28
US20120028414A1 (en) 2012-02-02

Similar Documents

Publication Publication Date Title
WO2010116694A3 (en) Method of manufacturing semiconductor device
WO2012048137A3 (en) Flexible circuits and methods for making the same
JP2013004881A5 (en)
CN111357102A (en) Non-embedded silicon bridge chip for multi-chip module
WO2010116698A3 (en) Method of manufacturing semiconductor chip
WO2010111601A3 (en) Methods of forming printable integrated circuit devices and devices formed thereby
EP2267796A3 (en) Separation method of nitride semiconductor layer, semiconductor device, manufacturing method thereof, semiconductor wafer, and manufacturing method thereof
JP2012039090A5 (en)
EP2693472A3 (en) Power semiconductor module and its method of manufacturing
EP1993128A3 (en) Method for manufacturing soi substrate
WO2007021639A3 (en) 3d ic method and device
WO2010104610A8 (en) Stacked microelectronic assembly with microelectronic elements having vias extending through bond pads
JP2011146445A5 (en)
TW200605242A (en) Wafer-level chip scale packaging method
WO2012052257A3 (en) Optoelectronic semiconductor chip and method for the production thereof
EP2058859A3 (en) Wiring substrate and semiconductor device and method of manufacturing the same
WO2009002381A3 (en) Mold compound circuit structure for enhanced electrical and thermal performance
EP2988325A3 (en) Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof
JP2010186847A5 (en)
WO2008122889A3 (en) Front-end processed wafer having through-chip connections
TW200746357A (en) Semiconductor device manufacturing method and semiconductor device
JP2017108019A5 (en)
JP2010199129A5 (en)
WO2012129153A3 (en) Solder in cavity interconnection structures
WO2014025722A3 (en) Method and system for gallium nitride electronic devices using engineered substrates

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13262830

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10719651

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10719651

Country of ref document: EP

Kind code of ref document: A2