JP5943544B2 - Manufacturing method of laminated device and laminated device - Google Patents

Description

  The present invention relates to a manufacturing method of a stacked device in which a plurality of semiconductor devices are stacked, and a stacked device manufactured by the manufacturing method.

  In the manufacturing process of semiconductor devices, devices such as ICs and LSIs are formed in each region partitioned by dividing lines called streets on the surface of the semiconductor wafer. Then, individual semiconductor devices are manufactured by dividing the semiconductor wafer into chips along the planned dividing lines. The semiconductor device manufactured in this way is widely used in various electric appliances.

  In recent years, along with miniaturization and thinning of electrical equipment, semiconductor device packages are also required to be miniaturized and thin, and higher density of packaging is required. One technique for integrating a plurality of semiconductor devices in one package is a three-dimensional mounting in which a plurality of semiconductor device chips are stacked in the vertical direction and mounted.

  In conventional three-dimensional packaging, wire bonding is used to connect between semiconductor device chips or between a semiconductor device chip and an interposer. In connection by wire bonding, inductance and the like increase by the length of the wiring, so that there is a problem that it is not suitable for high-speed signal exchange, and it is necessary to stack chips so that wires do not touch semiconductor device chips and the like Therefore, there are problems such as difficulty in miniaturization.

  In recent years, as a new three-dimensional mounting technique, a mounting technique using a through-silicon via (TSV) instead of a wire has attracted attention. When the TSV technology is used, since the wiring length is shorter than that of the wire, the wiring resistance and inductance can be greatly reduced, and the power consumption can be greatly reduced.

  On the other hand, as a method for laminating semiconductor device chips, the following laminating techniques are being developed. The first stacking method is a stacking method in which a plurality of semiconductor wafers are stacked, a through electrode passing through the stacked semiconductor wafers is formed, and the wafers are connected to each other (Wafer on Wafer: WOW).

  The second stacking method is a method of mounting individual semiconductor device chips on a semiconductor wafer via bumps (Chip on Wafer: COW). Individual laminated device chips are manufactured by dividing a wafer laminated by these lamination methods.

JP 2002-261232 A

  Most semiconductor wafers have a mix of non-defective devices and several defective devices. Therefore, WOW connects semiconductor wafers by stacking multiple semiconductor wafers and forming through electrodes that penetrate the stacked semiconductor wafers. Technology has the problem of poor yield.

  On the other hand, in the COW technology that mounts individual semiconductor device chips on a semiconductor wafer via bumps or the like, the semiconductor device chip is mounted on the semiconductor wafer. The problem arises that there is a risk of damage.

  In addition, laminated device chips connected via bumps and wires are sealed with a liquid curable resin (underfill) for the purpose of increasing strength and improving resistance to humidity and temperature, but the pitch between bumps is narrow. In some cases, it is difficult to inject liquid curable resin.

  The present invention has been made in view of such points, and the object of the present invention is to provide a manufacturing method for manufacturing a thin laminated device without deteriorating the yield and without damaging the semiconductor device chip. Is to provide.

According to the present invention, there is provided a manufacturing method of a stacked device in which a plurality of semiconductor devices are stacked, in which a first semiconductor device is formed in each region partitioned by a plurality of intersecting first streets set on the surface. A semiconductor device wafer preparation step for preparing a device wafer; and a support substrate in which chip mounting regions are formed in each region of a surface partitioned by a plurality of intersecting second streets corresponding to the first streets of the semiconductor device wafer. A support substrate preparation step to be prepared, and mounting of the chip on the support substrate corresponding to the first semiconductor device of the semiconductor device wafer on the surface side of the plurality of semiconductor device chips on which the second semiconductor devices are formed The plurality of semiconductor device chips disposed in the region and disposed on the support substrate A temporary wafer forming step for forming a temporary wafer by filling a resin on the back surface side, and a temporary wafer thinning for grinding the side of the temporary wafer filled with the resin to thin the semiconductor device chip to a predetermined thickness A back surface side of the plurality of semiconductor device chips thinned in the step of thinning the temporary wafer to face the surface of the semiconductor device wafer, and the plurality of semiconductor device chips and the semiconductor device of the temporary wafer A plurality of first semiconductor devices of a wafer are bonded together so as to form a plurality of stacked devices in which a plurality of first semiconductor devices and a plurality of second semiconductor devices are stacked. A bonded wafer forming step to be formed; and the semiconductor substrate by removing the support substrate from the bonded wafer A support substrate removing step of exposing the second semiconductor device of the vice chip; and forming a through electrode in the semiconductor device chip from the surface side of the semiconductor device chip where the second semiconductor device is exposed; individual and through electrode forming step of connecting the second semiconductor device and the semiconductor device wafer of the first semiconductor device, after performing the said through electrode formation step, a the bonded wafer along the first street There is provided a method for manufacturing a laminated device, comprising a dividing step of dividing the laminated device into a plurality of laminated devices.

  According to the method for manufacturing a laminated device of the present invention, after a plurality of semiconductor device chips are arranged on a support substrate and at least filled with a resin between the semiconductor device chips, the semiconductor device chips are thinned by grinding. It is possible to prevent the semiconductor device chip from being damaged.

  In addition, since only the non-defective semiconductor device chip can be selected and disposed on the support substrate to form the bonded wafer, the yield is not deteriorated. Furthermore, since the chip thickness can be reduced as compared with the conventional case, the entire thickness of the laminated device chip can be reduced.

It is a surface side perspective view of a semiconductor device wafer. It is a surface side perspective view of a support substrate concerning one embodiment. It is explanatory drawing which shows a mode that a semiconductor device chip is mounted on a support substrate corresponding to each semiconductor device of a semiconductor device wafer. It is explanatory drawing which shows a mode that two semiconductor device chips are mounted on a support substrate corresponding to each semiconductor device of a semiconductor device wafer. It is a partial cross section side view of the temporary wafer of the state which sealed the some semiconductor device chip mounted on the support substrate with resin. It is a partial cross section side view of the temporary wafer of the state which sealed each semiconductor device chip of the state in which two semiconductor devices were mounted on the support substrate corresponding to each semiconductor device of a semiconductor device wafer. It is a partial cross section side view of the temporary wafer of the state with which resin was filled between the semiconductor device chips mounted on the support substrate. FIG. 8A is an explanatory diagram of a dam formation step for forming the first annular dam on the support substrate, and FIG. 8B is an explanatory diagram of the dam formation step for forming the second dam on the support substrate. It is a principal part perspective view of the grinding device which shows a temporary wafer thinning step. It is a partial cross section side view of the temporary wafer after implementing a temporary wafer thinning step. It is a partial cross section side view which shows a bonding wafer formation step. It is a partial cross section side view of a bonding wafer. It is a partial cross section side view which shows a support substrate removal step. FIG. 14A is a partial cross-sectional side view of a state in which a resist is applied on a semiconductor device chip of a bonded wafer, and FIG. 14B is a diagram of a state in which through holes are formed in each semiconductor device chip of the bonded wafer. FIG. FIG. 15A is a partial cross-sectional side view in which copper is filled in each through hole after removing the resist, and FIG. 15B is a partial cross-sectional side view in which copper on the surface is removed by polishing. is there. It is sectional drawing of the bonding wafer after implementing the back surface grinding process of a semiconductor device wafer. It is sectional drawing which shows a bonding wafer division | segmentation step.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, a front side perspective view of a semiconductor device wafer 2 formed from a silicon wafer is shown. On the surface 2 a of the semiconductor device wafer 2, semiconductor devices 6 (first semiconductor devices) such as ICs and LSIs are formed in respective regions partitioned by a plurality of division lines (streets) 4 formed in a lattice shape. Yes. 2b is the back surface of the semiconductor device wafer 2, and 8 is a notch as a mark indicating the crystal orientation of the silicon wafer.

  Referring to FIG. 2, a front side perspective view of the support substrate 12 of one embodiment is shown. Preferably, the support substrate 12 is formed of a silicon wafer and has the same size as the semiconductor device wafer 2 shown in FIG.

  A plurality of streets 14 are formed in a lattice shape on the surface 12 a of the support substrate 12 corresponding to the streets 4 of the semiconductor device wafer 2, and chip mounting regions 16 are formed in the respective regions partitioned by the streets 14. . Reference numeral 12 b denotes a back surface of the support substrate 12, and reference numeral 18 denotes a notch corresponding to the notch 8 of the semiconductor device wafer 2.

  The support substrate shown in FIG. 2 is formed from the silicon wafer 12, but the support substrate is not limited to this, and may be formed from transparent glass or the like. When the support substrate is formed of glass, when the support substrate is mounted on the semiconductor device wafer 2, the semiconductor device 6 of the semiconductor device wafer 2 can be seen through, so that the street 14 and the chip mounting region 16 are formed on the support substrate. There is no need to form. Further, by forming a scale on the surface 12a of the support substrate 12, the chip mounting area 16 can be determined by the scale.

  After the semiconductor device wafer 2 shown in FIG. 1 and the support substrate 12 shown in FIG. 2 are prepared, in the method for manufacturing a laminated device chip according to the present invention, first, a plurality of semiconductor device chips 20 are mounted on the support substrate 12 and a temporary wafer is mounted. A temporary wafer forming step for forming the wafer is performed.

  In this temporary wafer formation step, as shown in FIG. 3, the surface 20 a side of the plurality of semiconductor device chips 20 on which the semiconductor devices 22 (second semiconductor devices) are formed are placed on the respective semiconductor devices 6 of the semiconductor device wafer 2. It is arranged on the chip mounting area 16 on the support substrate 12 corresponding to the above and bonded with a peelable adhesive.

  At this time, when the support substrate 12 shown in FIG. 2 is used, each chip mounting region 16 of the support substrate 12 is formed at a position corresponding to each device 6 of the semiconductor device wafer 2 shown in FIG. The surface 20a side of the plurality of semiconductor device chips 20 on which is formed may be placed on the chip mounting region 16 of the support substrate 12, and each semiconductor device chip 20 may be bonded to the support substrate 12 with a peelable adhesive.

  In the embodiment shown in FIG. 3, only one semiconductor device chip 20 is mounted on the chip mounting region 16 of the support substrate 12 corresponding to the semiconductor device 6 of the semiconductor device wafer 2, but as shown in FIG. A plurality of, for example, two semiconductor device chips 24 and 28 are mounted on the chip mounting region 16 of the support substrate 12 with the semiconductor devices (second semiconductor devices) 26 and 30 formed on the surface side facing down. May be.

  At this time, when the support substrate 12 faces the semiconductor device wafer 2, the semiconductor device chips 24 and 28 are mounted so as to have a desired arrangement with respect to the semiconductor device 6 of the semiconductor device wafer 2.

  When the semiconductor device chip 20 is mounted on each chip mounting region 16 of the support substrate 12, as shown in FIG. 5, each semiconductor device chip 20 is sealed with a resin 32 such as an epoxy resin, and the temporary wafer 34 is formed. Form. Also in the embodiment shown in FIG. 4, as shown in FIG. 6, the semiconductor device chips 24 and 28 are sealed with a resin 32 such as an epoxy resin to form a temporary wafer 34A.

  In the temporary wafers 34 and 34A shown in FIGS. 5 and 6, all the semiconductor device chips 20 or all the semiconductor device chips 24 and 28 are sealed with the resin 32. However, as shown in FIG. Thus, the temporary wafer 34 ′ may be formed by filling the resin 32 between the adjacent semiconductor device chips 20 without completely sealing the semiconductor device chips 20.

  In this case, the back surface 20 b side of each semiconductor device chip 20 is exposed from the resin 32. At this time, it is preferable to fill the resin 32 up to at least the same thickness as that obtained by grinding the semiconductor device chip 20 or 24 and 28 in a subsequent grinding step.

  When the fluidity of the resin to be injected as the sealing material is high, an annular dam 36 as shown in FIG. 8A surrounding the semiconductor device chip 20 on the outer peripheral edge of the temporary wafer, or shown in FIG. 8B. It is preferable to supply the liquid resin onto the support substrate 12 after the dam 38 is formed. Preferably, the dams 36 and 38 are formed of the same material as the resin 32 serving as a sealing material.

  After the provisional wafer 34 is formed, the provisional wafer 34 is ground so that the back surface 20b of the semiconductor device chip 20 is exposed by grinding the sealing resin 32 side of the provisional wafer 34, and the semiconductor device chip 20 is thinned to a predetermined thickness. Perform the thinning step.

  In the embodiment shown in FIG. 7, in this temporary wafer thinning step, the side of the temporary wafer 34 ′ filled with the resin 32 is ground to thin the semiconductor device chip 20 to a predetermined thickness.

  This provisional wafer thinning step will be described in more detail with reference to FIG. As shown in FIG. 9, the support substrate 12 side of the temporary wafer 34 is sucked and held by the chuck table 40 of the grinding device to expose the sealing resin 32.

  The grinding unit 42 of the grinding apparatus has a spindle 44 that is rotationally driven by a motor (not shown), and a wheel mount 46 is fixed to the tip of the spindle 44. In this wheel mount 46, a grinding wheel 52 constituted by fixing a plurality of grinding wheels 50 in which diamond abrasive grains are hardened by vitrified bond or the like to a free end portion of an annular base 48 is attachable and detachable with screws 54. It is installed.

  In this temporary wafer thinning step, while rotating the chuck table 40 in the direction of arrow a at 300 rpm, for example, the grinding wheel 52 is rotated in the same direction as the chuck table 40, that is, in the direction of arrow b at 6000 rpm, for example. The unit feeding mechanism is driven to bring the grinding wheel 50 into contact with the sealing resin 32 of the temporary wafer 34.

  Then, the grinding wheel 52 is ground by a predetermined amount at a predetermined grinding feed speed, and the temporary wafer 34 is ground. When this grinding is performed, the grinding of only the sealing resin 32 is performed first, but the back surface 20b of the semiconductor device chip 20 is ground simultaneously with the sealing resin 32 from the middle.

  The semiconductor device chip 20 is finished to a desired thickness, for example, 10 μm while measuring the thickness of the semiconductor device chip 20 with a contact type or non-contact type thickness measurement gauge (not shown). FIG. 10 shows a partial sectional side view of the temporary wafer 34 after the provisional wafer thinning step.

  After the provisional wafer thinning step, as shown in FIG. 11, the back surface 20b side of the semiconductor device chip 20 thinned in the provisional wafer thinning step faces the surface 2a of the semiconductor device wafer 2, and the provisional wafer 34 The semiconductor device chip 20 and the semiconductor device 6 of the semiconductor device wafer 2 are made to correspond to each other and bonded together with an adhesive to form a bonded wafer 56.

  FIG. 12 is a partial cross-sectional side view of a bonded wafer 56A in which two semiconductor device chips 24 and 28 of the temporary wafer 34A are bonded to each semiconductor device 6 of the semiconductor device wafer 2.

  Next, as shown in FIG. 13, the support substrate 12 is removed from the bonded wafer 56 to expose the semiconductor device 22 of the semiconductor device chip 20, thereby forming a laminated device wafer 57.

Then forming a through electrode from the surface side of the semiconductor device chip 20 on which the semiconductor device 22 is exposed to the semiconductor device chip 20, connecting the semiconductor device 6 of the semiconductor device 22 and the semiconductor device wafer 2 of the semiconductor device chip 20 through An electrode formation step is performed.

  This through electrode forming step will be described with reference to FIGS. First, as shown in FIG. 14A, a resist 58 is applied on the semiconductor device 22 of the laminated device wafer 57 by spin coating or the like.

  After applying the resist 58, the resist 58 is exposed according to a pattern to form a through electrode forming mask. When dry etching is performed through this through electrode forming mask, a plurality of through holes 60 penetrating each semiconductor device chip 20 are formed as shown in FIG.

  Instead of dry etching, through holes 60 penetrating each semiconductor device chip 20 may be formed by laser beam irradiation. Next, an insulating film and a barrier metal (not shown) are formed in each through hole 60.

  Next, after removing the resist 58, the through holes 60 are filled with copper 62, as shown in FIG. Next, when the copper 62 is polished and planarized by chemical mechanical polishing (CMP), the semiconductor device 22 of the semiconductor device chip 20 and the semiconductor device 6 of the semiconductor device wafer 2 are connected as shown in FIG. A through electrode 63 is formed.

  Although it is preferable to perform a back grinding step of grinding the back surface 2b of the semiconductor device wafer 2 after the through electrode 63 is formed, this back grinding step is not necessarily required. When performing the back surface grinding step, it is preferable to polish the back surface 2b of the semiconductor device wafer 2 to remove grinding distortion.

  In order to perform this back grinding step, it is preferable to attach a protective tape 64 for protecting the semiconductor device 22 to the semiconductor device 22 side of the laminated device wafer 57 as shown in FIG.

  Next, the back surface ground laminated device wafer 57 with the protective tape is attached to the dicing tape T, and the outer periphery of the dicing tape T is attached to the annular frame F. As a result, the laminated device wafer 57 is supported by the annular frame F via the dicing tape T, and is put into the cutting apparatus in this state.

  In the cutting apparatus, after well-known alignment for detecting the street 4 to be cut is performed, the street 4 extending in the first direction is sequentially cut by the cutting blade 68, and then the chuck table of the cutting apparatus is moved 90 degrees. After the rotation, the streets 4 extending in the second direction orthogonal to the first direction are sequentially cut to divide the laminated device wafer 57 into individual laminated device chips.

  This division step is not limited to cutting by the cutting blade 68, but is a full cut by ablation processing that irradiates a conventionally known laser beam, or a cleaving using a braking device after half cut by ablation processing, or a laminated device After the modified layer is formed in the wafer 57, the laminated device wafer 57 may be divided into individual laminated device chips by cleaving using a braking device or the like.

  In the embodiment described above, a laminated device chip in which two devices 6 and 20 are laminated is manufactured. However, in the laminated device chip manufacturing method of the present invention, a laminated device chip in which three or more devices are laminated is similarly used. Can be manufactured.

  In this case, the temporary wafers 34 shown in FIG. 10 are formed one after another, and after the semiconductor device chip 20 side of the temporary wafer 34 is bonded onto the laminated device wafer 57 shown in FIG. To do. Next, the through electrode forming step shown in FIGS. 14 and 15 is performed.

2 Semiconductor device wafer 4 street (division planned line)
6 Device 12 Support substrate 14 Street 16 Chip mounting area 20 Semiconductor device chip 22 Semiconductor device 24, 28 Semiconductor device chip 32 Sealing resin 34 Temporary wafer 36, 38 Dam 56, 56A Bonded wafer 57 Multilayer device wafer 58 Resist 60 Through hole 63 Through electrode 68 Cutting blade

Claims (1)

A method for producing a laminated device in which a plurality of semiconductor devices are laminated,
A semiconductor device wafer preparation step of preparing a semiconductor device wafer in which a first semiconductor device is formed in each region defined by a plurality of intersecting first streets set on the surface;
A support substrate preparation step of preparing a support substrate in which a chip mounting region is formed in each region of a surface partitioned by a plurality of intersecting second streets corresponding to the first streets of the semiconductor device wafer;
The surface side of a plurality of semiconductor device chips having a second semiconductor device formed on the surface is disposed in the chip mounting region on the support substrate corresponding to each first semiconductor device of the semiconductor device wafer, and A temporary wafer forming step of forming a temporary wafer by filling a resin on the back side of the plurality of semiconductor device chips disposed on the support substrate;
A temporary wafer thinning step of grinding the side of the temporary wafer filled with the resin to thin the semiconductor device chip to a predetermined thickness;
The back surfaces of the plurality of semiconductor device chips thinned in the temporary wafer thinning step are made to face the surface of the semiconductor device wafer, and the plurality of semiconductor device chips of the temporary wafer and the semiconductor device wafer A plurality of first semiconductor devices are bonded together to form a bonded bonded wafer so as to form a plurality of stacked devices in which a plurality of first semiconductor devices and a plurality of second semiconductor devices are respectively stacked. A combined wafer forming step;
Removing the support substrate from the bonded wafer to expose the second semiconductor device of the semiconductor device chip; and
A through electrode is formed in the semiconductor device chip from the surface side of the semiconductor device chip where the second semiconductor device is exposed, and the second semiconductor device of the semiconductor device chip and the first semiconductor device of the semiconductor device wafer A through electrode forming step for connecting
After performing the through electrode forming step, a dividing step of dividing the bonded wafer into individual laminated devices along the first street;
The manufacturing method of the laminated device characterized by comprising.

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