JP2010153645A - Method for manufacturing laminated semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a laminated semiconductor device in which a thin film is not damaged by a forming process or the like at the time of thin layer formation, even if the thin layer formation is repeated by laminating the substrate which has the thin film such as a SOI layer. <P>SOLUTION: The method for manufacturing the laminated semiconductor device is provide with stages of: S712 and S722 preparing a first substrate and a second substrate; S714 and S724 bonding a first support member to the surface of the first substrate and bonding the second support member to the surface of the second substrate; S716 and S726 thinning the first substrate and the second substrate by grinding each backside of the first substrate and the second substrate, while supporting the first substrate with the first support member and supporting the second substrate with the second support member; S742 joining the first substrate to the second substrate so that the backside of the first substrate is opposed to the backside of the second substrate; and S744 exposing the surface side of the second substrate by exfoliating the second support member. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a stacked semiconductor device in which a plurality of semiconductor substrates are stacked and bonded.

2. Description of the Related Art A stacked semiconductor device in which a plurality of semiconductor chips are stacked and bonded for the purpose of improving the performance of the semiconductor device without increasing the area is known. For example, Patent Document 1 discloses a method of aligning and laminating wafers on which a plurality of semiconductor devices are formed with high definition. According to the wafer stacking method described in Patent Document 1, after bonding the wafer to the wafer stack, the wafer surface opposite to the circuit surface is ground and polished to reduce the thickness.
JP 2006-1006006 A

  On the other hand, a semiconductor element may be formed on an SOI substrate having an SOI (silicon-on-insulator) layer for the purpose of improving the operation speed of the semiconductor device. However, the SOI layer is as thin as about 50 to 150 nm. If the thinning is repeated each time a substrate having a thin film such as an SOI layer is stacked, the thin film may be damaged by a processing process at the time of thinning.

  In order to solve the above problems, in the first aspect of the present invention, a step of preparing a first substrate and a second substrate, a first surface of the first substrate is attached to a first support member, and a second support is provided. A step of attaching one surface of the second support member to the member; and supporting the first substrate by the first support member and supporting the second substrate by the second support member. Provided is a method of manufacturing a laminated semiconductor device, comprising: thinning the first substrate and the second substrate by polishing each of the first substrate and the thinned first substrate and the second substrate; Is done.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 schematically shows an example of a cross section of the substrate bonding apparatus 200. The substrate bonding apparatus 200 manufactures a three-dimensional stacked semiconductor substrate by, for example, bonding the SOI substrate 120 and the SOI substrate 150 by applying pressure and heating. The substrate bonding apparatus 200 includes, for example, a frame body 210, a pressing unit 220 arranged inside the frame body 210, a pressure stage 230, a pressure receiving stage 240, and a pressure detection unit 250.

  The frame body 210 includes a top plate 212 and a bottom plate 216 that are parallel and horizontal to each other, and a plurality of columns 214 that couple the top plate 212 and the bottom plate 216. The top plate 212, the support column 214, and the bottom plate 216 have such a rigidity that deformation does not occur when a reaction force against pressure is applied to the SOI substrate 120 or the SOI substrate 150.

  The pressing part 220 is disposed on the bottom plate 216 inside the frame body 210. The pressing portion 220 includes a cylinder 222 fixed to the upper surface of the bottom plate 216 and a piston 224 that is disposed inside the cylinder 222 and moves up and down in a direction perpendicular to the bottom plate 216 (shown in the Z direction in the drawing). Have.

  The pressure stage 230 is mounted on the upper end of the piston 224. The pressure stage 230 includes a horizontal plate-like support portion 232 coupled to the upper end of the piston 224 and a plate-like first substrate holding portion 234 parallel to the support portion 232.

  The first substrate holding unit 234 is supported by the support unit 232 via a plurality of actuators 235. In addition to the pair of actuators 235 shown in the figure, the actuator 235 is also arranged forward and backward with respect to the paper surface. Each of these actuators 235 can be operated independently of each other. With such a structure, the inclination of the first substrate holding part 234 can be arbitrarily changed by appropriately operating the actuator 235. The first substrate holding unit 234 includes a heater 236 and is heated by the heater 236.

  The first substrate holding unit 234 attracts the support member 350 to the upper surface thereof by electrostatic adsorption, vacuum adsorption, or the like. The first substrate holding unit 234 sucks the surface of the support member 350 where the SOI substrate 150 is not attached. As a result, the support member 350 and the SOI substrate 150 swing together with the first substrate holding part 234, while the support member 350 and the SOI substrate 150 are prevented from moving or dropping from the first substrate holding part 234.

  The pressure receiving stage 240 includes a second substrate holding part 242 and a plurality of suspension parts 244. The suspension portion 244 is suspended from the lower surface of the top plate 212. The second substrate holding unit 242 is supported from below in the vicinity of the lower end of the suspension unit 244 and is disposed to face the pressure stage 230. The pressure receiving stage 240 has a heater 246 and is heated by the heater 246.

  The second substrate holding part 242 is supported by the suspension part 244 from below, but the upward movement is not restricted. However, a plurality of load cells 252, 254 and 256 are sandwiched between the top plate 212 and the second substrate holding part 242. The plurality of load cells 252, 254, 256 form a part of the pressure detection unit 250, regulate upward movement of the second substrate holding unit 242, and are applied upward to the second substrate holding unit 242. Detect pressure.

  The second substrate holding unit 242 attracts the support member 320 to the lower surface thereof by electrostatic adsorption, vacuum adsorption, or the like. The second substrate holding unit 242 sucks the surface of the support member 320 on which the SOI substrate 120 is not attached. As a result, the support member 320 and the SOI substrate 120 swing together with the second substrate holding part 242, while the support member 320 and the SOI substrate 120 are prevented from moving or dropping from the second substrate holding part 242.

  In the state shown in FIG. 1, the support column 214 of the pressing unit 220 is drawn into the cylinder 222, and the pressure stage 230 is lowered. Therefore, there is a wide gap between the pressure stage 230 and the pressure receiving stage 240.

  Among the pair of SOI substrates 120 and SOI substrates 150 to be bonded, one SOI substrate 150 is inserted into the gap from the side in a state of being attached to the support member 350, and is a pressure stage. 230. Similarly, the other SOI substrate 120 is inserted from the side into the gap, and held on the pressure receiving stage 240 so as to face the SOI substrate 150. The SOI substrate 120 may be inserted into the substrate bonding apparatus 200 with the support member 320 attached, or may be inserted into the substrate bonding apparatus 200 with the support member 320 not attached. May be.

  As shown in FIG. 1, a support member 320 may be attached to one surface of the SOI substrate 120. Similarly, a support member 350 may be attached to one surface of the SOI substrate 150. The support member 320 and the support member 350 are each attached to the SOI substrate 120 or the SOI substrate 150 with, for example, a UV curable liquid adhesive. In the present embodiment, the surface of the SOI substrate 120 where the support member 320 is not attached is bonded to the surface of the SOI substrate 150 where the support member 350 is not attached. Further, as shown in FIG. 1, in this embodiment, the diameters of the SOI substrate 120 and the SOI substrate 150 may be smaller than the diameters of the support member 320 and the support member 350.

  The SOI substrate 120 and the SOI substrate 150 are aligned with each other in a plane orthogonal to the Z direction. The alignment between the SOI substrate 120 and the SOI substrate 150 may be performed by the substrate bonding apparatus 200, or the SOI substrate 120 and the SOI substrate 150 aligned by another alignment apparatus are the substrate bonding apparatus. 200 may be conveyed.

  When the SOI substrate 120 and the SOI substrate 150 are aligned by the substrate bonding apparatus 200, for example, the pressing unit 220 is configured so that the first substrate holding unit 234 and the second substrate holding unit 242 have a horizontal direction and a rotational direction ( The relative position in the vertical direction may be adjusted.

  In this case, the pressing part 220 is driven by, for example, an elastic deformation body, a piezoelectric element or the like (not shown), and the relative position between the first substrate holding part 234 and the second substrate holding part 242 is set to submicron, nanometer. You may adjust precisely in units. The pressing unit 220 is driven by, for example, a servo motor (not shown), a feed screw, or the like, and roughly adjusts the relative position between the first substrate holding unit 234 and the second substrate holding unit 242 with a large stroke and low resolution. It's okay. The pressing unit 220 may execute the fine adjustment after the coarse adjustment.

  After the SOI substrate 120, the support member 320, the SOI substrate 150, and the support member 350 are arranged at predetermined positions of the substrate bonding apparatus 200, the pressure stage 230 rises toward the pressure receiving stage 240, and the SOI substrate 120. And the SOI substrate 150 are pressed. Further, the heaters 246 and 236 heat the pressure stage 230 and the pressure receiving stage 240 during pressing. Thereby, the SOI substrate 120 and the SOI substrate 150 are joined.

  FIG. 2 schematically shows an example of a cross section of the laminated semiconductor substrate 110. In the present embodiment, the laminated semiconductor substrate 110 is obtained by laminating an SOI substrate 120 and an SOI substrate 150. The SOI substrate 120 may be an example of a first substrate. The SOI substrate 150 may be an example of a second substrate.

  The SOI substrate 120 includes a substrate body 132, an insulating layer 134, and an SOI layer 136 formed in contact with the insulating layer 134 in this order. The substrate body 132 may be a silicon substrate, for example. The SOI substrate 120 may have a through hole 123 penetrating between the front surface 121 and the back surface 129 of the SOI substrate 120. The through hole 123 may be an example of a through hole. The SOI substrate 120 may have an alignment mark 124 on the surface 121.

  The SOI substrate 120 may have a plurality of semiconductor chips 122. The semiconductor chip 122 includes a semiconductor element 127 formed in the SOI layer 136, a bump 128 that electrically couples the semiconductor element 127 and another semiconductor element, and an embedded that electrically couples the semiconductor element 127 and the bump 128. An electrode 126 may be included. The buried electrode 126 is at least partially formed inside the through hole 123 and electrically couples the front surface 121 and the back surface 129. The embedded electrode 126 may be an example of a through coupling part.

  The SOI substrate 150 may have a configuration similar to that of the SOI substrate 120. The SOI substrate 150 includes a substrate body 162, an insulating layer 164, and an SOI layer 166 formed in contact with the insulating layer 164 in this order. The substrate body 162 may be a silicon substrate, for example. The SOI substrate 150 may have a through hole 153 that penetrates between the front surface 151 and the back surface 159 of the SOI substrate 150. The through hole 153 may be an example of a through hole. The SOI substrate 150 may have an alignment mark 154 on the surface 151.

  The SOI substrate 150 may include a plurality of semiconductor chips 152. The semiconductor chip 152 may have a configuration similar to that of the semiconductor chip 122. In the present embodiment, the semiconductor chip 152 includes a buried electrode 156, a semiconductor element 157, and a bump 158. Since the embedded electrode 156, the semiconductor element 157, and the bump 158 have the same configuration as the embedded electrode 126, the semiconductor element 127, and the bump 128, respectively, description thereof is omitted.

  As shown in FIG. 2, the SOI substrate 120 and the SOI substrate 150 are bonded so that the back surface 129 of the SOI substrate 120 and the back surface 159 of the SOI substrate 150 face each other. Thereby, the bump 128 formed on the back surface 129 of the SOI substrate 120 and the bump 158 formed on the back surface 159 of the SOI substrate 150 are electrically coupled. Further, the semiconductor chip 122 formed on the SOI substrate 120 and the semiconductor chip 152 formed on the SOI substrate 150 are stacked, and the stacked semiconductor device 100 is obtained.

  For example, the laminated semiconductor substrate 110 is formed by adjusting the relative positions of the SOI substrate 120 and the SOI substrate 150 so that the bumps 128 and the bumps 158 are bonded using the substrate bonding apparatus 200. It is obtained by being bonded to the SOI substrate 150. A plurality of stacked semiconductor devices 100 may be formed on the stacked semiconductor substrate 110. Each laminated semiconductor device 100 is obtained by cutting the laminated semiconductor substrate 110 by dicing or the like.

  As shown in FIG. 2, the SOI substrate 120 and the SOI substrate 150 are surfaces on which the support member 320 is attached to the surface 121 of the SOI substrate 120 where the SOI layer 136 is formed, and the SOI layer 166 of the SOI substrate 150 is formed. 151 may be bonded in a state in which the support member 350 is bonded. An alignment index 326 and an index 356 may be formed on the support member 320 and the support member 350, respectively. At least one of the support member 320 and the support member 350 may be a silicon support member such as a silicon wafer, or a glass substrate. The support member 320 may be an example of a first support member. The support member 350 may be an example of a second support member.

  In the present embodiment, the support member 320 and the support member 350 are attached to the surface 121 of the SOI substrate 120 and the surface 151 of the SOI substrate 150, and the back surface 129 of the SOI substrate 120 and the back surface 159 of the SOI substrate 150 are formed. The case where the SOI substrate 120 and the SOI substrate 150 are bonded so as to face each other has been described. However, the bonding method of the SOI substrate 120 and the SOI substrate 150 is not limited to this.

  For example, the support member 320 may be attached to the front surface 121 of the SOI substrate 120, and the back surface 129 of the SOI substrate 120 and the front surface 151 of the SOI substrate 150 may be attached to face each other. Further, a support member 350 may be attached to the surface 151 of the SOI substrate 150, and may be attached so that the surface 121 of the SOI substrate 120 and the back surface 159 of the SOI substrate 150 face each other. Alternatively, the surface 121 of the SOI substrate 120 and the surface 151 of the SOI substrate 150 may be bonded to face each other.

  In the present embodiment, the through hole 123, the through hole 153, the embedded electrode 126, and the embedded electrode 156 are formed on the SOI substrate 120 or the SOI substrate 150 before the step of bonding the SOI substrate 120 and the SOI substrate 150. However, the present invention is not limited to this. For example, the through hole 123, the through hole 153, the embedded electrode 126, and the embedded electrode 156 may be formed after the step in which the SOI substrate 120 and the SOI substrate 150 are joined.

At this time, the SOI substrate 120 and the SOI substrate 150 may be bonded via the bump 128 and the bump 158, or may be bonded without the bump 128 and the bump 158. For example, the SOI substrate 120 and the SOI substrate 150 may be formed with the through hole 123, the through hole 153, the embedded electrode 126, and the embedded electrode 156 after the protective films formed on the opposing surfaces are bonded to each other. The protective film may be, for example, an oxide film such as SiO ₂ or a polyimide film. In addition, the SOI substrate 120 and the SOI substrate 150 may be bonded with a resin formed on the opposing surfaces, and then the through hole 123, the through hole 153, the embedded electrode 126, and the embedded electrode 156 may be formed. The resin may be, for example, a BCB resin (manufactured by Dow Chemical Company).

  FIG. 3 schematically shows an example of a cross section of the laminated semiconductor substrate 610. In the present embodiment, the laminated semiconductor substrate 610 is obtained by laminating the laminated semiconductor substrate 110 and the SOI substrate 150. As shown in FIG. 3, in the laminated semiconductor substrate 110 and the SOI substrate 150, the front surface 151 of the SOI substrate 150 constituting the laminated semiconductor substrate 110 and the back surface 159 of the SOI substrate 150 bonded to the laminated semiconductor substrate 110 face each other. , Joined. Thereby, the bump 118 formed on the front surface 151 of the SOI substrate 150 constituting the laminated semiconductor substrate 110 and the bump 158 formed on the back surface 159 of the SOI substrate 150 bonded to the laminated semiconductor substrate 110 are electrically coupled. Is done. In addition, the semiconductor chip 122 and the semiconductor chip 152 formed on the stacked semiconductor substrate 110 and the semiconductor chip 152 formed on the SOI substrate 150 are stacked, whereby the stacked semiconductor device 600 is obtained.

  The laminated semiconductor substrate 610 is bonded using the substrate bonding apparatus 200, for example, similarly to the laminated semiconductor substrate 110. A plurality of stacked semiconductor devices 600 may be formed on the stacked semiconductor substrate 610. Each laminated semiconductor device 600 is obtained by cutting the laminated semiconductor substrate 610 by dicing or the like.

  FIG. 4 shows an example of a method for manufacturing the laminated semiconductor device 600. As described with reference to FIG. 3, the stacked semiconductor device 600 is obtained by cutting the stacked semiconductor substrate 610. The laminated semiconductor substrate 610 includes an SOI substrate 120 as an example of a first substrate, an SOI substrate 150 as an example of a second substrate, and an SOI substrate 150 as an example of a third substrate in this order. The laminated semiconductor substrate 610 can be manufactured using the substrate bonding apparatus 200, for example. Hereinafter, a method for manufacturing a stacked semiconductor device will be described by taking as an example a stacked semiconductor device 600 obtained by stacking the semiconductor chip 122, the semiconductor chip 152, and the semiconductor chip 152 in this order.

  In this embodiment, in S712, an SOI substrate 120 is prepared as an example of the first substrate. In S722 and S732, a plurality of SOI substrates 150 are prepared as examples of the second substrate and the third substrate.

  The SOI substrate 120 can be prepared by the following procedure, for example. First, an SOI substrate having the substrate body 132, the insulating layer 134, and the SOI layer 136 in this order is prepared. The SOI substrate may be a commercially available SOI substrate.

  The alignment mark 124 and the semiconductor element 127 are formed on the SOI layer 136 using a semiconductor manufacturing process. After the through hole 123 is formed in the SOI substrate by laser processing or the like, a buried electrode 126 is formed in the through hole 123 by a plating method, and the SOI substrate 120 is obtained. In addition, the outer periphery of the SOI substrate 120 may be trimmed. Thereby, the diameter of the SOI substrate 120 becomes smaller than the diameter of the commercially available SOI substrate. Thus, the SOI substrate 120 is prepared. The SOI substrate 150 may be prepared in the same manner as the SOI substrate 120.

  In S <b> 714, a support member 320 that is an example of a first support member is attached to the surface 121 of the SOI substrate 120. Similarly, in S724 and S734, a support member 350, which is an example of a second support member and a third support member, is attached to the surface 151 of each SOI substrate 150. Note that an index 326 may be formed in a region of the support member 320 where the SOI substrate 120 is not attached. The indicator 326 may be formed before the support member 320 is attached to the SOI substrate 120, or may be formed after the support member 320 is attached to the SOI substrate 120. Similarly, an index 356 may be formed in a region of the support member 350 where the SOI substrate 150 is not attached.

  In S716, the back surface 129 of the SOI substrate 120 is polished in a state where the SOI substrate 120 is supported by the support member 320. Thereby, the substrate main body 132 of the SOI substrate 120 is polished, and the SOI substrate 120 can be thinned. Further, the embedded electrode 126 is exposed on the polished surface of the SOI substrate 120. The back surface 129 of the SOI substrate 120 may be polished by, for example, a grindstone used in a back grinding process, or may be polished by a CMP method.

In S716, a protective film and bumps 128 may be formed on the polished surface of the SOI substrate 120. The protective film may be an insulating film such as a polyimide film or a SiO ₂ film. In FIG. 4, the protective film is not shown. The bump 128 may be formed in an opening formed by patterning a protective film by a photolithography method, for example, by reflow, plating, or vacuum deposition.

  In S726 and S736, the back surface 159 of the SOI substrate 150 is polished in a state where each SOI substrate 150 is supported by the support member 350, similarly to S716. Thereby, the substrate body 162 of the SOI substrate 150 is polished, and the SOI substrate 150 can be thinned. Further, the embedded electrode 156 is exposed on the polished surface of the SOI substrate 150. Similar to the SOI substrate 120, a protective film and bumps 158 may be formed on the polished surface of the SOI substrate 150.

  In S742, the SOI substrate 120 and the SOI substrate 150 are bonded. The SOI substrate 120 and the SOI substrate 150 are bonded so that the embedded electrode 126 and the embedded electrode 156 are electrically coupled to each other. In the present embodiment, the embedded electrode 126 and the embedded electrode 156 are electrically coupled via the bump 128 and the bump 158.

  In S742, the SOI substrate 120 and the SOI substrate 150 can be bonded using the substrate bonding apparatus 200, for example. The substrate bonding apparatus 200 may bond the SOI substrate 120 and the SOI substrate 150 after adjusting the relative positions of the SOI substrate 120 and the SOI substrate 150 so that the bump 128 and the bump 158 are bonded. The substrate bonding apparatus 200 may adjust the relative positions of the SOI substrate 120 and the SOI substrate 150 using, for example, the alignment mark 124, the alignment mark 154, the index 326 of the support member 320, and the index 356 of the support member 350.

  In the illustrated example, in S742, the SOI substrate 120 and the SOI substrate 150 are bonded to each other while being supported by the support member 320 or the support member 350, respectively. In this case, after the SOI substrate 120 and the SOI substrate 150 are polished in S716 and S726, the SOI substrate 120 and the SOI substrate 150 are not peeled off from the support member 320 or the support member 350. May be joined.

  For example, when the steps S716 and S726 are performed by the polishing apparatus and then the step S742 is performed by the substrate bonding apparatus, the support member 320 and the support member 350 used in S716 and S726 are separated from each other. The SOI substrate 120 and the SOI substrate 150 may be transferred from the polishing apparatus to the substrate bonding apparatus 200 without replacing the SOI substrate 120 and the SOI substrate 150.

  Instead, for example, when the steps S716 and S726 are performed by the polishing apparatus and then the step S742 is performed by the substrate bonding apparatus, the SOI substrate 120 and the SOI substrate 150 are used in S716 and S726, respectively. The support member 320 and the support member 350 may be replaced with another support member, and the SOI substrate 120 and the SOI substrate 150 supported by the other support member may be bonded to each other.

  In step S <b> 744, the support member 350 attached to the SOI substrate 150 attached to the SOI substrate 120 is peeled from the surface 151 of the SOI substrate 150. As a result, the surface 151 of the SOI substrate 150 is exposed. Thus, the laminated semiconductor substrate 110 is obtained.

  By adopting the above configuration, damage to the SOI layer 136 and the SOI layer 166 can be suppressed. In other words, stress is applied to the SOI layer 136 and the SOI layer 166 as the SOI substrate 120 and the SOI substrate 150 are thinned. Since the SOI layer 136 and the SOI layer 166 are very thin, the SOI layer 136 and the SOI layer 166 may be damaged when the stress is repeatedly applied.

  However, in the present embodiment, the thinning process is performed only once on the SOI substrate 120 and the SOI substrate 150 in the manufacturing process of the laminated semiconductor substrate 110. As a result, the stress applied to the SOI layer 136 can be reduced as compared with the case where the back surface 159 of the SOI substrate 150 is polished after the SOI substrate 120 and the SOI substrate 150 are bonded.

In S <b> 744, the protective film and the bump 118 may be formed on the exposed surface 151 of the SOI substrate 150. The protective film may be an insulating film such as a polyimide film or a SiO ₂ film. The bump 118 has the same configuration as the bump 128 and may be formed by the same method.

  In S752, the laminated semiconductor substrate 110 and another SOI substrate 150 are bonded. In the present embodiment, the SOI substrate 150 included in the stacked semiconductor substrate 110 and another SOI substrate 150 are bonded. The other SOI substrate 150 may be an example of a third substrate. The SOI substrate 150 and the other SOI substrate 150 included in the stacked semiconductor substrate 110 are bonded so that the respective embedded electrodes 156 are electrically coupled to each other.

  In the present embodiment, each embedded electrode 156 is electrically coupled via the bump 118 and the bump 158. The laminated semiconductor substrate 110 and the SOI substrate 150 can be bonded using the substrate bonding apparatus 200 in the same manner as in the case of forming the laminated semiconductor substrate 110, for example.

  In S <b> 754, the support member 350 attached to the SOI substrate 150 attached to the laminated semiconductor substrate 110 is peeled from the surface 151 of the SOI substrate 150. As a result, the surface 151 of the SOI substrate 150 is exposed. Thus, the laminated semiconductor substrate 610 is obtained.

Note that a plurality of SOI substrates 150 may be stacked by repeating the processes of S752 and S754 a plurality of times. At this time, a protective film and a bump may be formed on the surface 151 of the last stacked SOI substrate 150. The protective film may be an insulating film such as a polyimide film or a SiO ₂ film. The bump may have the same configuration as the bump 118 and may be formed by the same method.

  In the present embodiment, the case where the same SOI substrate 150 is repeatedly stacked has been described. However, the present invention is not limited to this. For example, different types of SOI substrates may be stacked. In this embodiment, the stacked semiconductor substrate and the SOI substrate 150 are bonded so that the back surface of the stacked semiconductor substrate on which a plurality of SOI substrates are stacked faces the back surface of the SOI substrate 150 that is stacked last. However, the lamination method is not limited to this. For example, the stacked semiconductor substrate and the SOI substrate 150 may be bonded so that the back surface of the stacked semiconductor substrate faces the front surface of the SOI substrate 150. In this case, the last stacked SOI substrate may not have a thinned substrate body, and the last stacked substrate may not be an SOI substrate.

  In the present embodiment, before the step of bonding the SOI substrate 120 and the SOI substrate 150 in S742 or before the step of bonding the stacked semiconductor substrate 110 and the SOI substrate 150 in S752, Although the case where the hole 153, the embedded electrode 126, and the embedded electrode 156 are formed in the SOI substrate 120 or the SOI substrate 150 has been described, the present invention is not limited to this. For example, the through hole 123, the through hole 153, the embedded electrode 126, and the embedded electrode 156 are formed after the step in which the SOI substrate 120 and the SOI substrate 150 are bonded in S742 or in the stacked semiconductor substrate 110 and the SOI substrate 150 in S752. May be formed after the step of bonding.

At this time, the SOI substrate 120 and the SOI substrate 150 may be bonded via the bump 128 and the bump 158, or may be bonded without the bump 128 and the bump 158. For example, the SOI substrate 120 and the SOI substrate 150 may be formed with the through hole 123, the through hole 153, the embedded electrode 126, and the embedded electrode 156 after the protective films formed on the opposing surfaces are bonded to each other. The protective film may be, for example, an oxide film such as SiO ₂ or a polyimide film. In addition, the SOI substrate 120 and the SOI substrate 150 may be bonded with a resin formed on the opposing surfaces, and then the through hole 123, the through hole 153, the embedded electrode 126, and the embedded electrode 156 may be formed. The resin may be, for example, a BCB resin (manufactured by Dow Chemical Company).

  By adopting the above configuration, damage to the SOI layer 136 and the SOI layer 166 can be suppressed. That is, in the manufacturing process of the laminated semiconductor substrate 610, the number of times stress is applied to the SOI layer 136 and the SOI layer 166 can be reduced by thinning the SOI substrate 120 or the SOI substrate 150. In addition, a substrate that forms a stacked semiconductor substrate such as the SOI substrate 120 or the SOI substrate 150 can be thinned in advance, and the thinned substrate can be stacked in accordance with the stacked semiconductor substrate to be manufactured. That is, by adopting the above configuration, it is possible to provide a method for manufacturing a laminated semiconductor substrate or a laminated semiconductor device excellent in mass productivity.

  The stacked semiconductor substrate 610 may include a plurality of stacked semiconductor devices 600. Therefore, after forming a plurality of laminated semiconductor substrates 610, the laminated semiconductor substrate 610 may be cut into a plurality of laminated semiconductor devices 600 by dicing or the like. As described above, the stacked semiconductor device 600 is obtained.

  FIG. 5 shows the SOI substrate 120 and the support member 320 described with reference to S714 of FIG. In FIG. 5, the support member 320 is attached to the surface 121 of the SOI substrate 120 on which the SOI layer 136 is formed.

  FIG. 6 shows the SOI substrate 120 and the support member 320 described in relation to S716 in FIG. In FIG. 6, the back surface 129 of the SOI substrate 120 is polished while the SOI substrate 120 is supported by the support member 320. The dotted line indicates the polished part.

  FIG. 7 shows the SOI substrate 120 and the SOI substrate 150 described in S742 of FIG. 4 together with the support member 320 and the support member 350. In FIG. 7, the SOI substrate 120 and the SOI substrate 150 are joined so that the embedded electrode 126 and the embedded electrode 156 are electrically coupled to each other.

  FIG. 8 shows the SOI substrate 120 and the SOI substrate 150 described in S744 of FIG. In FIG. 8, the support member 350 is peeled off, and the surface 151 of the SOI substrate 150 is exposed.

  FIG. 9 shows the stacked semiconductor substrate 110 and the SOI substrate 150 described in S752 of FIG. 4 together with the support member 320 and the support member 350. In FIG. 9, in the laminated semiconductor substrate 110 and the SOI substrate 150, the embedded electrode 156 of the SOI substrate 150 included in the laminated semiconductor substrate 110 and the embedded electrode 156 of the SOI substrate 150 bonded to the laminated semiconductor substrate 110 are electrically connected to each other. Are joined together.

  FIG. 10 shows the laminated semiconductor substrate 610 together with the support member 320 described in S754 of FIG. In FIG. 10, the support member 350 is peeled off, and the surface 151 of the SOI substrate 150 is exposed. Thereby, the laminated semiconductor substrate 110 is obtained.

  In the example illustrated in FIGS. 2 to 10, the case where the SOI substrate 120 and the SOI substrate 150 are bonded so that the polished surfaces face each other is described. The bonding method is not limited to this. For example, instead of this, the SOI substrate 120 and the SOI substrate 150 may be bonded so that the polished surface of one substrate and the unpolished surface of the other substrate face each other.

  When joining the SOI substrate 120 and the SOI substrate 150 so that the polished surface of one substrate and the unpolished surface of the other substrate face each other, for example, the following procedure is used to An unpolished surface may be exposed. First, after polishing one surface of the other substrate, the other substrate is once peeled from the support member before being bonded to the one substrate. Next, the other substrate may be reversed and the polished surface may be attached to the support member used during polishing. As a result, the unpolished surface of the other substrate is exposed.

  As another example of exposing the unpolished surface of the other substrate, in the above example, after the other substrate is once peeled off from the support member, it is supported separately from the support member used at the time of polishing. It may be replaced with a member. For example, after the other substrate is once peeled off from the support member, the other substrate may be reversed and the polished surface may be attached to a dedicated support member for bonding.

  As another example of the method for bonding the SOI substrate 120 and the SOI substrate 150, the SOI substrate 120 and the SOI substrate 150 may be bonded so that the unpolished surfaces face each other. In this case, for example, the unpolished surface of each substrate may be exposed by the following procedure. First, after polishing one surface of each substrate, each substrate is once peeled off from the support member before the substrates are bonded together. Next, each of the peeled substrates is inverted, and the polished surface is attached to the support member used at the time of polishing. This exposes the unpolished surface of each substrate.

  In the above example, the case where the SOI substrate 120 and the SOI substrate 150 are once peeled and then attached again to the supporting member used at the time of polishing is described, but the present invention is not limited to this. For example, one of the SOI substrate 120 and the SOI substrate 150 may be attached again to the support member used at the time of polishing, and the other may be replaced with a dedicated support member for bonding. Further, both the SOI substrate 120 and the SOI substrate 150 may be replaced with a dedicated support member for bonding.

  FIG. 11 schematically shows an example of a cross section of a laminated semiconductor substrate 1110 according to another embodiment. The stacked semiconductor substrate 1110 is obtained by stacking a stacked semiconductor substrate 110 and an SOI substrate 1150. The SOI substrate 1150 includes, for example, a substrate body 1162, an insulating layer 1164, and an SOI layer 1166 formed in contact with the insulating layer 1164 in this order. The SOI substrate 1150 may be an example of a fourth substrate. The substrate body 1162 may be a silicon substrate, for example. The SOI substrate 1150 may include a plurality of semiconductor chips 1152.

  The semiconductor chip 1152 may have a configuration similar to that of the semiconductor chip 122 or the semiconductor chip 152. The semiconductor chip 1152 may include a semiconductor element 1157 and bumps 1158. The semiconductor element 1157 and the bump 1158 may have the same configuration as the semiconductor element 127 and the bump 128, respectively, and description thereof will be omitted.

  As illustrated in FIG. 11, the stacked semiconductor substrate 1110 and the SOI substrate 1150 include bumps 118 formed on the surface 151 of the SOI substrate 150 constituting the stacked semiconductor substrate 110, and bumps 1158 formed on the surface 1151 of the SOI substrate 1150. It is joined via. Thereby, the semiconductor chip 122 and the semiconductor chip 152 formed on the stacked semiconductor substrate 110 and the semiconductor chip 1152 formed on the SOI substrate 1150 are stacked, and the stacked semiconductor device 1100 is obtained.

  The laminated semiconductor substrate 1110 is bonded using the substrate bonding apparatus 200, for example, similarly to the laminated semiconductor substrate 110. In this case, the substrate body 1162 of the SOI substrate 1150 may not be thinned from the back surface 1159 side. A plurality of stacked semiconductor devices 1100 may be formed on the stacked semiconductor substrate 1110. Each laminated semiconductor device 1100 is obtained by cutting the laminated semiconductor substrate 1110 by dicing or the like.

  Note that one or more SOI substrates may be stacked between the SOI substrate 150 and the SOI substrate 1150 as in the case of the stacked semiconductor device 600. In this case, the SOI substrate 1150 includes the other SOI through bumps formed on the surface of another SOI substrate stacked on the SOI substrate 150 and bumps 1158 formed on the surface 1151 of the SOI substrate 1150. Bonded to the substrate. Similarly to the case of the stacked semiconductor device 600, the through hole 123, the through hole 153, the embedded electrode 126, and the embedded electrode 156 may be formed before the step of bonding the stacked semiconductor substrate 110 and the SOI substrate 1150. . Further, the through hole 123, the through hole 153, the embedded electrode 126, and the embedded electrode 156 may be formed after the step of bonding the laminated semiconductor substrate 110 and the SOI substrate 1150.

  FIG. 12 shows another example of a method for manufacturing a laminated semiconductor device. This embodiment is different from the manufacturing method of the stacked semiconductor device described with reference to FIG. 4 in that the steps S714 and S716 are not included. That is, in this embodiment, the SOI substrate 120 is not thinned. In this embodiment, the support member 320 that supports the SOI substrate 120 is not attached to the SOI substrate 120. Note that the SOI substrate 120 may be thinned, and a support member 320 may be attached to the SOI substrate 120.

  Hereinafter, the method for fabricating the stacked semiconductor device according to the present embodiment will be explained with reference to FIGS. In the following description, the description of the same configuration as the manufacturing method described with reference to FIG. 4 may be omitted.

  FIG. 13 shows an example of a cross section in the manufacturing process by the manufacturing method of the laminated semiconductor device described in relation to FIG. FIG. 13 shows the SOI substrate 120 in S712 of FIG. As shown in the figure, an SOI substrate 120 having a substrate body 132, an insulating layer 134, and an SOI layer 136 in contact with the insulating layer 134 is prepared. At this time, a protective film and bumps may be formed on the surface 121 of the SOI substrate 120 in the same manner as described in relation to S716 in FIG.

  FIG. 14 shows an example of a cross-section in the manufacturing process by the manufacturing method of the stacked semiconductor device described in relation to FIG. FIG. 14 shows the SOI substrate 150 in S726 and S736 of FIG. As shown in the figure, the back surface 159 of the SOI substrate 150 is polished while the SOI substrate 150 is supported by the support member 350. The dotted line indicates the polished part.

  FIG. 15 shows an example of a cross section in the manufacturing process by the manufacturing method of the stacked semiconductor device described in relation to FIG. FIG. 15 shows the SOI substrate 120 and the SOI substrate 150 in S742 of FIG. As shown in the figure, in this embodiment, the SOI substrate 120 and the SOI substrate 150 are bonded so that the front surface 121 of the SOI substrate 120 and the back surface 159 of the SOI substrate 150 face each other. In the figure, an SOI substrate 120 and an SOI substrate 150 are joined so that an embedded electrode 126 and an embedded electrode 156 are electrically coupled to each other. Thereby, the laminated semiconductor substrate 720 can be formed.

  FIG. 16 shows an example of a cross-section in the manufacturing process by the method for manufacturing a laminated semiconductor device described in relation to FIG. FIG. 16 shows the stacked semiconductor substrate 720 in S744 of FIG. In the drawing, the support member 350 attached to the SOI substrate 150 attached to the SOI substrate 120 is peeled off from the surface 151 of the SOI substrate 150. As a result, the surface 151 of the SOI substrate 150 is exposed. As described above, the laminated semiconductor substrate 720 is obtained.

  FIG. 17 shows an example of a cross section in the manufacturing process by the manufacturing method of the laminated semiconductor device described in relation to FIG. FIG. 17 shows the stacked semiconductor substrate 720 and the SOI substrate 150 in S752 of FIG. The SOI substrate 150 may be an example of a third substrate. In the figure, the laminated semiconductor substrate 720 and the SOI substrate 150 are configured such that an embedded electrode 156 of the SOI substrate 150 included in the laminated semiconductor substrate 720 and an embedded electrode 156 of the SOI substrate 150 bonded to the laminated semiconductor substrate 720 are electrically connected to each other. Are joined together. Thereby, the laminated semiconductor substrate 710 can be formed.

  FIG. 18 shows an example of a cross section in the manufacturing process by the manufacturing method of the stacked semiconductor device described in relation to FIG. FIG. 18 shows the stacked semiconductor substrate 710 in S754 of FIG. In the figure, the support member 350 is peeled, and the surface 151 of the SOI substrate 150 is exposed. Thereby, the laminated semiconductor substrate 710 is obtained.

  Similar to the stacked semiconductor substrate 610, the stacked semiconductor substrate 710 may include a plurality of semiconductor devices. Therefore, after forming the laminated semiconductor substrate 710, the laminated semiconductor substrate 710 may be cut into a plurality of laminated semiconductor devices by dicing or the like. As described above, a laminated semiconductor device is obtained.

  As in the case of the stacked semiconductor device 600, the processes of S752 and S754 may be repeated a plurality of times. Similarly to the case of the stacked semiconductor device 600, the through hole 123, the through hole 153, the embedded electrode 126, and the embedded electrode 156 may be formed before the step of bonding the stacked semiconductor substrate 110 and the SOI substrate 1150. . Further, the through hole 123, the through hole 153, the embedded electrode 126, and the embedded electrode 156 may be formed after the step of bonding the laminated semiconductor substrate 110 and the SOI substrate 1150.

  By adopting the above configuration, damage to the SOI layer 136 and the SOI layer 166 can be suppressed. That is, in the manufacturing process of the stacked semiconductor substrate 710 and the stacked semiconductor substrate 720, the number of times stress is applied to the SOI layer 136 and the SOI layer 166 can be reduced by thinning the SOI substrate 120 or the SOI substrate 150. In addition, a substrate that forms a stacked semiconductor substrate such as the SOI substrate 120 or the SOI substrate 150 can be thinned in advance, and the thinned substrate can be stacked in accordance with the stacked semiconductor substrate to be manufactured. That is, by adopting the above configuration, it is possible to provide a method for manufacturing a laminated semiconductor substrate or a laminated semiconductor device excellent in mass productivity.

  In this embodiment, the case where the support member 320 and the support member 350 are attached to the SOI substrate 120 or the SOI substrate 150 with a UV curable liquid adhesive has been described, but the present invention is not limited thereto. For example, instead of this, the support member 320 and the support member 350 may be attached to the SOI substrate 120 or the SOI substrate 150 by electrostatic attraction force, respectively. In this case, for example, power supply means for supplying power to the support member 320 and the support member 350 may be provided in a polishing apparatus used in the polishing step. Accordingly, the SOI substrate 120 and the SOI substrate 150 can be polished in a state where the SOI substrate 120 and the SOI substrate 150 are securely attached to the support member 320 or the support member 350. In this case, the support member 320 and the support member 350 may be formed of ceramic, for example.

  In this embodiment, the case where the SOI substrate 120 and the SOI substrate 150 are bonded to each other has been described. However, the target to be bonded is not limited to this. For example, instead of this, a silicon wafer may be bonded.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

An example of the section of substrate pasting device 200 is shown roughly. An example of the cross section of the laminated semiconductor substrate 110 obtained by bonding the SOI substrate 120 and the SOI substrate 150 is shown schematically. An example of the section of layered semiconductor substrate 610 is shown roughly. An example of a method for manufacturing the laminated semiconductor device 600 will be described. An example of the cross section in the manufacturing process by the manufacturing method of the laminated semiconductor device 600 demonstrated in relation to FIG. 4 is shown. An example of the cross section in the manufacturing process by the manufacturing method of the laminated semiconductor device 600 demonstrated in relation to FIG. 4 is shown. An example of the cross section in the manufacturing process by the manufacturing method of the laminated semiconductor device 600 demonstrated in relation to FIG. 4 is shown. An example of the cross section in the manufacturing process by the manufacturing method of the laminated semiconductor device 600 demonstrated in relation to FIG. 4 is shown. An example of the cross section in the manufacturing process by the manufacturing method of the laminated semiconductor device 600 demonstrated in relation to FIG. 4 is shown. An example of the cross section in the manufacturing process by the manufacturing method of the laminated semiconductor device 600 demonstrated in relation to FIG. 4 is shown. An example of the section of lamination semiconductor substrate 1110 is shown roughly. Another example of a method for manufacturing a laminated semiconductor device will be described. An example of the cross section in the manufacture process by the manufacturing method of the laminated semiconductor device demonstrated in relation to FIG. 12 is shown. An example of the cross section in the manufacture process by the manufacturing method of the laminated semiconductor device demonstrated in relation to FIG. 12 is shown. An example of the cross section in the manufacture process by the manufacturing method of the laminated semiconductor device demonstrated in relation to FIG. 12 is shown. An example of the cross section in the manufacture process by the manufacturing method of the laminated semiconductor device demonstrated in relation to FIG. 12 is shown. An example of the cross section in the manufacture process by the manufacturing method of the laminated semiconductor device demonstrated in relation to FIG. 12 is shown. An example of the cross section in the manufacture process by the manufacturing method of the laminated semiconductor device demonstrated in relation to FIG. 12 is shown.

Explanation of symbols

100 laminated semiconductor device, 110 laminated semiconductor substrate, 118 bump, 120 SOI substrate, 121 surface, 122 semiconductor chip, 123 through hole, 124 alignment mark, 126 embedded electrode, 127 semiconductor element, 128 bump, 129 back surface, 132 substrate body, 134 insulating layer, 136 SOI layer, 150 SOI substrate, 151 surface, 152 semiconductor chip, 153 through hole, 154 alignment mark, 156 buried electrode, 157 semiconductor element, 158 bump, 159 back surface, 162 substrate body, 164 insulating layer, 166 SOI layer, 200 substrate bonding apparatus, 210 frame, 212 top plate, 214 support, 216 bottom plate, 220 pressing unit, 222 cylinder, 224 piston, 230 pressure stage, 232 Holding portion, 234 First substrate holding portion, 235 Actuator, 236 Heater, 240 Pressure receiving stage, 242 Second substrate holding portion, 244 Suspension portion, 246 Heater, 250 Pressure detection portion, 252 Load cell, 254 Load cell, 256 Load cell, 320 Support Member, 326 index, 350 support member, 356 index, 600 stacked semiconductor device, 610 stacked semiconductor substrate, 710 stacked semiconductor substrate, 720 stacked semiconductor substrate, 1100 stacked semiconductor device, 1110 stacked semiconductor substrate, 1150 SOI substrate, 1151 surface, 1152 Semiconductor chip, 1157 semiconductor element, 1158 bump, 1159 back surface, 1162 substrate body, 1164 insulating layer, 1166 SOI layer

Claims (21)

(A) providing a first substrate and a second substrate;
(B) affixing one surface of the first substrate to the first support member and affixing one surface of the second substrate to the second support member;
(C) The first substrate and the second substrate are each polished while the first substrate is supported by the first support member and the second substrate is supported by the second support member. Thinning one substrate and the second substrate;
(D) superposing and bonding the thinned first substrate and the second substrate to each other;
A method of manufacturing a laminated semiconductor device comprising: In the step (c), the other surface of the first substrate is polished while the first substrate is supported by the first support member, and the second substrate is supported by the second support member. Polishing the other surface of the second substrate,
In the step (d), the first substrate and the second substrate are bonded so that the other surface of the thinned first substrate and the other surface of the second substrate face each other.
A method for manufacturing a laminated semiconductor device according to claim 1.   In the step (d), the first substrate and the second substrate are bonded to each other while the first substrate is supported by the first support member and the second substrate is supported by the second support member. The manufacturing method of the laminated semiconductor device of Claim 1 or 2.   After polishing the first substrate and the second substrate in the step (c), respectively, the step is performed without peeling the first substrate and the second substrate from the first support member and the second support member, respectively. The method for manufacturing a laminated semiconductor device according to claim 3, wherein (d) is performed.   (E) After bonding the first substrate and the second substrate to each other, the second support member is peeled off to expose a surface of the second substrate attached to the second support member. The method for manufacturing a stacked semiconductor device according to claim 1, further comprising a step of: At least one of the first support member and the second support member is a silicon support member or a glass substrate.
The method for manufacturing a laminated semiconductor device according to claim 1. The first substrate and the second substrate are electrically connected between a through hole penetrating between the one surface and the other surface, and between the one surface and the other surface formed in the through hole. Each having a through-coupling portion that couples to
The first substrate and the second substrate are bonded so that the through-coupling portions are electrically coupled to each other;
The method for manufacturing a semiconductor device according to claim 1. The through hole and the through coupling portion are formed before the step of joining the first substrate and the second substrate.
A method for manufacturing a semiconductor device according to claim 7. The through hole and the through coupling portion are formed after the step of joining the first substrate and the second substrate.
A method for manufacturing a semiconductor device according to claim 7.   The first substrate and the second substrate each have an SOI layer formed in contact with the insulating layer and the insulating layer, and the first support member and the second support member are formed on the surface on which the SOI layer is formed. The method for manufacturing a laminated semiconductor device according to claim 1, wherein a layer is attached. (F) providing a third substrate;
(G) One surface of the third substrate is attached to a third support member, and the third substrate is polished by polishing the third substrate with the third support member supported by the third substrate. Thinning stage,
(H) superposing and bonding the second substrate and the thinned third substrate to each other;
The method for manufacturing a semiconductor device according to claim 1, further comprising:   (I) After bonding the second substrate and the third substrate to each other, the third support member is peeled off to expose a surface of the third substrate that is attached to the third support member. The method of manufacturing a stacked semiconductor device according to claim 11, further comprising: Repeating the steps (f) to (i) a plurality of times to further stack a plurality of the third substrates,
A method for manufacturing a laminated semiconductor device according to claim 12. The third substrate includes a through-hole penetrating between the one surface and the other surface, and a through-coupling that is electrically coupled between the one surface and the other surface formed in the through-hole. And
The second substrate and the third substrate are joined such that the through-coupling portion of the second substrate and the through-coupling portion of the third substrate are electrically coupled to each other;
The method for manufacturing a semiconductor device according to claim 11. The through hole and the through coupling part are formed before the step of joining the second substrate and the third substrate.
The manufacturing method according to claim 14. The through hole and the through coupling portion are formed after the step of joining the first substrate and the second substrate.
The manufacturing method according to claim 14.   The said 3rd board | substrate has an SOI layer formed in contact with the insulating layer and the said insulating layer, respectively, The said 3rd supporting member is affixed on the surface in which the said SOI layer was formed. A method for manufacturing a stacked semiconductor device according to claim 1. (J) preparing a fourth substrate;
(K) bonding the second substrate and the fourth substrate together;
The method of manufacturing a semiconductor device according to claim 1, further comprising:   The said 4th board | substrate has an SOI layer formed in contact with the insulating layer and the said insulating layer, The surface joined to the said 2nd board | substrate is a surface in which the said SOI layer was formed. A method for manufacturing a laminated semiconductor device. (L) preparing a fourth substrate;
(M) bonding the third substrate and the fourth substrate to each other;
The manufacturing method according to any one of claims 11 to 17, further comprising:   The said 4th board | substrate has an SOI layer formed in contact with the insulating layer and the said insulating layer, and the surface joined to the said 3rd board | substrate is a surface in which the said SOI layer was formed. A method for manufacturing a laminated semiconductor device.

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