TWI456727B - 晶粒封裝結構以及相關的晶粒封裝結構製造方法 - Google Patents
晶粒封裝結構以及相關的晶粒封裝結構製造方法 Download PDFInfo
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- TWI456727B TWI456727B TW099145752A TW99145752A TWI456727B TW I456727 B TWI456727 B TW I456727B TW 099145752 A TW099145752 A TW 099145752A TW 99145752 A TW99145752 A TW 99145752A TW I456727 B TWI456727 B TW I456727B
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- 238000004519 manufacturing process Methods 0.000 title claims 4
- 239000011162 core material Substances 0.000 claims 20
- 239000002184 metal Substances 0.000 claims 6
- 238000000034 method Methods 0.000 claims 5
- 229920002120 photoresistant polymer Polymers 0.000 claims 4
- 239000013078 crystal Substances 0.000 claims 2
- 239000000945 filler Substances 0.000 claims 2
- 239000000463 material Substances 0.000 claims 2
- 239000007769 metal material Substances 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 1
- 238000007747 plating Methods 0.000 claims 1
- 239000002861 polymer material Substances 0.000 claims 1
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Claims (12)
- 一種晶粒封裝結構,包含:一第一晶粒;一第二晶粒;一核心材料層,位於該第一晶粒和該第二晶粒之間;至少一通孔,穿過該第一晶粒、該第二晶粒以及該核心材料層;一金屬材料,填入該通孔中,使得該第一晶粒、該第二晶粒以及該核心材料層可以彼此電性連接;至少一訊號傳收單元,接觸該金屬材料;以及一介電層,包圍該第一晶粒,包含暴露該訊號傳收單元的至少一開口。
- 如申請專利範圍第1項的晶粒封裝結構,其中該第一晶粒係為一主機裝置,且該第二晶粒係為一僕裝置。
- 如申請專利範圍第1項的晶粒封裝結構,更包含一第三晶粒,具有至少一通孔,使得該第三晶粒可電性連接至該第二晶粒。
- 如申請專利範圍第1項的晶粒封裝結構,更包含填充材料,該填充材料位於該第一晶粒以及該核心材料,以及該第二晶粒和該核心材料之間。
- 如申請專利範圍第1項的晶粒封裝結構,更包含位於該開口旁的 連接墊。
- 如申請專利範圍第1項的晶粒封裝結構,其中該核心材料層包含聚合物材料。
- 一種晶粒封裝結構製造方法,包含:(a)形成具有通孔的一核心材料層,該通孔中具有金屬,其中該金屬具有一突出部份,該突出部份突出該核心材料層;(b)在該核心材料層的一第一側提供一第一晶粒,其中該第一晶粒具有通孔,且該第一晶粒的該通孔電性連接至該第一晶粒之一第一側上的核心材料層之該通孔;(c)於該第一晶粒上提供至少一訊號傳收單元,其中該訊號傳收單元位於該第一晶粒的一第二側上,其中該第一晶粒的該第二側相對於該第一晶粒的該第一側;(d)在該第一晶粒和該核心材料層上形成一介電層,其中該介電層包含暴露該訊號傳收單元的至少一開口;以及(e)於該核心材料層的一第二側上形成一第二晶粒,其中該核心材料層的該第二側相對於該核心材料層的該第一側。
- 如申請專利範圍第7項的晶粒封裝結構製造方法,更包含提供一第三晶粒,該第三晶粒具有至少一通孔,使得該第三晶粒可電性連接至該第二晶粒。
- 如申請專利範圍第7項的晶粒封裝結構製造方法,更包含提供填充材料,該填充材料位於該第一晶粒以及該核心材料之間,以及該第二晶粒和該核心材料之間。
- 如申請專利範圍第7項的晶粒封裝結構製造方法,其中該步驟(a)包含:於該核心材料層中形成該通孔;於該核心材料層的一表面上以及該通孔中鍍上金屬;以及於該金屬上提供一光阻層並蝕刻該金屬的其他部份以形成該突出部份。
- 如申請專利範圍第7項的晶粒封裝結構製造方法,更包含:在提供一第二晶粒於該核心材料層之一第二側上之前,於核心材料層之該第二側上提供一光阻層。
- 如申請專利範圍第7項的晶粒封裝結構製造方法,其中該步驟(e)包含:於該訊號傳收單元上提供一光阻層;提供該介電層;以及移除該訊號傳收單元上的該光阻層。
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US8421193B2 (en) * | 2010-11-18 | 2013-04-16 | Nanya Technology Corporation | Integrated circuit device having through via and method for preparing the same |
US20120168935A1 (en) * | 2011-01-03 | 2012-07-05 | Nanya Technology Corp. | Integrated circuit device and method for preparing the same |
US20130264688A1 (en) * | 2012-04-06 | 2013-10-10 | Omnivision Technologies, Inc. | Method and apparatus providing integrated circuit system with interconnected stacked device wafers |
US9142581B2 (en) | 2012-11-05 | 2015-09-22 | Omnivision Technologies, Inc. | Die seal ring for integrated circuit system with stacked device wafers |
TWI492340B (zh) * | 2012-12-12 | 2015-07-11 | Ind Tech Res Inst | 封裝結構及其製造方法 |
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