CN102339803A - 裸片封装结构以及相关的裸片封装结构制造方法 - Google Patents

裸片封装结构以及相关的裸片封装结构制造方法 Download PDF

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CN102339803A
CN102339803A CN2011100577918A CN201110057791A CN102339803A CN 102339803 A CN102339803 A CN 102339803A CN 2011100577918 A CN2011100577918 A CN 2011100577918A CN 201110057791 A CN201110057791 A CN 201110057791A CN 102339803 A CN102339803 A CN 102339803A
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nude film
core material
material layer
encapsulating structure
hole
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CN102339803B (zh
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陈仁君
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本发明公开了一种裸片封装结构，包含：一第一裸片；一第二裸片；一核心材料层，位于该第一裸片和该第二裸片之间；至少一通孔，通过该第一裸片、该第二裸片以及该核心材料层；一金属材料，填入该通孔中，使得该第一裸片、该第二裸片以及该核心材料层可以彼此电连接；至少一信号传收单元，接触该金属材料；以及一介电层，包围该第一裸片，包含暴露该信号传收单元的至少一开口。本发明可快速形成连接垫电路并形成简洁但完整的3D封装结构。

Description

裸片封装结构以及相关的裸片封装结构制造方法
技术领域
本发明公开了裸片封装结构以及相关的裸片封装结构制造方法，特别公开了使用TSV(Through-Silicon Via，硅晶穿孔)的裸片封装结构以及相关的裸片封装结构制造方法。
背景技术
现今的DRAM结构常需要高密度或高速度的结构。为了满足高密度结构的需求，发展出了3D封装结构。与传统的2D封装结构比较起来，使用3D封装技术的芯片具有较短的导电路径以及垂直的导电结构。使得使用3D封装技术的芯片与传统2D封装结构比较起来具有较短的传导路径以及较少的信号延迟时间。此外，可以通过3D封装结构增加芯片表现。而且，芯片功率消耗、寄生电容以及电感也会随之减少。
TSV技术为一种3D封装技术。然而，现今的TSV技术仍然不稳定且具有高成本，使得现今的3D封装技术难以跟传统封装技术竞争。
发明内容
因此，本发明的目的之一为提供一种较简洁的3D封装结构。
本发明的一实施例揭露了一种裸片封装结构，包含：一第一裸片；一第二裸片；一核心材料层，位于该第一裸片和该第二裸片之间；至少一通孔，通过该第一裸片、该第二裸片以及该核心材料层；一金属材料，填入该通孔中，使得该第一裸片、该第二裸片以及该核心材料层可以彼此电连接；至少一信号传收单元，接触该金属材料；以及一介电层，包围该第一裸片，包含暴露该信号传收单元的至少一开口。
本发明的另一实施例揭露了一种裸片封装结构制造方法，包含：(1)形成具有通孔的一核心材料层，该通孔中具有金属，其特征是该金属具有一突出部分，该突出部分突出该核心材料层；(2)在该核心材料层的一第一侧提供一第一裸片，其特征是该第一裸片具有通孔，且该第一裸片的该通孔电连接至该第一裸片的一第一侧上的核心材料层的该通孔；(3)于该第一裸片上提供至少一信号传收单元，其特征是该信号传收单元位于该第一裸片的一第二侧上，其中该第一裸片的该第二侧相对于该第一裸片的该第一侧；(4)在该第一裸片和该核心材料层上形成一介电层，其特征是该介电层包含暴露该信号传收单元的至少一开口；以及(5)于该核心材料层的一第二侧上形成一第二裸片，其特征是该核心材料层的该第二侧相对于该核心材料层的该第一侧。
根据本发明的实施例，可以快速完成连接垫电路，以提供简单但完整的3D封装结构。
附图说明
图1和图2绘示了根据本发明的一实施例的裸片封装结构的剖面图。
图3a-10b绘示了根据本发明的一实施例的裸片封装结构制造方法。
其中，附图标记说明如下：
100                         裸片封装结构
101、601                    第一裸片
103、301                    核心材料层
105、913                    第二裸片
107、109、303、305、602、604通孔
110、307                   金属材料
111                        介电层
112、114、701、703         选通凸块
113、115、603              填充材料
117-127、907-911           连接垫
201                        第三裸片
401、501          光阻层
705、707          光阻材料
801               介电材料
915               填充材料
1001～1011        锡球
具体实施方式
在说明书及后续的权利要求当中使用了某些词汇来指称特定的元件。本领域的技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个元件。本说明书及前述的权利要求并不以名称的差异来作为区分元件的方式，而是以元件在功能上的差异来作为区分的准则。在通篇说明书及前述的权利要求当中所提及的“包含”为一开放式的用语，所以应解释成“包含但不限定于”。
图1绘示了根据本发明的一实施例的裸片封装结构100的剖面图。如图1所示，裸片封装结构100包含一第一裸片101，一核心材料层103、一第二裸片105、通孔107、109、金属材料110、介电层111、选通凸块(strobe bump)112、114、填充材料113、115以及连接垫117～127。核心材料层103(可为聚合物材料例如PI等)，被提供于第一裸片101和第二裸片105之间。此外，填充材料113位于核心材料层103和第二裸片105之间，且填充材料115位于第一裸片101和核心材料层103之间。通孔107、109穿过第一裸片101、第二裸片105以及核心材料层103。金属材料110填入通孔107和109中，使得第一裸片101、第二裸片105以及核心材料层103可以彼此电连接。选通凸块112、114接触金属材料110，使得粘结(bonding)在连接垫117～127上的锡球可通过选通凸块112、114和金属110。也就是说，选通凸块112、114可作为信号传收单元使用。介电层111包围第一裸片101，并包含了暴露选通凸块112、114的开口129、131。
在一实施例中，第一裸片101为一主机设备(master device)，且第二裸片105为一子设备(slave device)。此外，裸片封装结构100可更包含除了第一裸片101和第二裸片105之外的裸片。如图2所示，裸片封装结构100更包含了一第三裸片105，其也作为子设备使用。须注意的是，裸片封装结构100可包含更多的裸片，但在此不再赘述。在此例中，填充材料203可被提供于第二裸片105和第三裸片201之间。此种结构可被使用于多种电子设备中(例如，一DRAM)。
图3a-10b绘示了根据本发明的一实施例的裸片封装结构制造方法。请留意图3a-10b中的步骤仅用以举例，并非用以限定本发明。
如图3a所示，提供了一核心材料层301(例如聚合物材料PI)。在图3b中，通孔303和305形成于核心材料层301中。然后，在图4a中，如铜之类的金属材料307可被提供于核心材料层301上(例如，通过涂布处理)。在图4b中，光阻层401被提供在金属材料307的某些部分上。接着会通过显影或蚀刻移除其他部分的金属材料307，使得金属材料307突出于核心材料层301的表面，如图5a所示。然后，光阻层501被提供于核心材料层301上。
在图6a中，第一裸片601被提供在一表面上，此表面相对于光阻层被提供的表面。第一裸片601包含了通孔602和604(例如，TSV结构)。核心材料层301的通孔和第一裸片601可以通过热压接法(Thermal compression)、超声波压接法(ultra-sonic compression)或熔接等形式而连结在一起。此外，填充材料603可被提供于核心材料层301以及第一裸片601之间，使得第一裸片601可紧密地连接至核心材料层301，且蒸气可被防止进入核心材料层301和第一裸片601间的间隙。
在图7a中，提供了选通凸块701、703(作为信号传收单元使用)，被提供以接触第一裸片601的通孔602、604。通过此类选通凸块701、703，可以省略长成金属种和薄膜的工艺，使得介电材料801的连接垫电路可以很快的形成。在图7b中，可使用一显影工艺来对准选通凸块701、703的位置，使得光阻材料705、707可被提供在选通凸块701、703上。然后，介电材料801(可为UV胶或B阶环氧树脂)，可通过一印刷过程被提供(未限制于此)。在图8b中，光阻材料705、707被移除，以形成曝露选通凸块701、703的开口。
在图9a中，提供了锡球的连接垫907-911。在图9b中提供了第二裸片913。此外，类似于第一裸片601、填充材料915可被提供于第二裸片913和核心材料层301之间。在图10a中，锡球1001～1011被提供于连接垫901～911上，且可施行一油墨工艺(ink process)以形成图10b的结构。然后可施行一凸块底金属层(Under Bump Metallurgy，UBM)工艺至第二裸片913的一主动表面。如前所述，可提供多个裸片以形成图2的结构，并可通过此方法形成较高容量的DRAM。
根据前述实施例，可快速形成连接垫电路并形成简洁但完整的3D封装结构。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (12)

1.一种裸片封装结构，其特征是，包含：
一第一裸片；
一第二裸片；
一核心材料层，位于该第一裸片和该第二裸片之间；
至少一通孔，穿过该第一裸片、该第二裸片以及该核心材料层；
一金属材料，填入该通孔中，使得该第一裸片、该第二裸片以及该核心材料层可以彼此电连接；
至少一信号传收单元，接触该金属材料；以及
一介电层，包围该第一裸片，包含暴露该信号传收单元的至少一开口。
2.权利要求1的裸片封装结构，其特征是，该第一裸片为一主机设备，且该第二裸片为一子设备。
3.权利要求1的裸片封装结构，其特征是，还包含一第三裸片，具有至少一通孔，使得该第三裸片可电连接至该第二裸片。
4.权利要求1的裸片封装结构，其特征是，还包含填充材料，该填充材料位于该第一裸片以及该核心材料，以及该第二裸片和该核心材料之间。
5.权利要求1的裸片封装结构，其特征是，还包含位于该开口旁的连接垫。
6.权利要求1的裸片封装结构，其特征是，该核心材料层包含聚合物材料。
7.一种裸片封装结构制造方法，其特征是，包含：
(1)形成具有通孔的一核心材料层，该通孔中具有金属，其特征是，该金属具有一突出部分，该突出部分突出该核心材料层；
(2)在该核心材料层的一第一侧提供一第一裸片，其特征是，该第一裸片具有通孔，且该第一裸片的该通孔电连接至该第一裸片的一第一侧上的核心材料层的该通孔；
(3)于该第一裸片上提供至少一信号传收单元，其特征是，该信号传收单元位于该第一裸片的一第二侧上，其中该第一裸片的该第二侧相对于该第一裸片的该第一侧；
(4)在该第一裸片和该核心材料层上形成一介电层，其特征是，该介电层包含暴露该信号传收单元的至少一开口；以及
(5)于该核心材料层的一第二侧上形成一第二裸片，其特征是，该核心材料层的该第二侧相对于该核心材料层的该第一侧。
8.权利要求7的裸片封装结构制造方法，其特征是，还包含：提供一第三裸片，该第三裸片具有至少一通孔，使得该第三裸片可电连接至该第二裸片。
9.权利要求7的裸片封装结构制造方法，其特征是，还包含：提供填充材料，该填充材料位于该第一裸片以及该核心材料之间，以及该第二裸片和该核心材料之间。
10.权利要求7的裸片封装结构制造方法，其特征是，该步骤(1)包含：
于该核心材料层中形成该通孔；
于该核心材料层的一表面上以及该通孔中镀上金属；以及
于该金属上提供一光阻层并蚀刻该金属的其他部分以形成该突出部分。
11.权利要求7的裸片封装结构制造方法，其特征是，还包含：
在提供一第二裸片于该核心材料层的一第二侧上之前，于核心材料层的该第二侧上提供一光阻层。
12.权利要求7的裸片封装结构制造方法，其特征是，该步骤(5)包含：
于该信号传收单元上提供一光阻层；
提供该介电层；以及
移除该信号传收单元上的该光阻层。
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