CN102339803A - 裸片封装结构以及相关的裸片封装结构制造方法 - Google Patents

裸片封装结构以及相关的裸片封装结构制造方法 Download PDF

Info

Publication number
CN102339803A
CN102339803A CN2011100577918A CN201110057791A CN102339803A CN 102339803 A CN102339803 A CN 102339803A CN 2011100577918 A CN2011100577918 A CN 2011100577918A CN 201110057791 A CN201110057791 A CN 201110057791A CN 102339803 A CN102339803 A CN 102339803A
Authority
CN
China
Prior art keywords
nude film
core material
material layer
encapsulating structure
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011100577918A
Other languages
English (en)
Other versions
CN102339803B (zh
Inventor
陈仁君
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanya Technology Corp
Original Assignee
Nanya Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Publication of CN102339803A publication Critical patent/CN102339803A/zh
Application granted granted Critical
Publication of CN102339803B publication Critical patent/CN102339803B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05017—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01059—Praseodymium [Pr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)

Abstract

本发明公开了一种裸片封装结构，包含：一第一裸片；一第二裸片；一核心材料层，位于该第一裸片和该第二裸片之间；至少一通孔，通过该第一裸片、该第二裸片以及该核心材料层；一金属材料，填入该通孔中，使得该第一裸片、该第二裸片以及该核心材料层可以彼此电连接；至少一信号传收单元，接触该金属材料；以及一介电层，包围该第一裸片，包含暴露该信号传收单元的至少一开口。本发明可快速形成连接垫电路并形成简洁但完整的3D封装结构。

Description

裸片封装结构以及相关的裸片封装结构制造方法
技术领域
本发明公开了裸片封装结构以及相关的裸片封装结构制造方法，特别公开了使用TSV(Through-Silicon Via，硅晶穿孔)的裸片封装结构以及相关的裸片封装结构制造方法。
背景技术
现今的DRAM结构常需要高密度或高速度的结构。为了满足高密度结构的需求，发展出了3D封装结构。与传统的2D封装结构比较起来，使用3D封装技术的芯片具有较短的导电路径以及垂直的导电结构。使得使用3D封装技术的芯片与传统2D封装结构比较起来具有较短的传导路径以及较少的信号延迟时间。此外，可以通过3D封装结构增加芯片表现。而且，芯片功率消耗、寄生电容以及电感也会随之减少。
TSV技术为一种3D封装技术。然而，现今的TSV技术仍然不稳定且具有高成本，使得现今的3D封装技术难以跟传统封装技术竞争。
发明内容
因此，本发明的目的之一为提供一种较简洁的3D封装结构。
本发明的一实施例揭露了一种裸片封装结构，包含：一第一裸片；一第二裸片；一核心材料层，位于该第一裸片和该第二裸片之间；至少一通孔，通过该第一裸片、该第二裸片以及该核心材料层；一金属材料，填入该通孔中，使得该第一裸片、该第二裸片以及该核心材料层可以彼此电连接；至少一信号传收单元，接触该金属材料；以及一介电层，包围该第一裸片，包含暴露该信号传收单元的至少一开口。
本发明的另一实施例揭露了一种裸片封装结构制造方法，包含：(1)形成具有通孔的一核心材料层，该通孔中具有金属，其特征是该金属具有一突出部分，该突出部分突出该核心材料层；(2)在该核心材料层的一第一侧提供一第一裸片，其特征是该第一裸片具有通孔，且该第一裸片的该通孔电连接至该第一裸片的一第一侧上的核心材料层的该通孔；(3)于该第一裸片上提供至少一信号传收单元，其特征是该信号传收单元位于该第一裸片的一第二侧上，其中该第一裸片的该第二侧相对于该第一裸片的该第一侧；(4)在该第一裸片和该核心材料层上形成一介电层，其特征是该介电层包含暴露该信号传收单元的至少一开口；以及(5)于该核心材料层的一第二侧上形成一第二裸片，其特征是该核心材料层的该第二侧相对于该核心材料层的该第一侧。
根据本发明的实施例，可以快速完成连接垫电路，以提供简单但完整的3D封装结构。
附图说明
图1和图2绘示了根据本发明的一实施例的裸片封装结构的剖面图。
图3a-10b绘示了根据本发明的一实施例的裸片封装结构制造方法。
其中，附图标记说明如下：
100                         裸片封装结构
101、601                    第一裸片
103、301                    核心材料层
105、913                    第二裸片
107、109、303、305、602、604通孔
110、307                   金属材料
111                        介电层
112、114、701、703         选通凸块
113、115、603              填充材料
117-127、907-911           连接垫
201                        第三裸片
401、501          光阻层
705、707          光阻材料
801               介电材料
915               填充材料
1001～1011        锡球
具体实施方式
在说明书及后续的权利要求当中使用了某些词汇来指称特定的元件。本领域的技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个元件。本说明书及前述的权利要求并不以名称的差异来作为区分元件的方式，而是以元件在功能上的差异来作为区分的准则。在通篇说明书及前述的权利要求当中所提及的“包含”为一开放式的用语，所以应解释成“包含但不限定于”。
图1绘示了根据本发明的一实施例的裸片封装结构100的剖面图。如图1所示，裸片封装结构100包含一第一裸片101，一核心材料层103、一第二裸片105、通孔107、109、金属材料110、介电层111、选通凸块(strobe bump)112、114、填充材料113、115以及连接垫117～127。核心材料层103(可为聚合物材料例如PI等)，被提供于第一裸片101和第二裸片105之间。此外，填充材料113位于核心材料层103和第二裸片105之间，且填充材料115位于第一裸片101和核心材料层103之间。通孔107、109穿过第一裸片101、第二裸片105以及核心材料层103。金属材料110填入通孔107和109中，使得第一裸片101、第二裸片105以及核心材料层103可以彼此电连接。选通凸块112、114接触金属材料110，使得粘结(bonding)在连接垫117～127上的锡球可通过选通凸块112、114和金属110。也就是说，选通凸块112、114可作为信号传收单元使用。介电层111包围第一裸片101，并包含了暴露选通凸块112、114的开口129、131。
在一实施例中，第一裸片101为一主机设备(master device)，且第二裸片105为一子设备(slave device)。此外，裸片封装结构100可更包含除了第一裸片101和第二裸片105之外的裸片。如图2所示，裸片封装结构100更包含了一第三裸片105，其也作为子设备使用。须注意的是，裸片封装结构100可包含更多的裸片，但在此不再赘述。在此例中，填充材料203可被提供于第二裸片105和第三裸片201之间。此种结构可被使用于多种电子设备中(例如，一DRAM)。
图3a-10b绘示了根据本发明的一实施例的裸片封装结构制造方法。请留意图3a-10b中的步骤仅用以举例，并非用以限定本发明。
如图3a所示，提供了一核心材料层301(例如聚合物材料PI)。在图3b中，通孔303和305形成于核心材料层301中。然后，在图4a中，如铜之类的金属材料307可被提供于核心材料层301上(例如，通过涂布处理)。在图4b中，光阻层401被提供在金属材料307的某些部分上。接着会通过显影或蚀刻移除其他部分的金属材料307，使得金属材料307突出于核心材料层301的表面，如图5a所示。然后，光阻层501被提供于核心材料层301上。
在图6a中，第一裸片601被提供在一表面上，此表面相对于光阻层被提供的表面。第一裸片601包含了通孔602和604(例如，TSV结构)。核心材料层301的通孔和第一裸片601可以通过热压接法(Thermal compression)、超声波压接法(ultra-sonic compression)或熔接等形式而连结在一起。此外，填充材料603可被提供于核心材料层301以及第一裸片601之间，使得第一裸片601可紧密地连接至核心材料层301，且蒸气可被防止进入核心材料层301和第一裸片601间的间隙。
在图7a中，提供了选通凸块701、703(作为信号传收单元使用)，被提供以接触第一裸片601的通孔602、604。通过此类选通凸块701、703，可以省略长成金属种和薄膜的工艺，使得介电材料801的连接垫电路可以很快的形成。在图7b中，可使用一显影工艺来对准选通凸块701、703的位置，使得光阻材料705、707可被提供在选通凸块701、703上。然后，介电材料801(可为UV胶或B阶环氧树脂)，可通过一印刷过程被提供(未限制于此)。在图8b中，光阻材料705、707被移除，以形成曝露选通凸块701、703的开口。
在图9a中，提供了锡球的连接垫907-911。在图9b中提供了第二裸片913。此外，类似于第一裸片601、填充材料915可被提供于第二裸片913和核心材料层301之间。在图10a中，锡球1001～1011被提供于连接垫901～911上，且可施行一油墨工艺(ink process)以形成图10b的结构。然后可施行一凸块底金属层(Under Bump Metallurgy，UBM)工艺至第二裸片913的一主动表面。如前所述，可提供多个裸片以形成图2的结构，并可通过此方法形成较高容量的DRAM。
根据前述实施例，可快速形成连接垫电路并形成简洁但完整的3D封装结构。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (12)

1.一种裸片封装结构，其特征是，包含：
一第一裸片；
一第二裸片；
一核心材料层，位于该第一裸片和该第二裸片之间；
至少一通孔，穿过该第一裸片、该第二裸片以及该核心材料层；
一金属材料，填入该通孔中，使得该第一裸片、该第二裸片以及该核心材料层可以彼此电连接；
至少一信号传收单元，接触该金属材料；以及
一介电层，包围该第一裸片，包含暴露该信号传收单元的至少一开口。
2.权利要求1的裸片封装结构，其特征是，该第一裸片为一主机设备，且该第二裸片为一子设备。
3.权利要求1的裸片封装结构，其特征是，还包含一第三裸片，具有至少一通孔，使得该第三裸片可电连接至该第二裸片。
4.权利要求1的裸片封装结构，其特征是，还包含填充材料，该填充材料位于该第一裸片以及该核心材料，以及该第二裸片和该核心材料之间。
5.权利要求1的裸片封装结构，其特征是，还包含位于该开口旁的连接垫。
6.权利要求1的裸片封装结构，其特征是，该核心材料层包含聚合物材料。
7.一种裸片封装结构制造方法，其特征是，包含：
(1)形成具有通孔的一核心材料层，该通孔中具有金属，其特征是，该金属具有一突出部分，该突出部分突出该核心材料层；
(2)在该核心材料层的一第一侧提供一第一裸片，其特征是，该第一裸片具有通孔，且该第一裸片的该通孔电连接至该第一裸片的一第一侧上的核心材料层的该通孔；
(3)于该第一裸片上提供至少一信号传收单元，其特征是，该信号传收单元位于该第一裸片的一第二侧上，其中该第一裸片的该第二侧相对于该第一裸片的该第一侧；
(4)在该第一裸片和该核心材料层上形成一介电层，其特征是，该介电层包含暴露该信号传收单元的至少一开口；以及
(5)于该核心材料层的一第二侧上形成一第二裸片，其特征是，该核心材料层的该第二侧相对于该核心材料层的该第一侧。
8.权利要求7的裸片封装结构制造方法，其特征是，还包含：提供一第三裸片，该第三裸片具有至少一通孔，使得该第三裸片可电连接至该第二裸片。
9.权利要求7的裸片封装结构制造方法，其特征是，还包含：提供填充材料，该填充材料位于该第一裸片以及该核心材料之间，以及该第二裸片和该核心材料之间。
10.权利要求7的裸片封装结构制造方法，其特征是，该步骤(1)包含：
于该核心材料层中形成该通孔；
于该核心材料层的一表面上以及该通孔中镀上金属；以及
于该金属上提供一光阻层并蚀刻该金属的其他部分以形成该突出部分。
11.权利要求7的裸片封装结构制造方法，其特征是，还包含：
在提供一第二裸片于该核心材料层的一第二侧上之前，于核心材料层的该第二侧上提供一光阻层。
12.权利要求7的裸片封装结构制造方法，其特征是，该步骤(5)包含：
于该信号传收单元上提供一光阻层；
提供该介电层；以及
移除该信号传收单元上的该光阻层。
CN201110057791.8A 2010-07-15 2011-03-10 裸片封装结构制造方法 Active CN102339803B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/836,583 US8143712B2 (en) 2010-07-15 2010-07-15 Die package structure
US12/836,583 2010-07-15

Publications (2)

Publication Number Publication Date
CN102339803A true CN102339803A (zh) 2012-02-01
CN102339803B CN102339803B (zh) 2013-09-25

Family

ID=45466324

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110057791.8A Active CN102339803B (zh) 2010-07-15 2011-03-10 裸片封装结构制造方法

Country Status (3)

Country Link
US (1) US8143712B2 (zh)
CN (1) CN102339803B (zh)
TW (1) TWI456727B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8421193B2 (en) * 2010-11-18 2013-04-16 Nanya Technology Corporation Integrated circuit device having through via and method for preparing the same
US20120168935A1 (en) * 2011-01-03 2012-07-05 Nanya Technology Corp. Integrated circuit device and method for preparing the same
US20130264688A1 (en) * 2012-04-06 2013-10-10 Omnivision Technologies, Inc. Method and apparatus providing integrated circuit system with interconnected stacked device wafers
US9142581B2 (en) 2012-11-05 2015-09-22 Omnivision Technologies, Inc. Die seal ring for integrated circuit system with stacked device wafers
TWI492340B (zh) * 2012-12-12 2015-07-11 Ind Tech Res Inst 封裝結構及其製造方法
KR102190382B1 (ko) 2012-12-20 2020-12-11 삼성전자주식회사 반도체 패키지

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080230913A1 (en) * 2007-03-20 2008-09-25 Siliconware Precision Industries Co., Ltd. Stackable semiconductor device and fabrication method thereof
US20080303163A1 (en) * 2007-06-07 2008-12-11 United Test And Assembly Center Ltd. Through silicon via dies and packages
US20090004777A1 (en) * 2007-05-22 2009-01-01 United Test And Assembly Center Ltd. Stacked die semiconductor package and method of assembly
US20100159643A1 (en) * 2008-12-19 2010-06-24 Texas Instruments Incorporated Bonding ic die to tsv wafers
CN101840912A (zh) * 2009-03-06 2010-09-22 台湾积体电路制造股份有限公司 半导体装置及其制造方法
CN102104009A (zh) * 2009-12-16 2011-06-22 中国科学院微电子研究所 一种三维硅基电容器的制作方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10164800B4 (de) * 2001-11-02 2005-03-31 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauelements mit mehreren übereinander gestapelten und miteinander kontaktierten Chips
TW200802660A (en) * 2006-06-28 2008-01-01 Megica Corp Semiconductor chip structure
KR101336569B1 (ko) * 2007-05-22 2013-12-03 삼성전자주식회사 증가된 결합 신뢰성을 갖는 반도체 패키지 및 그 제조 방법
TWI362102B (en) * 2007-07-11 2012-04-11 Ind Tech Res Inst Three-dimensional dice-stacking package structure and method for manufactruing the same
TW200924148A (en) * 2007-11-26 2009-06-01 Ind Tech Res Inst Structure of three-dimensional stacked dies with vertical electrical self-interconnections and method for manufacturing the same
TWI389291B (zh) * 2008-05-13 2013-03-11 Ind Tech Res Inst 三維堆疊晶粒封裝結構
US7872332B2 (en) * 2008-09-11 2011-01-18 Micron Technology, Inc. Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods
TWI370532B (en) * 2009-11-12 2012-08-11 Ind Tech Res Inst Chip package structure and method for fabricating the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080230913A1 (en) * 2007-03-20 2008-09-25 Siliconware Precision Industries Co., Ltd. Stackable semiconductor device and fabrication method thereof
US20090004777A1 (en) * 2007-05-22 2009-01-01 United Test And Assembly Center Ltd. Stacked die semiconductor package and method of assembly
US20080303163A1 (en) * 2007-06-07 2008-12-11 United Test And Assembly Center Ltd. Through silicon via dies and packages
US20100159643A1 (en) * 2008-12-19 2010-06-24 Texas Instruments Incorporated Bonding ic die to tsv wafers
CN101840912A (zh) * 2009-03-06 2010-09-22 台湾积体电路制造股份有限公司 半导体装置及其制造方法
CN102104009A (zh) * 2009-12-16 2011-06-22 中国科学院微电子研究所 一种三维硅基电容器的制作方法

Also Published As

Publication number Publication date
US20120013018A1 (en) 2012-01-19
CN102339803B (zh) 2013-09-25
TW201203492A (en) 2012-01-16
US8143712B2 (en) 2012-03-27
TWI456727B (zh) 2014-10-11

Similar Documents

Publication Publication Date Title
US9899249B2 (en) Fabrication method of coreless packaging substrate
US8058721B2 (en) Package structure
CN104253115B (zh) 用于半导体封装中减小的管芯到管芯间隔的底部填充材料流控制
US20120049366A1 (en) Package structure having through-silicon-via (tsv) chip embedded therein and fabrication method thereof
US20070007641A1 (en) Chip-embedded interposer structure and fabrication method thereof, wafer level stack structure and resultant package structure
US9338900B2 (en) Interposer substrate and method of fabricating the same
CN102339803B (zh) 裸片封装结构制造方法
US10109572B2 (en) Method for fabricating package structure
US10448508B2 (en) Printed circuit board and semiconductor package including the same
US8436463B2 (en) Packaging substrate structure with electronic component embedded therein and method for manufacture of the same
US11069540B2 (en) Package on package and a method of fabricating the same
CN105304584A (zh) 中介基板及其制造方法
US20090008766A1 (en) High-Density Fine Line Structure And Method Of Manufacturing The Same
US20140346667A1 (en) Semiconductor package and method of fabricating the same
TWI550744B (zh) 單層線路式封裝基板及其製法、單層線路式封裝結構及其製法
US20120224328A1 (en) Inner-layer heat-dissipating board, multi-chip stack package structure having the inner layer heat-dissipating board and fabrication method thereof
US20180047662A1 (en) Interposer substrate and method of manufacturing the same
US20160165722A1 (en) Interposer substrate and method of fabricating the same
KR102146131B1 (ko) 패키지 적층 소자
US9941208B1 (en) Substrate structure and manufacturing method thereof
US20090001547A1 (en) High-Density Fine Line Structure And Method Of Manufacturing The Same
US20160099202A1 (en) Semiconductor packaging structure
TWI555153B (zh) 基板結構及其製法
US20080303150A1 (en) High-Density Fine Line Structure And Method Of Manufacturing The Same
KR101384342B1 (ko) 반도체 패키지

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant