JP6394056B2 - Ａ／ｄ変換装置、グレイコード生成装置、撮像素子、並びに、電子機器 - Google Patents

Ａ／ｄ変換装置、グレイコード生成装置、撮像素子、並びに、電子機器 Download PDF

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Publication number
JP6394056B2
JP6394056B2 JP2014100185A JP2014100185A JP6394056B2 JP 6394056 B2 JP6394056 B2 JP 6394056B2 JP 2014100185 A JP2014100185 A JP 2014100185A JP 2014100185 A JP2014100185 A JP 2014100185A JP 6394056 B2 JP6394056 B2 JP 6394056B2
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Japan
Prior art keywords
phase
gray code
signal
clock signal
conversion
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Expired - Fee Related
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JP2014100185A
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English (en)
Japanese (ja)
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JP2015128278A (ja
JP2015128278A5 (enExample
Inventor
祐一 武田
祐一 武田
篤史 鈴木
篤史 鈴木
貴範 佐伯
貴範 佐伯
高橋　知宏
知宏 高橋
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Sony Corp
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Sony Corp
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Priority to JP2014100185A priority Critical patent/JP6394056B2/ja
Priority to TW103137278A priority patent/TWI657667B/zh
Priority to US15/025,378 priority patent/US10334195B2/en
Priority to PCT/JP2014/005841 priority patent/WO2015079663A1/en
Priority to CN201480063496.5A priority patent/CN105830434B/zh
Priority to CN201910972975.3A priority patent/CN110677607B/zh
Priority to KR1020167013394A priority patent/KR20160091328A/ko
Publication of JP2015128278A publication Critical patent/JP2015128278A/ja
Publication of JP2015128278A5 publication Critical patent/JP2015128278A5/ja
Application granted granted Critical
Publication of JP6394056B2 publication Critical patent/JP6394056B2/ja
Priority to US16/430,793 priority patent/US10659710B2/en
Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/004—Counters counting in a non-natural counting order, e.g. random counters
    • H03K23/005—Counters counting in a non-natural counting order, e.g. random counters using minimum change code, e.g. Gray Code
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H03M1/1255—Synchronisation of the sampling frequency or phase to the input frequency or phase
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00026—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
    • H03K2005/00052—Variable delay controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter by mixing the outputs of fixed delayed signals with each other or with the input signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/56—Input signal compared with linear ramp

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Manipulation Of Pulses (AREA)
  • Optical Modulation, Optical Deflection, Nonlinear Optics, Optical Demodulation, Optical Logic Elements (AREA)
JP2014100185A 2013-11-27 2014-05-14 Ａ／ｄ変換装置、グレイコード生成装置、撮像素子、並びに、電子機器 Expired - Fee Related JP6394056B2 (ja)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP2014100185A JP6394056B2 (ja) 2013-11-27 2014-05-14 Ａ／ｄ変換装置、グレイコード生成装置、撮像素子、並びに、電子機器
TW103137278A TWI657667B (zh) 2013-11-27 2014-10-28 Ａ／ｄ轉換裝置、格雷碼產生裝置、信號處理裝置、成像元件及電子裝置
PCT/JP2014/005841 WO2015079663A1 (en) 2013-11-27 2014-11-20 A/d conversion device with a multiphase clock generation unit based on phase interpolators
CN201480063496.5A CN105830434B (zh) 2013-11-27 2014-11-20 具有基于相位插值器的多相位时钟生成单元的a/d转换装置
US15/025,378 US10334195B2 (en) 2013-11-27 2014-11-20 A/D conversion device, gray code generation device, signal processing device, imaging element, and electronic device
CN201910972975.3A CN110677607B (zh) 2013-11-27 2014-11-20 具有基于相位插值器的多相位时钟生成单元的a/d转换装置
KR1020167013394A KR20160091328A (ko) 2013-11-27 2014-11-20 위상 보간기를 기초로 한 다상 클록 생성부를 갖는 a/d 변환 장치
US16/430,793 US10659710B2 (en) 2013-11-27 2019-06-04 A/D conversion device, gray code generation device, signal processing device, imaging element, and electronic device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2013244949 2013-11-27
JP2013244949 2013-11-27
JP2014100185A JP6394056B2 (ja) 2013-11-27 2014-05-14 Ａ／ｄ変換装置、グレイコード生成装置、撮像素子、並びに、電子機器

Publications (3)

Publication Number Publication Date
JP2015128278A JP2015128278A (ja) 2015-07-09
JP2015128278A5 JP2015128278A5 (enExample) 2017-03-09
JP6394056B2 true JP6394056B2 (ja) 2018-09-26

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US (2) US10334195B2 (enExample)
JP (1) JP6394056B2 (enExample)
KR (1) KR20160091328A (enExample)
CN (2) CN105830434B (enExample)
TW (1) TWI657667B (enExample)
WO (1) WO2015079663A1 (enExample)

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Publication number Publication date
CN110677607A (zh) 2020-01-10
TW201526551A (zh) 2015-07-01
US10659710B2 (en) 2020-05-19
US20160249004A1 (en) 2016-08-25
CN110677607B (zh) 2022-03-18
CN105830434B (zh) 2019-10-29
JP2015128278A (ja) 2015-07-09
TWI657667B (zh) 2019-04-21
WO2015079663A1 (en) 2015-06-04
US10334195B2 (en) 2019-06-25
CN105830434A (zh) 2016-08-03
KR20160091328A (ko) 2016-08-02
US20190289241A1 (en) 2019-09-19

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