JP6337099B2 - フロップトレイエリアおよび電力最適化のための回路およびレイアウト技法 - Google Patents

フロップトレイエリアおよび電力最適化のための回路およびレイアウト技法 Download PDF

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JP6337099B2
JP6337099B2 JP2016516796A JP2016516796A JP6337099B2 JP 6337099 B2 JP6337099 B2 JP 6337099B2 JP 2016516796 A JP2016516796 A JP 2016516796A JP 2016516796 A JP2016516796 A JP 2016516796A JP 6337099 B2 JP6337099 B2 JP 6337099B2
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Prior art keywords
flop
flip
scan
input
type transistor
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Japanese (ja)
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JP2016531275A5 (enExample
JP2016531275A (ja
Inventor
シャー、ジャイ・マドゥカー
スワミナサン、チェサン
ダッタ、アニメシュ
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3177—Testing of logic operation, e.g. by logic analysers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
JP2016516796A 2013-05-29 2014-05-28 フロップトレイエリアおよび電力最適化のための回路およびレイアウト技法 Active JP6337099B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/905,060 2013-05-29
US13/905,060 US9024658B2 (en) 2013-05-29 2013-05-29 Circuit and layout techniques for flop tray area and power otimization
PCT/US2014/039856 WO2014193998A1 (en) 2013-05-29 2014-05-28 Circuit and layout techniques for flop tray area and power optimization

Publications (3)

Publication Number Publication Date
JP2016531275A JP2016531275A (ja) 2016-10-06
JP2016531275A5 JP2016531275A5 (enExample) 2017-07-06
JP6337099B2 true JP6337099B2 (ja) 2018-06-06

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JP2016516796A Active JP6337099B2 (ja) 2013-05-29 2014-05-28 フロップトレイエリアおよび電力最適化のための回路およびレイアウト技法

Country Status (6)

Country Link
US (1) US9024658B2 (enExample)
EP (1) EP3004903B1 (enExample)
JP (1) JP6337099B2 (enExample)
KR (1) KR20160016890A (enExample)
CN (1) CN105247377B (enExample)
WO (1) WO2014193998A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6268461B2 (ja) 2013-03-28 2018-01-31 セイコーエプソン株式会社 半導体装置、物理量センサー、電子機器及び移動体
US9685141B2 (en) * 2014-01-31 2017-06-20 Samsung Display Co., Ltd. MDLL/PLL hybrid design with uniformly distributed output phases
US10033359B2 (en) 2015-10-23 2018-07-24 Qualcomm Incorporated Area efficient flip-flop with improved scan hold-margin
US9966953B2 (en) 2016-06-02 2018-05-08 Qualcomm Incorporated Low clock power data-gated flip-flop
US11092646B1 (en) * 2020-02-18 2021-08-17 Qualcomm Incorporated Determining a voltage and/or frequency for a performance mode
US11500016B2 (en) * 2020-12-07 2022-11-15 Taiwan Semiconductor Manufacturing Company Ltd. Circuit screening system and circuit screening method

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* Cited by examiner, † Cited by third party
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US5444404A (en) 1994-03-03 1995-08-22 Vlsi Technology, Inc. Scan flip-flop with power saving feature
WO1995030230A2 (en) * 1994-04-28 1995-11-09 Apple Computer, Inc. Scannable d-flip-flop with system independent clocking
JPH09270677A (ja) * 1995-09-05 1997-10-14 Mitsubishi Electric Corp フリップフロップ回路及びスキャンパス並びに記憶回路
US5719878A (en) 1995-12-04 1998-02-17 Motorola Inc. Scannable storage cell and method of operation
JPH1052073A (ja) * 1996-07-31 1998-02-20 Seiko Kurotsuku Kk 超音波モータの駆動回路
JPH1194914A (ja) 1997-09-22 1999-04-09 Matsushita Electric Ind Co Ltd スキャンパス制御回路
US6708303B1 (en) 1998-03-06 2004-03-16 Texas Instruments Incorporated Method and apparatus for controlling a seperate scan output of a scan circuit
US6289477B1 (en) * 1998-04-28 2001-09-11 Adaptec, Inc. Fast-scan-flop and integrated circuit device incorporating the same
US6420894B1 (en) 1999-12-29 2002-07-16 Intel Corporation Implementation of iscan cell for self-resetting dynamic circuit
JP3928938B2 (ja) * 2002-05-28 2007-06-13 シャープ株式会社 電圧変換回路および半導体装置
JP2004069492A (ja) * 2002-08-06 2004-03-04 Renesas Technology Corp フリップフロップ回路
US7237164B1 (en) 2004-04-15 2007-06-26 Marvell International Ltd. Area optimized edge-triggered flip-flop for high-speed memory dominated design
JP2006005661A (ja) * 2004-06-17 2006-01-05 Matsushita Electric Ind Co Ltd フリップフロップ回路
KR101076809B1 (ko) * 2004-06-18 2011-10-25 삼성전자주식회사 불필요한 전력소모를 줄일 수 있는 스캔 플립플롭 회로
US20060085707A1 (en) * 2004-09-28 2006-04-20 Texas Instruments Incorporated High speed energy conserving scan architecture
KR100604904B1 (ko) 2004-10-02 2006-07-28 삼성전자주식회사 스캔 입력을 갖는 플립 플롭 회로
US7315191B2 (en) * 2005-06-30 2008-01-01 Texas Instruments Incorporated Digital storage element architecture comprising dual scan clocks and reset functionality
US7543205B2 (en) * 2006-04-27 2009-06-02 Texas Instruments Incorporated Control signal synchronization of a scannable storage circuit
US7793178B2 (en) 2006-07-12 2010-09-07 Texas Instruments Incorporated Cell supporting scan-based tests and with reduced time delay in functional mode
US7649395B2 (en) 2007-05-15 2010-01-19 Ati Technologies Ulc Scan flip-flop with internal latency for scan input
JP4999632B2 (ja) * 2007-10-12 2012-08-15 オンセミコンダクター・トレーディング・リミテッド 半導体集積回路
KR20090131010A (ko) * 2008-06-17 2009-12-28 주식회사 동부하이텍 듀얼 모드 에지 트리거 플립플롭
US7893722B2 (en) * 2008-09-11 2011-02-22 Arm Limited Clock control of state storage circuitry
CN102062836B (zh) * 2009-11-17 2013-02-06 三星半导体(中国)研究开发有限公司 扫描寄存器、扫描链、芯片及其测试方法
US20110181331A1 (en) * 2010-01-24 2011-07-28 Freescale Semiconductor, Inc. Integrated circuit with leakage reduction in static nets
US8427214B2 (en) * 2010-06-03 2013-04-23 Arm Limited Clock state independent retention master-slave flip-flop
WO2012009717A1 (en) * 2010-07-16 2012-01-19 Marvell World Trade Ltd. Charge-injection sense-amp logic
US8493119B2 (en) * 2010-12-13 2013-07-23 Apple Inc. Scannable flip-flop with hold time improvements
US8502561B2 (en) * 2011-07-01 2013-08-06 Arm Limited Signal value storage circuitry with transition detector
US8578224B2 (en) * 2011-12-31 2013-11-05 Texas Instruments Incorporated High density flip-flop with asynchronous reset
CN103576082B (zh) * 2012-08-06 2018-01-12 恩智浦美国有限公司 低功率扫描触发器单元
US9020084B2 (en) * 2013-01-31 2015-04-28 Qualcomm Incorporated High frequency synchronizer

Also Published As

Publication number Publication date
US9024658B2 (en) 2015-05-05
EP3004903B1 (en) 2017-05-03
CN105247377B (zh) 2018-02-09
WO2014193998A1 (en) 2014-12-04
EP3004903A1 (en) 2016-04-13
CN105247377A (zh) 2016-01-13
KR20160016890A (ko) 2016-02-15
US20140359385A1 (en) 2014-12-04
JP2016531275A (ja) 2016-10-06

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