CN105247377B - 用于触发器盘区域和功率优化的电路和布局技术 - Google Patents

用于触发器盘区域和功率优化的电路和布局技术 Download PDF

Info

Publication number
CN105247377B
CN105247377B CN201480030877.3A CN201480030877A CN105247377B CN 105247377 B CN105247377 B CN 105247377B CN 201480030877 A CN201480030877 A CN 201480030877A CN 105247377 B CN105247377 B CN 105247377B
Authority
CN
China
Prior art keywords
trigger
input
signal
scan
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201480030877.3A
Other languages
English (en)
Chinese (zh)
Other versions
CN105247377A (zh
Inventor
J·M·沙阿
C·斯瓦米纳森
A·达塔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN105247377A publication Critical patent/CN105247377A/zh
Application granted granted Critical
Publication of CN105247377B publication Critical patent/CN105247377B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3177Testing of logic operation, e.g. by logic analysers
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541Scan latches or cell details

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
CN201480030877.3A 2013-05-29 2014-05-28 用于触发器盘区域和功率优化的电路和布局技术 Active CN105247377B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/905,060 2013-05-29
US13/905,060 US9024658B2 (en) 2013-05-29 2013-05-29 Circuit and layout techniques for flop tray area and power otimization
PCT/US2014/039856 WO2014193998A1 (en) 2013-05-29 2014-05-28 Circuit and layout techniques for flop tray area and power optimization

Publications (2)

Publication Number Publication Date
CN105247377A CN105247377A (zh) 2016-01-13
CN105247377B true CN105247377B (zh) 2018-02-09

Family

ID=51022458

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480030877.3A Active CN105247377B (zh) 2013-05-29 2014-05-28 用于触发器盘区域和功率优化的电路和布局技术

Country Status (6)

Country Link
US (1) US9024658B2 (enExample)
EP (1) EP3004903B1 (enExample)
JP (1) JP6337099B2 (enExample)
KR (1) KR20160016890A (enExample)
CN (1) CN105247377B (enExample)
WO (1) WO2014193998A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6268461B2 (ja) 2013-03-28 2018-01-31 セイコーエプソン株式会社 半導体装置、物理量センサー、電子機器及び移動体
US9685141B2 (en) * 2014-01-31 2017-06-20 Samsung Display Co., Ltd. MDLL/PLL hybrid design with uniformly distributed output phases
US10033359B2 (en) 2015-10-23 2018-07-24 Qualcomm Incorporated Area efficient flip-flop with improved scan hold-margin
US9966953B2 (en) 2016-06-02 2018-05-08 Qualcomm Incorporated Low clock power data-gated flip-flop
US11092646B1 (en) * 2020-02-18 2021-08-17 Qualcomm Incorporated Determining a voltage and/or frequency for a performance mode
US11500016B2 (en) * 2020-12-07 2022-11-15 Taiwan Semiconductor Manufacturing Company Ltd. Circuit screening system and circuit screening method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050283691A1 (en) * 2004-06-18 2005-12-22 Chae Kwan-Yeob Scan flip-flop circuit with reduced power consumption
US7237164B1 (en) * 2004-04-15 2007-06-26 Marvell International Ltd. Area optimized edge-triggered flip-flop for high-speed memory dominated design
US20080284480A1 (en) * 2007-05-15 2008-11-20 Ati Technologies Ulc Scan flip-flop with internal latency for scan input
CN101610078A (zh) * 2008-06-17 2009-12-23 东部高科股份有限公司 双模边沿触发的触发器
CN101685666A (zh) * 2008-09-11 2010-03-31 Arm有限公司 状态存储电路的时钟控制
CN102062836A (zh) * 2009-11-17 2011-05-18 三星半导体(中国)研究开发有限公司 扫描寄存器、扫描链、芯片及其测试方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444404A (en) 1994-03-03 1995-08-22 Vlsi Technology, Inc. Scan flip-flop with power saving feature
WO1995030230A2 (en) * 1994-04-28 1995-11-09 Apple Computer, Inc. Scannable d-flip-flop with system independent clocking
JPH09270677A (ja) * 1995-09-05 1997-10-14 Mitsubishi Electric Corp フリップフロップ回路及びスキャンパス並びに記憶回路
US5719878A (en) 1995-12-04 1998-02-17 Motorola Inc. Scannable storage cell and method of operation
JPH1052073A (ja) * 1996-07-31 1998-02-20 Seiko Kurotsuku Kk 超音波モータの駆動回路
JPH1194914A (ja) 1997-09-22 1999-04-09 Matsushita Electric Ind Co Ltd スキャンパス制御回路
US6708303B1 (en) 1998-03-06 2004-03-16 Texas Instruments Incorporated Method and apparatus for controlling a seperate scan output of a scan circuit
US6289477B1 (en) * 1998-04-28 2001-09-11 Adaptec, Inc. Fast-scan-flop and integrated circuit device incorporating the same
US6420894B1 (en) 1999-12-29 2002-07-16 Intel Corporation Implementation of iscan cell for self-resetting dynamic circuit
JP3928938B2 (ja) * 2002-05-28 2007-06-13 シャープ株式会社 電圧変換回路および半導体装置
JP2004069492A (ja) * 2002-08-06 2004-03-04 Renesas Technology Corp フリップフロップ回路
JP2006005661A (ja) * 2004-06-17 2006-01-05 Matsushita Electric Ind Co Ltd フリップフロップ回路
US20060085707A1 (en) * 2004-09-28 2006-04-20 Texas Instruments Incorporated High speed energy conserving scan architecture
KR100604904B1 (ko) 2004-10-02 2006-07-28 삼성전자주식회사 스캔 입력을 갖는 플립 플롭 회로
US7315191B2 (en) * 2005-06-30 2008-01-01 Texas Instruments Incorporated Digital storage element architecture comprising dual scan clocks and reset functionality
US7543205B2 (en) * 2006-04-27 2009-06-02 Texas Instruments Incorporated Control signal synchronization of a scannable storage circuit
US7793178B2 (en) 2006-07-12 2010-09-07 Texas Instruments Incorporated Cell supporting scan-based tests and with reduced time delay in functional mode
JP4999632B2 (ja) * 2007-10-12 2012-08-15 オンセミコンダクター・トレーディング・リミテッド 半導体集積回路
US20110181331A1 (en) * 2010-01-24 2011-07-28 Freescale Semiconductor, Inc. Integrated circuit with leakage reduction in static nets
US8427214B2 (en) * 2010-06-03 2013-04-23 Arm Limited Clock state independent retention master-slave flip-flop
WO2012009717A1 (en) * 2010-07-16 2012-01-19 Marvell World Trade Ltd. Charge-injection sense-amp logic
US8493119B2 (en) * 2010-12-13 2013-07-23 Apple Inc. Scannable flip-flop with hold time improvements
US8502561B2 (en) * 2011-07-01 2013-08-06 Arm Limited Signal value storage circuitry with transition detector
US8578224B2 (en) * 2011-12-31 2013-11-05 Texas Instruments Incorporated High density flip-flop with asynchronous reset
CN103576082B (zh) * 2012-08-06 2018-01-12 恩智浦美国有限公司 低功率扫描触发器单元
US9020084B2 (en) * 2013-01-31 2015-04-28 Qualcomm Incorporated High frequency synchronizer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7237164B1 (en) * 2004-04-15 2007-06-26 Marvell International Ltd. Area optimized edge-triggered flip-flop for high-speed memory dominated design
US20050283691A1 (en) * 2004-06-18 2005-12-22 Chae Kwan-Yeob Scan flip-flop circuit with reduced power consumption
US20080284480A1 (en) * 2007-05-15 2008-11-20 Ati Technologies Ulc Scan flip-flop with internal latency for scan input
CN101610078A (zh) * 2008-06-17 2009-12-23 东部高科股份有限公司 双模边沿触发的触发器
CN101685666A (zh) * 2008-09-11 2010-03-31 Arm有限公司 状态存储电路的时钟控制
CN102062836A (zh) * 2009-11-17 2011-05-18 三星半导体(中国)研究开发有限公司 扫描寄存器、扫描链、芯片及其测试方法

Also Published As

Publication number Publication date
JP6337099B2 (ja) 2018-06-06
US9024658B2 (en) 2015-05-05
EP3004903B1 (en) 2017-05-03
WO2014193998A1 (en) 2014-12-04
EP3004903A1 (en) 2016-04-13
CN105247377A (zh) 2016-01-13
KR20160016890A (ko) 2016-02-15
US20140359385A1 (en) 2014-12-04
JP2016531275A (ja) 2016-10-06

Similar Documents

Publication Publication Date Title
CN105247377B (zh) 用于触发器盘区域和功率优化的电路和布局技术
CN101720527B (zh) 用作扫描输入的具有内部延迟的扫描触发器及其操作方法
US20090300448A1 (en) Scan flip-flop device
JP3587248B2 (ja) スキャン用フリップフロップ
US8159260B1 (en) Delay chain burn-in for increased repeatability of physically unclonable functions
US9979381B1 (en) Semi-data gated flop with low clock power/low internal power with minimal area overhead
US7859310B2 (en) Semiconductor integrated circuit
US8578224B2 (en) High density flip-flop with asynchronous reset
TWI642275B (zh) 正反器電路和掃描鏈
US9020084B2 (en) High frequency synchronizer
JP2008502286A (ja) 高性能リピータモードおよび通常リピータモードを有するリピータ回路
TW201305582A (zh) 掃描測試電路
JP6430667B2 (ja) フィードバックラッチ回路
CN102680881B (zh) 测试技术和电路的设计
CN100413073C (zh) 用于避免多电源输入/输出的瞬态短路电流的集成电路
US20140298126A1 (en) Latch circuit, scan test circuit and latch circuit control method
CN113608112B (zh) 扫描输出触发器
JP2008172770A (ja) 電力ゲート論理を有する低電力レベル・センシティブ・スキャン設計ラッチに関する方法及びシステム
US8643421B1 (en) Implementing low power, single master-slave elastic buffer
JP3573703B2 (ja) 半導体装置の製造方法
JP2001324544A (ja) スキャンパステスト用フリップフロップ回路
JP5231065B2 (ja) スキャン用フリップフロップ回路
JP4077123B2 (ja) 差動信号出力回路
CN103983912B (zh) 适用于片上系统的扫描测试控制电路
JP6449633B2 (ja) スキャンフリップフロップ回路、スキャンテスト回路、半導体集積回路およびスキャンテスト方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant