JP4999632B2 - 半導体集積回路 - Google Patents
半導体集積回路 Download PDFInfo
- Publication number
- JP4999632B2 JP4999632B2 JP2007266860A JP2007266860A JP4999632B2 JP 4999632 B2 JP4999632 B2 JP 4999632B2 JP 2007266860 A JP2007266860 A JP 2007266860A JP 2007266860 A JP2007266860 A JP 2007266860A JP 4999632 B2 JP4999632 B2 JP 4999632B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- flip
- flop
- output signal
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
12 第2のAND回路 13 OR回路
14 組合せ論理回路 20 アナログ回路
21〜23 第1〜第3のアナログ回路
FF1〜FF6 第1〜第6のフリップフロップ
SEL1〜SEL6 第1〜第6のセレクタ
T1〜T4 MOSトランジスタ
Claims (5)
- 第1の回路と、
前記第1の回路に対応して設けられた複数のフリップフロップと、
スキャンテスト時に前記複数のフリップフロップをチェーン状に接続してシフトレジスタを形成する複数のセレクタと、
スキャンテスト時における前記シフトレジスタの許容動作周波数に比して、低い許容動作周波数を有する第2の回路と、
前記フリップフロップの出力信号が入力され、通常動作時には前記フリップフロップの出力信号を前記第2の回路に伝播可能にすると共に、スキャンテスト時には前記フリップフロップの出力信号を前記第2の回路に伝播不可能にするように制御するゲート回路と、を備えることを特徴とする半導体集積回路。 - 前記ゲート回路は、スキャンテスト時にはその出力信号が一定レベルに固定されることを特徴とする請求項1に記載の半導体集積回路。
- 前記第1の回路は、デジタル回路であり、前記第2の回路は、アナログ回路であることを特徴とする請求項1又は請求項2に記載の半導体集積回路。
- 前記第2の回路は、レベルシフト回路であることを特徴とする請求項1、2、3のいずれかに記載の半導体集積回路。
- 前記第1の回路は、組合せ論理回路であることを特徴とする請求項1、2、3、4のいずれかに記載の半導体集積回路。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007266860A JP4999632B2 (ja) | 2007-10-12 | 2007-10-12 | 半導体集積回路 |
TW097131680A TWI380040B (en) | 2007-10-12 | 2008-08-20 | Semiconductor integrated circuit |
US12/246,873 US7788565B2 (en) | 2007-10-12 | 2008-10-07 | Semiconductor integrated circuit |
CN2008101699253A CN101408587B (zh) | 2007-10-12 | 2008-10-09 | 半导体集成电路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007266860A JP4999632B2 (ja) | 2007-10-12 | 2007-10-12 | 半導体集積回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009097879A JP2009097879A (ja) | 2009-05-07 |
JP4999632B2 true JP4999632B2 (ja) | 2012-08-15 |
Family
ID=40564709
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007266860A Active JP4999632B2 (ja) | 2007-10-12 | 2007-10-12 | 半導体集積回路 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7788565B2 (ja) |
JP (1) | JP4999632B2 (ja) |
CN (1) | CN101408587B (ja) |
TW (1) | TWI380040B (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101982788B (zh) * | 2010-09-30 | 2012-09-19 | 哈尔滨工业大学 | 基于ieee1500标准的ip核测试传输组件及其控制方法 |
JP5889735B2 (ja) * | 2012-07-05 | 2016-03-22 | カシオ計算機株式会社 | 半導体集積回路 |
US9024658B2 (en) * | 2013-05-29 | 2015-05-05 | Qualcomm Incorporated | Circuit and layout techniques for flop tray area and power otimization |
JP7354807B2 (ja) * | 2019-12-03 | 2023-10-03 | 株式会社デンソー | 半導体集積回路 |
CN113484604B (zh) * | 2021-07-08 | 2023-04-21 | 中国人民解放军国防科技大学 | 可消除测量电路影响的set脉冲测量电路及集成电路芯片 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0654344B2 (ja) * | 1988-09-07 | 1994-07-20 | 株式会社豊田中央研究所 | スキャンパス回路 |
JP3180421B2 (ja) * | 1992-03-30 | 2001-06-25 | 日本電気株式会社 | テスト回路を内蔵したアナログ・ディジタル混在マスタ |
US5793778A (en) * | 1997-04-11 | 1998-08-11 | National Semiconductor Corporation | Method and apparatus for testing analog and digital circuitry within a larger circuit |
JP2000269436A (ja) * | 1999-03-19 | 2000-09-29 | Seiko Epson Corp | 半導体装置及びそれを用いた電子機器 |
JP4428489B2 (ja) | 1999-08-23 | 2010-03-10 | パナソニック株式会社 | 集積回路装置及びそのテスト方法 |
US7228476B2 (en) * | 2004-11-05 | 2007-06-05 | Stmicroelectronics, Inc. | System and method for testing integrated circuits at operational speed using high-frequency clock converter |
JP2006162490A (ja) * | 2004-12-09 | 2006-06-22 | Sanyo Electric Co Ltd | スキャンテスト回路 |
JP4563791B2 (ja) * | 2004-12-20 | 2010-10-13 | Okiセミコンダクタ株式会社 | 半導体集積回路 |
-
2007
- 2007-10-12 JP JP2007266860A patent/JP4999632B2/ja active Active
-
2008
- 2008-08-20 TW TW097131680A patent/TWI380040B/zh not_active IP Right Cessation
- 2008-10-07 US US12/246,873 patent/US7788565B2/en active Active
- 2008-10-09 CN CN2008101699253A patent/CN101408587B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2009097879A (ja) | 2009-05-07 |
US7788565B2 (en) | 2010-08-31 |
TW200925627A (en) | 2009-06-16 |
CN101408587A (zh) | 2009-04-15 |
CN101408587B (zh) | 2011-07-27 |
TWI380040B (en) | 2012-12-21 |
US20090106610A1 (en) | 2009-04-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7649395B2 (en) | Scan flip-flop with internal latency for scan input | |
KR101344577B1 (ko) | 집적 회로 테스트를 위한 저전력 및 영역 효율적인 스캔 셀 | |
US9291674B1 (en) | Integrated circuit with low power scan flip-flop | |
US20070016834A1 (en) | Reducing Power Dissipation During Sequential Scan Tests | |
US7444569B2 (en) | Semiconductor integrated circuit having test circuitry with reduced power consumption | |
US20110296265A1 (en) | System for testing integrated circuit with asynchronous clock domains | |
US9606177B2 (en) | Scan flip-flop circuit with dedicated clocks | |
US6788105B2 (en) | Semiconductor integrated circuit | |
US8850280B2 (en) | Scan enable timing control for testing of scan cells | |
EP1971871B1 (en) | Reduced pin count scan chain implementation | |
KR20110105153A (ko) | 플립플롭 회로 및 스캔 플립 플롭 회로 | |
JP4999632B2 (ja) | 半導体集積回路 | |
JP2010276479A (ja) | 半導体集積回路、及びそのテスト方法 | |
US6853212B2 (en) | Gated scan output flip-flop | |
JP2003043108A (ja) | フリップフロップ及びスキャンパス回路 | |
US11747398B2 (en) | Scan chain circuit and corresponding method | |
US20060242505A1 (en) | Apparatus for performing stuck fault testings within an integrated circuit | |
JP2006145307A (ja) | スキャンテスト回路 | |
JP2006194727A (ja) | 集積回路のテスト方法。 | |
JP6449633B2 (ja) | スキャンフリップフロップ回路、スキャンテスト回路、半導体集積回路およびスキャンテスト方法 | |
JP5442522B2 (ja) | 半導体集積回路のテスト回路 | |
JP2004037183A (ja) | スキャンフリップフロップ | |
JP4104634B2 (ja) | 半導体装置 | |
JP4703398B2 (ja) | 半導体集積回路およびその試験方法 | |
JP2008198773A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100127 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20110531 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20110602 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120425 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120507 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120515 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4999632 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150525 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150525 Year of fee payment: 3 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150525 Year of fee payment: 3 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |