JP6280014B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP6280014B2
JP6280014B2 JP2014201765A JP2014201765A JP6280014B2 JP 6280014 B2 JP6280014 B2 JP 6280014B2 JP 2014201765 A JP2014201765 A JP 2014201765A JP 2014201765 A JP2014201765 A JP 2014201765A JP 6280014 B2 JP6280014 B2 JP 6280014B2
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Japan
Prior art keywords
magnetic shield
shield material
semiconductor chip
lower magnetic
semiconductor device
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JP2014201765A
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English (en)
Japanese (ja)
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JP2016072492A5 (https=
JP2016072492A (ja
Inventor
直 荒井
直 荒井
之治 竹内
之治 竹内
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2014201765A priority Critical patent/JP6280014B2/ja
Priority to US14/870,078 priority patent/US9490221B2/en
Publication of JP2016072492A publication Critical patent/JP2016072492A/ja
Publication of JP2016072492A5 publication Critical patent/JP2016072492A5/ja
Application granted granted Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/656—Fan-in layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/015—Manufacture or treatment of bond wires
    • H10W72/01515—Forming coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
JP2014201765A 2014-09-30 2014-09-30 半導体装置及びその製造方法 Active JP6280014B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2014201765A JP6280014B2 (ja) 2014-09-30 2014-09-30 半導体装置及びその製造方法
US14/870,078 US9490221B2 (en) 2014-09-30 2015-09-30 Semiconductor device having multiple magnetic shield members

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014201765A JP6280014B2 (ja) 2014-09-30 2014-09-30 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2016072492A JP2016072492A (ja) 2016-05-09
JP2016072492A5 JP2016072492A5 (https=) 2017-06-01
JP6280014B2 true JP6280014B2 (ja) 2018-02-14

Family

ID=55585379

Family Applications (1)

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JP2014201765A Active JP6280014B2 (ja) 2014-09-30 2014-09-30 半導体装置及びその製造方法

Country Status (2)

Country Link
US (1) US9490221B2 (https=)
JP (1) JP6280014B2 (https=)

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KR102354370B1 (ko) * 2015-04-29 2022-01-21 삼성전자주식회사 쉴딩 구조물을 포함하는 자기 저항 칩 패키지
US10535611B2 (en) * 2015-11-20 2020-01-14 Apple Inc. Substrate-less integrated components
US9807866B2 (en) * 2015-11-30 2017-10-31 Intel Corporation Shielding mold for electric and magnetic EMI mitigation
US20170170087A1 (en) 2015-12-14 2017-06-15 Intel Corporation Electronic package that includes multiple supports
JP6407186B2 (ja) * 2016-03-23 2018-10-17 Tdk株式会社 電子回路パッケージ
JP6107998B1 (ja) * 2016-03-23 2017-04-05 Tdk株式会社 電子回路パッケージ
US11139341B2 (en) 2018-06-18 2021-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Protection of MRAM from external magnetic field using magnetic-field-shielding structure
US11088083B2 (en) * 2018-06-29 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. DC and AC magnetic field protection for MRAM device using magnetic-field-shielding structure
US11239179B2 (en) 2018-11-28 2022-02-01 Shiann-Tsong Tsai Semiconductor package and fabrication method thereof
US11211340B2 (en) * 2018-11-28 2021-12-28 Shiann-Tsong Tsai Semiconductor package with in-package compartmental shielding and active electro-magnetic compatibility shielding

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05190697A (ja) * 1992-01-10 1993-07-30 Nitto Denko Corp 半導体部品の製造方法
JP2001035973A (ja) * 1999-07-19 2001-02-09 Tokin Corp 半導体装置封止材料
JP2001127211A (ja) * 1999-10-26 2001-05-11 Nec Corp 電磁波ノイズの遮蔽部を備える半導体集積回路と該半導体集積回路の実装構造
JP4873776B2 (ja) * 2000-11-30 2012-02-08 ソニー株式会社 非接触ｉｃカード
KR100923804B1 (ko) * 2001-09-03 2009-10-27 파나소닉 주식회사 반도체발광소자, 발광장치 및 반도체발광소자의 제조방법
JP3879576B2 (ja) * 2002-04-16 2007-02-14 ソニー株式会社 磁気不揮発性メモリ素子の磁気シールドパッケージ
JP4096302B2 (ja) * 2002-12-16 2008-06-04 ソニー株式会社 磁気メモリ装置
JP2004349476A (ja) * 2003-05-22 2004-12-09 Toshiba Corp 半導体装置
JP4105654B2 (ja) * 2004-04-14 2008-06-25 富士通株式会社 垂直磁気記録媒体、磁気記憶装置、および垂直磁気記録媒体の製造方法
JP2006216911A (ja) * 2005-02-07 2006-08-17 Renesas Technology Corp 半導体装置およびカプセル型半導体パッケージ
US7183617B2 (en) * 2005-02-17 2007-02-27 Taiwan Semiconductor Manufacturing Co., Ltd. Magnetic shielding for magnetically sensitive semiconductor devices
JP4871280B2 (ja) * 2005-08-30 2012-02-08 スパンション エルエルシー 半導体装置およびその製造方法
JP5124930B2 (ja) * 2005-10-05 2013-01-23 住友ベークライト株式会社 半導体封止用エポキシ樹脂組成物及び半導体装置
JP5425461B2 (ja) * 2008-12-26 2014-02-26 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
WO2010089921A1 (ja) * 2009-02-07 2010-08-12 株式会社 村田製作所 平板状コイル付きモジュールの製造方法及び平板状コイル付きモジュール
KR101171512B1 (ko) * 2010-06-08 2012-08-06 삼성전기주식회사 반도체 패키지의 제조 방법
CN102339763B (zh) * 2010-07-21 2016-01-27 飞思卡尔半导体公司 装配集成电路器件的方法
JP2012109307A (ja) * 2010-11-15 2012-06-07 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
US8466539B2 (en) * 2011-02-23 2013-06-18 Freescale Semiconductor Inc. MRAM device and method of assembling same
JP5829562B2 (ja) * 2012-03-28 2015-12-09 ルネサスエレクトロニクス株式会社 半導体装置
KR102187809B1 (ko) * 2014-02-21 2020-12-07 삼성전자주식회사 자기 차폐부를 가지는 반도체 패키지 제조방법

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US20160093795A1 (en) 2016-03-31
JP2016072492A (ja) 2016-05-09
US9490221B2 (en) 2016-11-08

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