TWI575671B - 半導體封裝及其方法 - Google Patents
半導體封裝及其方法 Download PDFInfo
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- TWI575671B TWI575671B TW103104862A TW103104862A TWI575671B TW I575671 B TWI575671 B TW I575671B TW 103104862 A TW103104862 A TW 103104862A TW 103104862 A TW103104862 A TW 103104862A TW I575671 B TWI575671 B TW I575671B
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- 239000004065 semiconductor Substances 0.000 title claims description 31
- 238000000034 method Methods 0.000 title claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 76
- 239000002184 metal Substances 0.000 claims description 76
- 239000000463 material Substances 0.000 claims description 26
- 239000004020 conductor Substances 0.000 claims description 18
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 239000005022 packaging material Substances 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 description 8
- 239000012790 adhesive layer Substances 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 230000017525 heat dissipation Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 229910000640 Fe alloy Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- KGWWEXORQXHJJQ-UHFFFAOYSA-N [Fe].[Co].[Ni] Chemical compound [Fe].[Co].[Ni] KGWWEXORQXHJJQ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- IYRDVAUFQZOLSB-UHFFFAOYSA-N copper iron Chemical compound [Fe].[Cu] IYRDVAUFQZOLSB-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000005415 magnetization Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 235000015096 spirit Nutrition 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000010792 warming Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/80—Constructional details
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45139—Silver (Ag) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Mram Or Spin Memory Techniques (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Hall/Mr Elements (AREA)
Description
本發明係有關於一種半導體封裝及其方法,特別是有關於一種磁電阻式隨機存取記憶體晶片封裝及其方法。
磁電阻式隨機存取記憶體晶片主要是利用電子的自旋特性,透過磁性結構中自由層的磁化方向不同所產生之磁阻變化來記錄訊號的”0”與”1”,其運作的基本原理與在硬碟上存儲數據一樣,所儲存的資料具有永久性,直到被外界的磁場影響之後,才會改變這個磁性數據。其耗能低及反應速度快的特性,和靜態隨機存取記憶體(SRAM)相同,而其積集度高,和動態隨機存取記憶體(DRAM)相同。換句話說,MRAM具備了SRAM和DRAM共同的優點,MRAM在市場上大量運用的機會是指日可待的。
由於MRAM的操作特性,需要隔絕不必要,或者非讀寫操作的磁場影響,因此在MRAM的封裝上,需要做磁場隔絕之保護。習知外部磁場隔絕結構,係透過一金屬層遮蔽晶片,以達到磁屏蔽的效果。目前做法有二種,一種是直接貼附於晶片的主動表面,一種是形成於封裝材料之外。第一種作法的缺點在於,其對於晶片對外連接的導線(wire),並無法提供磁屏蔽的效果,外部磁場可能經由晶片的打線區域(wire-bonding region)滲入晶片中,而造成磁阻改變。而第二種做法,一般需要讓部分導線暴露
於封裝材料外,然後經由濺鍍方式在封裝材料外形成金屬層,以形成磁屏蔽。此種方法不但需要特殊機台,製程複雜,且容易造成導線偏移(wire sweep),在後續切割封裝材料時,刀具會接觸金屬層,容易產生毛邊或者造成刀具磨損。
本發明的觀點之一,就是提出一種半導體封裝及其方法,可以解決上述習知技術的缺點。
本發明的另一觀點在於,提供一種半導體封裝及其方法,可以包覆打線區域及包覆導線,且防止導線偏移。
本發明的再一觀點在於,提供一種半導體封裝及其方法,無須特殊機台,可以簡化製程。
根據本發明的上述觀點,提供一種半導體封裝包括:一封裝載體、一晶片、一薄膜、一第一屏蔽金屬板以及一封裝材料。其中封裝載體,具有至少一導體部件;晶片具有一主動表面及對應的一晶片背面,晶片以背面貼附於封裝載體上。其中主動表面具有至少一接點,接點以一導線與導體部件電性連接。薄膜則配置於主動表面上,且包覆部分導線。第一屏蔽金屬板配置於薄膜上;封裝材料包覆晶片、導線、至少部分封裝載體、薄膜以及至少部分第一屏蔽金屬板。
根據本發明的某些實施例,半導體封裝更包括一第二屏蔽金屬板配置於晶片與封裝載體之間。其中第一屏蔽金屬板及第二屏蔽金屬板之材質包括鐵鎳合金。
根據本發明的某些實施例,其中封裝載體包括一導線架,而
導體部件為一引腳。根據本發明的其他實施例,封裝載體包括一電路板基板,而導體部件為一線路。
根據本發明的某些實施例,晶片包括一磁電阻式隨機存取記憶體晶片(MRAM)。
根據本發明的上述觀點,提供一種半導體封裝方法,包括:提供一封裝載體,封裝載體具有至少一導體部件。提供一晶片,其中晶片具有一主動表面及對應的一晶片背面,將晶片以背面貼附於封裝載體上,其中主動表面具有至少一接點。以一導線電性連接接點與導體部件。提供一第一屏蔽金屬板,且第一屏蔽金屬板上具有一薄膜,將第一屏蔽金屬板覆蓋於主動表面上,使得薄膜覆蓋主動表面,且包覆部分導線。提供一封裝材料、包覆晶片、導線、至少部分封裝載體、薄膜以及至少部分第一屏蔽金屬板。
根據本發明的某些實施例,在提供晶片前,更包括貼附一第二屏蔽金屬板於封裝載體上,且晶片係以背面貼附於第二屏蔽金屬板上。
根據本發明的某些實施例,其中第一屏蔽金屬板及第二屏蔽金屬板之材質包括鐵鎳合金。其中晶片包括一磁電阻式隨機存取記憶體晶片(MRAM)。
根據本發明的半導體封裝及其方法,屏蔽金屬板可以包覆打線區域及包覆導線,且防止導線偏移。而屏蔽金屬板覆蓋於晶片的主動表面並無須特殊機台,因此可以簡化製程。
100‧‧‧導線架
102‧‧‧晶片座
104‧‧‧導腳
106‧‧‧第二屏蔽金屬板
108,118‧‧‧黏著層
110‧‧‧晶片
112‧‧‧主動表面
120‧‧‧導線
122‧‧‧第一屏蔽金屬板
124‧‧‧薄膜
126‧‧‧封裝材料
200‧‧‧球柵陣列封裝基板
202‧‧‧焊墊
204‧‧‧焊球墊
114‧‧‧晶片背面
116‧‧‧接點
206‧‧‧焊球
圖一至圖五繪示根據本發明的一種半導體封裝方法,各製程
步驟的剖面示意圖。
圖六繪示根據本發明另一實施例,一種半導體封裝的剖面示意圖。
圖七繪示根據本發明再一實施例,一種半導體封裝的剖面示意圖。
關於本發明的優點,精神與特徵,將以實施例並參照所附圖式,進行詳細說明與討論。值得注意的是,為了讓本發明能更容易理解,後附的圖式僅為示意圖,相關尺寸並非以實際比例繪示。
為了讓本發明的優點,精神與特徵可以更容易且明確地了解,後續將以實施例並參照所附圖式進行詳述與討論。值得注意的是,這些實施例僅為本發明代表性的實施例,其中所舉例的特定方法,裝置,條件,材質等並非用以限定本發明或對應的實施例。
本發明的半導體封裝結構及其方法之後述的實施例,係主要針對磁電阻式隨機存取記憶體晶片(MRAM)的封裝,然而並非限定於此種晶片封裝,任何需要磁屏蔽之晶片,都可以利用本發明的封裝結構及方法。
請參照圖一至圖五,其繪示根據本發明的一種半導體封裝方法,各製程步驟的剖面示意圖。根據本發明的某些實施例,本發明的半導體封裝係建構於一封裝載體上,而封裝載體具有至少一導體部件。在本實施例中,以導線架(lead frame)作為封裝載體為例,如圖一所示,導線架100包括一晶片座102,及環繞於晶片座102周圍的多個導腳104(即導體部件)。而導線架100的材質包括銅、銅合金、鐵合金、鐵鎳合金、銅鐵合金、鐵鈷
鎳合金等等,且其表面可以局部性或全面性,進行鍍層處理,而鍍層材料包括銅、鎳、銀、錫合金、鈀、鉑、金等等。
請參照圖二,為了強化晶片背面的磁屏蔽,較佳是在晶片座102上貼附一第二屏蔽金屬板106,比如是一鐵鎳合金金屬板,可以提供極佳的磁屏蔽作用。而第二屏蔽金屬板106可以透過一黏著層108,貼附於晶片座102上。黏著層108比如是一導熱膠,可以強化晶片背面的散熱,或者是一黏晶膠(DAF)或貼帶(tape)。接著,請參照圖三,將一晶片110,比如是磁電阻式隨機存取記憶體晶片(MRAM),貼附於第二屏蔽金屬板106上。晶片110具有一主動表面112及一對應之晶片背面114,主動表面112具有多個接點116,用以將內部元件與電路對外連接;而晶片背面114係藉由一黏著層118,貼附於第二屏蔽金屬板106上。黏著層118比如是一導熱膠,可以強化晶片背面的散熱,或者是黏晶膠(DAF)或一貼帶。然後,進行一打線製程(wire bonding),以一導線120,比如是金線、銅線、銀線或其合金線,電性連接接點116與導腳104。
請參照圖四,提供一第一屏蔽金屬板122,且第一屏蔽金屬板122上具有一薄膜124,該薄膜124可預先形成於第一屏蔽金屬板122上,再切割形成單獨構件,接著,再將第一屏蔽金屬板122覆蓋於主動表面112上,使得薄膜124覆蓋主動表面112,且包覆部分導線120。其中薄膜124可以是一種絕緣膠(non-conductive paste),並且具有導線穿透能力(wire penetrating capability),亦稱為FOW(Film over wire),所以第一屏蔽金屬板122覆蓋於主動表面112時,導線120的一部份可以穿透薄膜124,而包覆於薄膜124中。接著,會進行適當的加溫,使得薄膜124固化(curing)。
請參照圖五,接著進行一封裝步驟,以一封裝材料126,包覆晶片106、導線120、部分封裝載體100(及部分的晶片座102及導腳104),薄膜124以及第一屏蔽金屬板122。更詳細地說,封裝材料126可以是一絕緣的封裝膠,將圖四中的元件放入一模穴(未繪示)中,然後將封裝材料126填充於模穴中,以包覆圖四中的元件,且暴露出晶片座102及導腳104的下表面。暴露出的晶片座102下表面除了可以幫助晶片散熱,還可以做為對外的接地接點。而暴露出的導腳104下表面作為對外電性連接之接點。至此,已完成了本發明的半導體封裝。
因此,在某些實施例中,本發明的半導體封裝,在結構上主要包括:一封裝載體100、一晶片110、一薄膜124、一第一屏蔽金屬板122、第二屏蔽金屬板106、以及一封裝材料126。如圖五所示,其中封裝載體100,具有至少一導體部件(即導腳104);晶片110具有一主動表面112及對應的一晶片背面114,晶片110以晶片背面114貼附於第二屏蔽金屬板106上,再貼附於封裝載體100(例如是晶片座102)上。其中主動表面112具有至少一接點116,接點116以一導線120與導體部件(例如是導腳104)電性連接。薄膜124則配置於主動表面112上,且包覆部分導線120。第一屏蔽金屬板122配置於薄膜124上;封裝材料126包覆晶片110、導線120、至少部分封裝載體100、薄膜124、第二屏蔽金屬板106以及第一屏蔽金屬板122。
值得一提的是,第一屏蔽金屬板122與第二屏蔽金屬板106可為設計成相同形狀及大小,而在某些實施例中,第一屏蔽金屬板122與第二屏蔽金屬板106亦可為不同形狀及大小。
請參照圖六,其繪示根據本發明另一實施例,一種半導體封
裝的剖面示意圖。值得一提的是,在某些實施例中,如果所選用的封裝載體100(如圖一所示)之材質,尤其是晶片座102之材質為一磁屏蔽材質,比如是鐵鎳合金或其它類似材質,則上述實施例中的第二屏蔽金屬板106(如圖五所示)是可以省略的。因此,如圖六所示,晶片110以晶片背面114,藉由一黏著層118,直接貼附於晶片座102上,其他結構則與圖五實施例中相似。在此實施例中,第一屏蔽金屬板122,提供晶片110主動表面112方向的磁場屏蔽保護,而晶片座102則提供晶片110之晶片背面114方向的磁場屏蔽保護。
請參照圖七,其繪示根據本發明再一實施例,一種半導體封裝的剖面示意圖。本發明的半導體封裝,所選用的封裝載體除了上述的導線架外,也可以是其他種類的封裝載體(package carrier)。以圖七為例,在某些實施例中,封裝載體也可以是一球柵陣列封裝基板200(Ball Grid Array Substrate,BGA substrate)。習知的球柵陣列封裝基板200是由一高積集度的印刷電路板所構成,做為晶片與外部電路連接的媒介,而其電性連接的途徑包含了晶片連接的焊墊202(bonding pad),藉由內部的多層印刷電路(未繪示),焊球墊204(ball pad)以及焊球206(solder ball),與外部電路電性連接。因此在球柵陣列封裝基板200中,焊墊202、焊球墊204以及焊球206就構成了前述的「導體部件」。如圖七所示,晶片110的接點116,藉由導線120連接焊墊202,並經由焊球墊204以及焊球206與外部電路電性連接。另外值得一提的是,第一屏蔽金屬板122除了提供晶片110在主動表面112方向的磁場屏蔽,另外由於其為金屬材質,所以也可以提供良好的散熱途徑。因此,在本發明的某些實施例中,為了加強晶片的散熱效果,封裝材料126可以選
擇性只包覆第一屏蔽金屬板122的部分,而讓其外側表面暴露出來,以提高散熱效果,如圖七所示。
綜上所述,本發明的半導體封裝及其方法,屏蔽金屬板可以透過薄膜包覆打線區域及包覆導線,涵蓋整個晶片的主動表面,可以提供良好的磁場屏蔽效果,並且防止導線偏移。而屏蔽金屬板覆蓋於晶片的主動表面的製程並無須特殊機台,因此可以簡化製程。
藉由以上較佳具體實施例之詳述,係希望能更加清楚描述本發明之特徵與精神,而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地,其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本創作之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧導線架
102‧‧‧晶片座
104‧‧‧導腳
106‧‧‧屏蔽金屬板
108,118‧‧‧黏著層
110‧‧‧晶片
112‧‧‧主動表面
114‧‧‧晶片背面
116‧‧‧接點
120‧‧‧導線
122‧‧‧第一屏蔽金屬板
124‧‧‧薄膜
126‧‧‧封裝材料
Claims (10)
- 一種半導體封裝,包括:一封裝載體,具有至少一導體部件;一晶片,具有一主動表面及對應的一晶片背面,該晶片以該背面貼附於該封裝載體上,其中該主動表面具有至少一接點,該接點以一導線與該導體部件電性連接;一薄膜,配置於該主動表面上,且包覆部分該導線;一第一屏蔽金屬板,配置於該薄膜上;一第二屏蔽金屬板,配置於該晶片與該封裝載體之間;以及一封裝材料,包覆該晶片、該導線、至少部分該封裝載體、該薄膜以及至少部分該第一屏蔽金屬板與該第二屏蔽金屬板;其中,該第一屏蔽金屬板與該第二屏蔽金屬板之面積皆大於該晶片,且該第一屏蔽金屬板與該第二屏蔽金屬板均完全覆蓋該晶片;其中,該第一屏蔽金屬板與該薄膜邊緣切齊。
- 如請求項1所述之半導體封裝,其中該第一屏蔽金屬板之材質包括鐵鎳合金。
- 如請求項1所述之半導體封裝,其中該第二屏蔽金屬板之材質包括鐵鎳合金。
- 如請求項1所述之半導體封裝,其中該封裝載體包括一導線架,且該導體部件為一引腳。
- 如請求項1所述之半導體封裝,其中該封裝載體包括一電路板基板,且該導體部件為一線路。
- 如請求項1所述之半導體封裝,其中該晶片包括一磁電阻式隨機存取記憶體晶片(MRAM)。
- 一種半導體封裝方法,包括:提供一封裝載體,該封裝載體具有至少一導體部件;提供一晶片,該晶片具有一主動表面及對應的一晶片背面,將該晶片以該背面貼附於該封裝載體上,其中該主動表面具有至少一接點;以一導線電性連接該接點與該導體部件;提供一第一屏蔽金屬板,且該第一屏蔽金屬板上具有一薄膜,其中,該薄膜預先形成於該第一屏蔽金屬板後,再一同切割該第一屏蔽金屬板,將切割後之該第一屏蔽金屬板覆蓋於該主動表面上,使得該薄膜覆蓋該主動表面,且包覆部分該導線;貼附一第二屏蔽金屬板於該封裝載體上,且該晶片係以該背面貼附於該第二屏蔽金屬板上;以及提供一封裝材料,包覆該晶片、該導線、至少部分該封裝載體、該薄膜以及至少部分該第一屏蔽金屬板與該第二屏蔽金屬板;其中,該第一屏蔽金屬板與該第二屏蔽金屬板之面積皆大於該晶片,且該第一屏蔽金屬板與該第二屏蔽金屬板均完全覆蓋該晶片。
- 如請求項7所述之半導體封裝方法,其中該第一屏蔽金屬板之材質包括鐵鎳合金。
- 如請求項7所述之半導體封裝方法,其中該第二屏蔽金屬板之材質包括鐵鎳合金。
- 如請求項7所述之半導體封裝方法,其中該晶片包括一磁電阻式隨機存取 記憶體晶片(MRAM)。
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