JP6173340B2 - バス上の複数のデータ線を介してデータを送るシステムおよび方法 - Google Patents

バス上の複数のデータ線を介してデータを送るシステムおよび方法 Download PDF

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JP6173340B2
JP6173340B2 JP2014547498A JP2014547498A JP6173340B2 JP 6173340 B2 JP6173340 B2 JP 6173340B2 JP 2014547498 A JP2014547498 A JP 2014547498A JP 2014547498 A JP2014547498 A JP 2014547498A JP 6173340 B2 JP6173340 B2 JP 6173340B2
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slimbus
data
data line
component
port
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JP2015506042A5 (enExample
JP2015506042A (ja
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ハンス・ゲオルク・グルーバー
マゲシュ・ハリハラン
ジュリオ・アルセオ
シュレン・モーハン
アリス・バラトソス
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/70—Admission control; Resource allocation
    • H04L47/72—Admission control; Resource allocation using reservation actions during connection setup
    • H04L47/726—Reserving resources in multiple paths to be used simultaneously
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Dc Digital Transmission (AREA)
JP2014547498A 2011-12-16 2012-12-14 バス上の複数のデータ線を介してデータを送るシステムおよび方法 Expired - Fee Related JP6173340B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161576840P 2011-12-16 2011-12-16
US61/576,840 2011-12-16
US13/714,140 2012-12-13
US13/714,140 US9929972B2 (en) 2011-12-16 2012-12-13 System and method of sending data via a plurality of data lines on a bus
PCT/US2012/069800 WO2013090752A1 (en) 2011-12-16 2012-12-14 System and method of sending data via a plurality of data lines on a bus

Publications (3)

Publication Number Publication Date
JP2015506042A JP2015506042A (ja) 2015-02-26
JP2015506042A5 JP2015506042A5 (enExample) 2016-01-21
JP6173340B2 true JP6173340B2 (ja) 2017-08-02

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JP2014547498A Expired - Fee Related JP6173340B2 (ja) 2011-12-16 2012-12-14 バス上の複数のデータ線を介してデータを送るシステムおよび方法

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US (1) US9929972B2 (enExample)
EP (1) EP2791810B1 (enExample)
JP (1) JP6173340B2 (enExample)
KR (1) KR20140113632A (enExample)
CN (1) CN103975317B (enExample)
IN (1) IN2014MN00902A (enExample)
WO (1) WO2013090752A1 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8966302B2 (en) * 2010-06-23 2015-02-24 Broadcom Corporation Method for power management of data buses in electronic devices
US9904652B2 (en) * 2013-11-14 2018-02-27 Qualcomm Incorporated System and method of sending data via additional secondary data lines on a bus
US10509761B2 (en) * 2013-11-14 2019-12-17 Qualcomm Incorporated System and method of sending data via additional secondary data lines on a bus
CN105306380B (zh) * 2014-07-17 2018-08-17 炬芯（珠海）科技有限公司 数据传输方法及其装置和应用
US20160062729A1 (en) * 2014-09-03 2016-03-03 Qualcomm Incorporated Multi-channel audio communication in a serial low-power inter-chip media bus (slimbus) system
US20160142455A1 (en) * 2014-11-14 2016-05-19 Qualcomm Incorporated Multi-channel audio alignment schemes
US20160142454A1 (en) * 2014-11-14 2016-05-19 Qualcomm Incorporated Multi-channel audio alignment schemes
US9841940B2 (en) 2015-06-05 2017-12-12 Qualcomm Incorporated Power reduction through clock management
US10852495B2 (en) * 2015-09-25 2020-12-01 Intel Corporation Microelectronic package communication using radio interfaces connected through wiring
CN107643994B (zh) * 2016-07-20 2021-11-30 中兴通讯股份有限公司 终端、终端外设、信号发送及接收方法、数据传输系统
US20180285292A1 (en) * 2017-03-28 2018-10-04 Qualcomm Incorporated System and method of sending data via additional secondary data lines on a bus
CN110287138A (zh) * 2019-06-12 2019-09-27 京微齐力(北京)科技有限公司 一种集成fpga和mipi的电路装置及装置中信号传输方法
CN110825344A (zh) * 2019-11-12 2020-02-21 天津飞腾信息技术有限公司 一种异步数据传输方法和结构
CN111324568A (zh) * 2020-02-20 2020-06-23 深圳震有科技股份有限公司 一种多数据mdio总线

Family Cites Families (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE756377A (fr) * 1969-09-19 1971-03-01 Burroughs Corp Commande de lignes de communication de donnees
US3766531A (en) * 1972-03-13 1973-10-16 Honeywell Inf Systems Communication line multiplexing apparatus having a main memory and an input/output memory
CH584488A5 (enExample) * 1975-05-05 1977-01-31 Ibm
US4547880A (en) * 1983-05-13 1985-10-15 Able Computer Communication control apparatus for digital devices
US5008880A (en) * 1988-03-14 1991-04-16 Sharp Kabushiki Kaisha Data transmission apparatus
JPH06103898B2 (ja) 1991-05-27 1994-12-14 メガソフト株式会社 シリアル伝送のための機能を利用したパラレル伝送方法
WO1994018766A1 (en) * 1993-02-09 1994-08-18 Dsc Communications Corporation High-speed packet bus
JP3071976B2 (ja) * 1993-03-29 2000-07-31 株式会社日立製作所 通信システムのバス型クロック供給方式
US5557614A (en) * 1993-12-22 1996-09-17 Vlsi Technology, Inc. Method and apparatus for framing data in a digital transmission line
US5815692A (en) * 1995-12-15 1998-09-29 National Semiconductor Corporation Distributed clock generator
DE69731074T2 (de) * 1997-04-30 2005-10-06 Hewlett-Packard Development Co., L.P., Houston Anordnung und Verfahren zur Übertragung von Daten über eine Vielzahl von Kanälen
US6079024A (en) * 1997-10-20 2000-06-20 Sun Microsystems, Inc. Bus interface unit having selectively enabled buffers
US6275498B1 (en) 1998-03-19 2001-08-14 3Com Corporation Extended PHY addressing
US6101567A (en) * 1998-06-03 2000-08-08 Lucent Technologies Inc. Parallel backplane physical layer interface with scalable data bandwidth
KR100264866B1 (ko) * 1998-07-13 2000-09-01 윤종용 다수의 트렁크 기능을 지원하는 디지털 트렁크회로
JP2000173173A (ja) 1998-12-04 2000-06-23 Victor Co Of Japan Ltd 伝送方法、送信装置及び受信装置
JP3465227B2 (ja) 2000-01-26 2003-11-10 日本電気エンジニアリング株式会社 電話端末装置
US6606675B1 (en) * 2000-07-20 2003-08-12 Rambus, Inc. Clock synchronization in systems with multi-channel high-speed bus subsystems
SE0004832L (sv) * 2000-12-22 2002-02-26 Ericsson Telefon Ab L M Digitalt bussystem
US7305008B2 (en) * 2001-03-14 2007-12-04 Siemens Communications, Inc. Parallel bus LAN
EP1862911B1 (en) 2001-07-25 2011-03-23 Sony Corporation Interface device
US20030158990A1 (en) * 2001-12-11 2003-08-21 Allen Gregory M. Method and apparatus of disabling the pull-up on a USB type of data line
KR100454126B1 (ko) 2002-01-15 2004-10-26 삼성전자주식회사 분리된 클록 라인을 구비한 정보 처리 시스템
US7337344B2 (en) * 2003-01-31 2008-02-26 Point Grey Research Inc. Methods and apparatus for synchronizing devices on different serial data buses
US7136953B1 (en) * 2003-05-07 2006-11-14 Nvidia Corporation Apparatus, system, and method for bus link width optimization
US7188263B1 (en) * 2003-05-07 2007-03-06 Nvidia Corporation Method and apparatus for controlling power state of a multi-lane serial bus link having a plurality of state transition detectors wherein powering down all the state transition detectors except one
US7469311B1 (en) * 2003-05-07 2008-12-23 Nvidia Corporation Asymmetrical bus
US6973519B1 (en) * 2003-06-03 2005-12-06 Lexar Media, Inc. Card identification compatibility
US20040252800A1 (en) * 2003-06-13 2004-12-16 Kishore Kota Multi-channel line interface unit with on-chip clock management
DE10344818B4 (de) * 2003-09-27 2008-08-14 Qimonda Ag Vorrichtung zum Kalibrieren der relativen Phase zweier Empfangssignale eines Speicherbausteins
US7158536B2 (en) 2004-01-28 2007-01-02 Rambus Inc. Adaptive-allocation of I/O bandwidth using a configurable interconnect topology
TWI233736B (en) * 2004-03-09 2005-06-01 Benq Corp Data rate adjustment device and system thereof
US7197591B2 (en) * 2004-06-30 2007-03-27 Intel Corporation Dynamic lane, voltage and frequency adjustment for serial interconnect
CN100547933C (zh) 2004-12-13 2009-10-07 埃派克森微电子有限公司 用于时钟信号同步的系统和方法
US7627069B2 (en) * 2005-01-27 2009-12-01 Rambus Inc. Digital transmit phase trimming
US7245552B2 (en) * 2005-06-22 2007-07-17 Infineon Technologies Ag Parallel data path architecture
KR100976290B1 (ko) * 2005-11-29 2010-08-16 엔엑스피 비 브이 버스 스테이션 회로, 다수의 버스 스테이션 회로를 포함하는 전자 시스템, 버스 스테이션 회로의 동작 방법 및 메시지 전송 방법
KR100805836B1 (ko) * 2006-07-26 2008-02-21 삼성전자주식회사 버스 폭 설정 장치, 디스플레이 장치 그리고 버스 폭 설정방법
JP5205819B2 (ja) * 2007-06-06 2013-06-05 日本電気株式会社 通信システムおよびそのパケットスケジューリング方法ならびに送信ノード
US7949817B1 (en) * 2007-07-31 2011-05-24 Marvell International Ltd. Adaptive bus profiler
US20090063889A1 (en) * 2007-09-05 2009-03-05 Faisal Dada Aligning data on parallel transmission lines
US20090074407A1 (en) * 2007-09-14 2009-03-19 Sierra Monolithics, Inc. High-speed serializer, related components, systems and methods
US7809869B2 (en) * 2007-12-20 2010-10-05 International Business Machines Corporation Throttling a point-to-point, serial input/output expansion subsystem within a computing system
US8103918B2 (en) * 2008-03-25 2012-01-24 Arm Limited Clock control during self-test of multi port memory
US8661173B2 (en) 2008-03-31 2014-02-25 Intel Corporation USB data striping
US8341303B2 (en) 2008-06-30 2012-12-25 Intel Corporation Asymmetrical universal serial bus communications
US20100005212A1 (en) * 2008-07-01 2010-01-07 International Business Machines Corporation Providing a variable frame format protocol in a cascade interconnected memory system
WO2010026446A1 (en) * 2008-09-04 2010-03-11 Freescale Semiconductor, Inc. Method and apparatus for transmitting data
US8495310B2 (en) * 2008-09-22 2013-07-23 Qimonda Ag Method and system including plural memory controllers and a memory access control bus for accessing a memory device
US20100191995A1 (en) 2009-01-26 2010-07-29 Koby Levy In-Band Sleep Protocol for Embedded Bus
JP5333753B2 (ja) * 2009-04-07 2013-11-06 Ｎｌｔテクノロジー株式会社 液晶表示装置及び信号処理方法
US8621128B2 (en) * 2009-12-04 2013-12-31 St-Ericsson Sa Methods and systems for reliable link startup
US9355051B2 (en) * 2010-09-10 2016-05-31 Cypress Semiconductor Corporation Apparatus, method, and manufacture for using a read preamble to optimize data capture
US8762760B2 (en) * 2010-09-14 2014-06-24 Xilinx, Inc. Method and apparatus for adaptive power control in a multi-lane communication channel
JP5598220B2 (ja) * 2010-09-30 2014-10-01 ソニー株式会社 送信装置、送信方法、受信装置、受信方法および送受信システム
US8681839B2 (en) * 2010-10-27 2014-03-25 International Business Machines Corporation Calibration of multiple parallel data communications lines for high skew conditions
US8732376B2 (en) * 2010-11-19 2014-05-20 Sharp Kabushiki Kaisha Data forwarding circuit, data forwarding method, display device, host-side device, and electronic apparatus
US8745455B2 (en) * 2010-11-23 2014-06-03 Intel Corporation Providing an on-die logic analyzer (ODLA) having reduced communications
US9065674B2 (en) 2011-04-29 2015-06-23 Qualcomm Incorporated Multiple slimbus controllers for slimbus components
US9043634B2 (en) 2011-04-29 2015-05-26 Qualcomm Incorporated Methods, systems, apparatuses, and computer-readable media for waking a SLIMbus without toggle signal
US9736548B2 (en) * 2011-06-08 2017-08-15 Qualcomm Incorporated Multipath rate adaptation

Also Published As

Publication number Publication date
KR20140113632A (ko) 2014-09-24
US9929972B2 (en) 2018-03-27
CN103975317B (zh) 2017-06-20
IN2014MN00902A (enExample) 2015-04-17
WO2013090752A1 (en) 2013-06-20
EP2791810A1 (en) 2014-10-22
EP2791810B1 (en) 2016-11-16
US20130156044A1 (en) 2013-06-20
CN103975317A (zh) 2014-08-06
JP2015506042A (ja) 2015-02-26

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