WO2022121199A1 - Qspi控制器，图像处理器及闪存访问方法 - Google Patents

Qspi控制器，图像处理器及闪存访问方法 Download PDF

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Publication number
WO2022121199A1
WO2022121199A1 PCT/CN2021/087349 CN2021087349W WO2022121199A1 WO 2022121199 A1 WO2022121199 A1 WO 2022121199A1 CN 2021087349 W CN2021087349 W CN 2021087349W WO 2022121199 A1 WO2022121199 A1 WO 2022121199A1
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stage
state machine
qspi
flash memory
assignment
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PCT/CN2021/087349
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English (en)
French (fr)
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刘刚强
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长沙景嘉微电子股份有限公司
长沙景美集成电路设计有限公司
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Publication of WO2022121199A1 publication Critical patent/WO2022121199A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
    • G06F9/4451—User profiles; Roaming
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of computer technology, and in particular, to a QSPI controller, an image processor and a flash memory access method.
  • serial Peripheral Interface Serial Peripheral Interface
  • SPI Serial Peripheral Interface
  • the embodiments of the present application provide a QSPI controller and a flash memory access method, which solve the problem of low data transmission speed in flash memory access.
  • a QSPI controller includes: an on-chip bus interface, a sending FIFO memory, a receiving FIFO memory, and a transceiver control module; the on-chip bus The interface is used to connect with the AHB bus to obtain configuration commands; the sending FIFO memory is used to store the sent data; the receiving FIFO memory is used to store the received data; the transceiver control module is used to store the received data according to the configuration
  • the command controls the state machine to jump in various stages, and outputs the communication signal to the flash memory through the QSPI bus.
  • an image processor including the QSPI controller provided in the first aspect, a bus interconnection system, and a central processing unit; the bus interconnection system is respectively connected to the The central processing connection and the PCIe bus connection; the bus interconnection system is connected with the QSPI controller through the AHB bus; the QSPI controller is connected with the flash memory through the QSPI bus.
  • a flash memory access method includes: obtaining a configuration command, where the configuration command is used to configure a state machine in the QSPI controller according to the QSPI protocol; A configuration command controls the state machine to jump in various stages, and outputs a communication signal to the flash memory.
  • a flash memory access device includes: an acquisition module, configured to acquire a configuration command, where the configuration command is used to configure a state in the QSPI controller according to a QSPI protocol
  • the access module is used to control the state machine to jump in various stages according to the configuration command, and output a communication signal to the flash memory.
  • an electronic device includes one or more processors; a memory; and one or more application programs, wherein the one or more application programs are stored in In the memory and configured to be executed by the one or more processors, the one or more programs are configured to perform a method as applied to an electronic device as described above.
  • the embodiments of the present application provide a computer-readable storage medium, where a program code is stored in the computer-readable storage medium, wherein the above method is executed when the program code is running .
  • a configuration command is obtained, and the configuration command is used to configure the state machine in the QSPI controller according to the QSPI protocol; according to the configuration command , control the state machine to jump in each stage, and output communication signals to the flash memory.
  • a QSPI controller is designed, the state machine in the QSPI controller is controlled to jump in various stages through configuration commands, and the access to the flash memory is realized by outputting communication signals. Based on the QSPI protocol, two-wire or four-wire access can be realized, improving the speed of data transfer in flash memory access.
  • FIG. 1 is a structural diagram of a QSPI controller provided by an embodiment of the application.
  • Fig. 2 is a schematic diagram of the connection of a QSPI controller in an image processor provided by an embodiment of the application;
  • FIG. 3 is a flowchart of a flash memory access method provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of jumping of a state machine in an idle phase according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of jumping of a state machine in an instruction phase according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of jumping of a state machine in an address phase according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of jumping of a state machine in a byte alternation stage provided by an embodiment of the present application.
  • FIG. 8 is a functional block diagram of a flash memory access device provided by an embodiment of the present application.
  • FIG. 9 is a structural block diagram of an electronic device for executing the flash memory access method according to the embodiment of the present application proposed by the embodiment of the present application.
  • serial Peripheral Interface Serial Peripheral Interface
  • SPI Serial Peripheral Interface
  • QSPI is an extension of the SPI interface, which is more widely used than SPI.
  • SPI protocol On the basis of the SPI protocol, the function of QSPI has been enhanced, a queue transmission mechanism has been added, and a queue serial peripheral interface protocol has been introduced.
  • the user can transfer data 4 times faster than the SPI interface.
  • QSPI starts the transmission, until the end of the transmission, the transmission process does not require CPU intervention, which greatly improves the transmission efficiency.
  • the embodiments of the present application provide a QSPI controller and a flash memory access method.
  • the QSPI controller includes an on-chip bus interface, a sending FIFO memory, a receiving FIFO memory, and a transceiver control module; the The on-chip bus interface is used to connect with the AHB bus to obtain configuration commands; the sending FIFO memory is used to store the sending data; the receiving FIFO memory is used to store the received data; the transceiver control module is used to store the received data according to the The above configuration command controls the state machine to jump in each stage, and outputs the communication signal to the flash memory through the QSPI bus.
  • a QSPI controller is designed, the state machine in the QSPI controller is controlled to jump in various stages through configuration commands, and the access to the flash memory is realized by outputting communication signals. Based on the QSPI protocol, two-wire or four-wire access can be realized, improving the speed of data transfer in flash memory access.
  • the solutions in the embodiments of the present application may be implemented by using a computer hardware description language, for example, the Verilog language.
  • FIG. 1 a structural block diagram of a QSPI controller provided by an embodiment of the present application is shown.
  • the QSPI controller 10 includes an on-chip bus interface 11, a sending-in, first-out (First Input First Output, FIFO) memory 12, a receiving first-in, first-out (First Input First Output, FIFO) memory 13, and a transceiver control module 14.
  • the on-chip bus interface 11 is used to connect with the AHB bus to obtain configuration commands
  • the transmit FIFO memory 12 is used to store the transmit data
  • the receive FIFO memory 13 is used to store the receive data
  • the transmit data can be understood as reading Data
  • the received data can be understood as written data
  • the transceiver control module 14 is used to control the state machine to jump in various stages according to the configuration command, and output communication signals to the flash memory through the QSPI bus.
  • the state machine in the transceiver control module 14 is controlled through the AHB bus configuration register, and the form of configuring the register can be a configuration command, in which each stage of the state machine can be configured. Therefore, the transceiver control module 14 can access the flash memory according to the assignment of each stage of the state machine in the configuration command.
  • the transceiver control module 14 includes a state machine, and the state machine can jump to various stages, and these stages can be idle stage, instruction stage, address stage, alternate byte stage, empty cycle stage and data stage.
  • the QSPI controller can communicate with the flash memory through commands. Each command includes five stages: instruction stage, address stage, alternate byte stage, dummy cycle stage and data stage. Any stage can be skipped, but at least To contain one of the instruction phase, address phase, alternate byte phase, or data phase.
  • commands (8-bit instructions) can be sent to the flash memory, allowing any value to be sent, specifying the type of operation to be performed, and can be sent in 1-wire, 2-wire or 4-wire by configuration.
  • the address phase the address is sent to the flash memory, and data is read or written from the specified address, allowing 1-4 bytes of address to be sent, which can be sent in 1-wire, 2-wire or 4-wire mode through configuration.
  • 1-4 bytes are sent to the flash memory, generally used to control the operating mode.
  • no data is sent or received for a given period of 1-31 cycles in order to give the flash memory time to prepare the data phase when higher clock frequencies are used.
  • any number of bytes can be received from or sent to flash.
  • the on-chip bus interface 11 is connected to the AHB bus, and configuration commands can be obtained, wherein AHB is an abbreviation of Advanced High Performance Bus (AHB), which is a bus interface.
  • AHB is an abbreviation of Advanced High Performance Bus (AHB), which is a bus interface.
  • the transceiver control module 14 is connected to the flash memory through the QSPI bus, and is used to control the state machine to jump in various stages according to the configuration command, and output communication signals through the QSPI bus to realize access to the flash memory.
  • Flash memory is a kind of non-volatile memory, that is, the data that has been written can still be saved even when the power is turned off. It is based on a fixed block rather than a single byte. Common flash memory includes U disk, flash memory card, etc.
  • the on-chip bus interface 11, the transmit FIFO memory 12, the receive FIFO memory 13, and the transceiver control module 14 form a soft channel through control signals, and the register can be configured through the AHB bus to access flash memory.
  • the on-chip bus interface 11 and the transceiver control module 14 can directly transmit data streams to form a hard channel and realize direct access to the flash memory. Therefore, the QSPI controller accesses the flash memory in two ways, and is compatible with all flash memory with SPI or QSPI interface, wherein the software configuration is flexible and supports dual-wire access.
  • the QSPI controller provided by the embodiment of the present application can be designed to be used in a chip. Please refer to FIG. 2, which shows a schematic diagram of the connection of the QSPI controller provided by the embodiment of the present application in a graphics processor (Graphics Processing Unit, GPU) 20.
  • a graphics processor Graphics Processing Unit, GPU
  • the GPU 20 includes a central processing unit (Central Processing Unit, CPU) 21, a bus interconnection system 22 and the QSPI controller 10, wherein the QSPI controller is connected to the bus interconnection system 22 through the AHB bus, so The bus interconnection system 22 is connected with the CPU 21 through the AXI bus, and is connected with the PCIe bus through the AXI bus.
  • the QSPI controller 10 is connected to the flash memory 23 through a QSPI bus, and outputs a communication signal through the QSPI bus to achieve access to the flash memory 23 .
  • the communication between the GPU 20 and the flash memory 23 can be realized.
  • the QSPI controller provided by the embodiment of the present application includes an on-chip bus interface, a transmit FIFO memory, a receive FIFO memory, and a transceiver control module; the on-chip bus interface is used to connect with the AHB bus to obtain configuration commands; the transmit FIFO memory is used for The receiving FIFO memory is used to store the received data; the transceiver control module is used to control the state machine to jump in each stage according to the configuration command, and output the communication signal to the flash memory through the QSPI bus.
  • a QSPI controller is designed, the state machine in the QSPI controller is controlled to jump in various stages through configuration commands, and the access to the flash memory is realized by outputting communication signals. Based on the QSPI protocol, two-wire or four-wire access can be realized, improving the speed of data transfer in flash memory access.
  • FIG. 3 is a flowchart of a flash memory access method provided by an embodiment of the present application. Please refer to FIG. 3.
  • An embodiment of the present application provides a flash memory access method, which can be applied to the QSPI controller provided by the foregoing embodiments. Specifically, the method The following steps can be included.
  • Step 110 Obtain a configuration command, where the configuration command is used to configure the state machine in the QSPI controller according to the QSPI protocol.
  • the QSPI controller can obtain a configuration command through the AHB bus, and the configuration command is used to configure the state machine in the QSPI controller according to the QSPI protocol.
  • the state machine is in the transceiver control module in the QSPI controller.
  • the state machine can be controlled through an AHB bus configuration register.
  • the configuration command may include a communication command for communicating with the flash memory, and each command includes five stages: an instruction stage, an address stage, an alternate byte stage, a dummy cycle stage, and a data stage, and any one of the five stages. It can be skipped, but at least any one of the instruction stage, the address stage, the alternate byte stage or the data stage is included, and the communication command can assign values to each stage to form the communication command.
  • the state machine includes an idle stage and five stages corresponding to the communication commands, so the state machine can be configured through a configuration command.
  • Step 120 Control the state machine to jump in various stages according to the configuration command, and output a communication signal to the flash memory.
  • the configuration command may include a communication command for communicating with the flash memory, and the communication command may configure five stages of the state machine. Therefore, the state machine can jump in various stages according to the configuration command, and output a communication signal to the flash memory to realize access to the flash memory, that is, to communicate with the flash memory. Specifically, it may be to obtain the current stage of the state machine; to obtain the assignment of each stage of the state machine in the configuration command; stage; when the state machine jumps to another stage, output a communication signal to the flash memory.
  • the state machine can be controlled to jump in each stage through the configuration command. The following will describe the jump of the state machine in each stage in detail.
  • the state machine can jump to the instruction stage, the address stage, and the data stage. If the assignment of the instruction stage is not 0, the state machine jumps to the instruction stage; if the assignment of the instruction stage is 0, the state machine jumps to the address stage; if there is only the data If the assignment of the stage is not 0, the state machine jumps to the data stage.
  • FIG. 4 a schematic diagram of jumping of the state machine in the idle phase is shown.
  • the state machine When the state machine is currently in the idle phase, it can jump from the idle phase to the instruction phase when condition 1 is satisfied, from the idle phase to the address phase when condition 2 is satisfied, and from the idle phase to the data phase when condition 3 is satisfied.
  • condition 1 is that the assignment of the instruction stage is not 0.
  • Condition 2 is the assignment of the instruction phase to 0.
  • Condition 3 is that the assignment in the data-only phase is not 0.
  • the state machine can jump to the idle stage, the address stage, the alternate byte stage, the empty cycle stage and the data stage. If the assignment of other stages is 0, the state machine jumps to the idle stage; if the assignment of the address stage is not 0, the state machine jumps to the address stage; if the assignment of the address stage is 0, The state machine jumps to the alternate byte stage; if the assignment of the address stage and the alternate byte stage is 0, the state machine jumps to the empty cycle stage; if only the data stage is assigned an assignment Not 0, the state machine jumps to the data phase.
  • FIG. 5 a schematic diagram of jumping of the state machine in the instruction stage is shown.
  • the state machine When the state machine is currently in the instruction phase, and the state enable is valid, if condition 4 is satisfied, it can jump from the instruction phase to the idle phase; if condition 5 is satisfied, it can jump from the instruction phase to the address phase; if condition 6 is satisfied, the instruction The stage jumps to the alternate byte stage; if the condition 7 is satisfied, it can jump from the instruction stage to the empty cycle stage; if the condition 8 is satisfied, it can jump from the instruction stage to the data stage.
  • condition 4 is that the assignments of other stages are all 0, that is, the assignments of the address stage, the alternate byte stage, the empty cycle stage and the data stage are all 0.
  • Condition 5 is that the assignment of the address stage is not 0.
  • Condition 6 is the assignment of the address stage to 0.
  • Condition 7 is that the address stage and the alternate byte stage are both assigned 0.
  • Condition 8 is that only the assignment of the data phase is not 0, that is, the assignment of the address phase, the alternate byte phase, and the empty cycle phase are all 0.
  • the state machine can jump to the alternate byte phase, the dummy cycle phase and the data phase. If the assignment of the alternate byte stage is not 0, the state machine jumps to the alternate byte stage; if the assignment to the alternate byte stage is 0, the state machine jumps to the empty cycle stage; if only If the assignment of the data phase is not 0, the state machine jumps to the data phase.
  • FIG. 6 a schematic diagram of jumping of the state machine in the address phase is shown.
  • the state machine When the state machine is currently in the address phase and the state enable is valid, if condition 9 is satisfied, it can jump from the address phase to the alternate byte phase; if condition 10 is satisfied, it can jump from the address phase to the empty cycle phase; if condition 11 is satisfied It is possible to jump from the address phase to the data phase.
  • condition 9 is that the assignment of the alternate byte stage is not 0.
  • condition 10 is the assignment of the alternate byte stage to 0.
  • condition 11 is that only the assignment of the data phase is not 0, that is, the assignment of the alternate byte phase and the empty cycle phase are both 0.
  • the state machine can jump to the dummy cycle stage and the data stage. If the assignment of the empty cycle stage is not 0, the state machine jumps to the empty cycle stage; if the assignment of the empty cycle stage is 0, the state machine jumps to the data stage.
  • FIG. 7 a schematic diagram of jumping of the state machine in the byte alternation stage is shown.
  • the state machine When the state machine is currently in the byte alternation stage, and the state enable is valid, if condition 12 is satisfied, it can jump from the alternate byte stage to the empty cycle stage; if condition 13 is satisfied, it can jump from the byte alternation stage to the data stage .
  • the condition 12 is that the assignment of the idle cycle phase is not 0.
  • the condition 13 is that the value of the idle cycle phase is 0.
  • the state machine If the state machine is currently in the idle cycle stage and the state enable is valid, when the data stage is not 0, the state machine jumps to the data stage. That is, when the value of the data phase is 0, the state machine can jump from the idle cycle phase to the data phase.
  • the state machine When the state machine is currently in the data phase, data transmission and reception can be performed in the data phase. Therefore, the count value of the byte reception counter can be obtained, and the count value is equal to the configuration value in the configuration command.
  • the state machine When the data is sent and received, the state machine can jump from the data phase to the idle phase.
  • the conversion is performed according to 8 bits per byte, and the count value in the data phase may also be a number of bits.
  • the access modes in the QSPI protocol can be single-wire access, dual-wire access, and four-wire access.
  • the access mode can be configured through registers.
  • single-line, dual-line, and four-line access to flash memory can be achieved. That is to say, through the configuration command, the access mode of the state machine at each stage can be obtained.
  • the access mode corresponding to the current stage of the state machine can be determined according to the configuration command; the pre-designed value corresponding to the current stage is determined according to the access mode; the current The actual count value corresponding to the current stage; when the actual count value is equal to the pre-designed value, another stage to which the state machine jumps is determined according to the assignment of each stage.
  • the access method corresponding to this stage can be obtained first, and the corresponding preset value can be determined.
  • the actual count value is equal to the preset value, according to The above condition jumps to the next stage.
  • the address stage it is determined that the access mode is dual-line access, and the two address bits of the flash memory capacity can be 24 bits and 32 bits. Assuming that the address bits are 24 bits, the preset count value corresponding to dual-line access is 12. , if it is determined that the access mode is single-line access, the preset count value corresponding to single-line access is 24.
  • the actual count value is equal to the preset value, it can jump to another stage according to the above conditions.
  • the flash memory is given time to prepare the data phase. Therefore, in the idle cycle phase, the preset count value is the configured number of cycles, and the actual count The value is the actual number of cycles. In the configuration command, the number of cycles can be pre-configured, and the configured number of cycles is the preset value. When the actual number of cycles is equal to the configured number of cycles, jump to another stage according to the above conditions.
  • the direction of the line at each stage can be controlled by a configuration command.
  • the configuration command can determine whether to read or write, and after determining whether to read or write, the direction of the line can be controlled.
  • the state machine When the state machine jumps to any stage, it can output the communication signal to the flash memory through the QSPI bus to realize the communication with the flash memory.
  • a configuration command is obtained, and the configuration command is used to configure the state machine in the QSPI controller according to the QSPI protocol; according to the configuration command, the state machine is controlled to jump in various stages , and output the communication signal to the flash memory.
  • a QSPI controller is designed, the state machine in the QSPI controller is controlled to jump in each stage through configuration commands, and the access to the flash memory is realized by outputting communication signals.
  • FIG. 8 is a functional block diagram of a flash memory access device provided by an embodiment of the present application.
  • an embodiment of the present application provides a flash memory access device 200 .
  • the flash memory access device 200 includes an acquisition module 210 and an access module 220 .
  • the obtaining module 210 is used to obtain a configuration command, and the configuration command is used to configure the state machine in the QSPI controller according to the QSPI protocol; the access module 220 is used to control the state according to the configuration command The machine jumps in various stages and outputs communication signals to the flash memory.
  • the state machine includes an idle stage, an instruction stage, an address stage, an alternate byte stage, an empty cycle stage and a data stage
  • the access module 220 is further configured to obtain the stage that the state machine is currently in; obtain the The assignment of each stage of the state machine in the configuration command; according to the assignment of each stage, another stage to which the state machine jumps is determined.
  • the access module 220 is further configured to jump to the instruction stage if the assignment of the instruction stage is not 0; if the instruction If the assignment of the stage is 0, the state machine jumps to the address stage; if only the assignment of the data stage is not 0, the state machine jumps to the data stage.
  • the access module 220 is also used to jump to the idle stage if the assignments in other stages are all 0; If the assignment of the address stage is not 0, the state machine jumps to the address stage; if the assignment of the address stage is 0, the state machine jumps to the alternate byte stage; if the The assignment of the address stage and the alternate byte stage is 0, and the state machine jumps to the empty cycle stage; if only the assignment of the data stage is not 0, the state machine jumps to the data stage.
  • the access module 220 is further configured to jump to the state machine if the assignment of the alternate byte stage is not 0.
  • the alternate byte stage if the assignment of the alternate byte stage is 0, the state machine jumps to the empty cycle stage; if only the assignment of the data stage is not 0, the state machine jumps to the data stage.
  • the access module 220 is further configured to jump to the state machine if the assignment of the empty cycle stage is not 0. the idle cycle stage; if the value of the idle cycle stage is 0, the state machine jumps to the data stage.
  • the access module 220 is further configured to jump to the state machine if the assignment of the data stage is not 0. data stage.
  • the access module 220 is further configured to obtain the count value of the byte receiving counter; if the count value is equal to the configuration value in the configuration command, the state The machine jumps to the idle phase.
  • the access module 220 is further configured to determine, according to a configuration command, an access mode corresponding to the stage that the state machine is currently in,
  • the access mode includes single-line, double-line, and four-line; determine the pre-designed value corresponding to the current stage according to the access mode; obtain the actual count value corresponding to the current stage; when the actual count value is equal to the When pre-designing the value, another stage to which the state machine jumps is determined according to the assignment of each stage.
  • the flash memory access device acquires a configuration command, where the configuration command is used to configure the state machine in the QSPI controller according to the QSPI protocol; according to the configuration command, the state machine is controlled to jump in various stages , and output the communication signal to the flash memory.
  • a QSPI controller is designed, the state machine in the QSPI controller is controlled to jump in various stages through configuration commands, and the access to the flash memory is realized by outputting communication signals. Based on the QSPI protocol, two-wire or four-wire access can be realized, improving the speed of data transfer in flash memory access.
  • FIG. 9 is a structural block diagram of an electronic device for executing the flash memory access method according to the embodiment of the present application proposed by the embodiment of the present application.
  • an embodiment of the present application provides a structural block diagram of an electronic device.
  • the electronic device 300 includes a processor 310, a memory 320 and one or more application programs, wherein the one or more application programs are stored in In the memory 320 and configured to be executed by the one or more processors 310, the one or more programs are configured to perform the above-described method of flash memory access.
  • the electronic device 300 may be a terminal device capable of running an application program, such as a smart phone, a tablet computer, an electronic book, or the like, and may also be a server.
  • the electronic device 300 in the present application may include one or more of the following components: a processor 310, a memory 320, and one or more application programs, wherein the one or more application programs may be stored in the memory 320 and configured to be executed by One or more processors 310 execute, and one or more programs are configured to execute the methods described in the foregoing method embodiments.
  • Processor 310 may include one or more processing cores.
  • the processor 310 uses various interfaces and lines to connect various parts of the entire electronic device 300, and executes by running or executing the instructions, programs, code sets or instruction sets stored in the memory 320, and calling the data stored in the memory 320.
  • the processor 310 may adopt at least one of a digital signal processing (Digital Signal Processing, DSP), a Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA), and a Programmable Logic Array (Programmable Logic Array, PLA).
  • DSP Digital Signal Processing
  • FPGA Field-Programmable Gate Array
  • PLA Programmable Logic Array
  • the processor 310 may integrate one or a combination of a central processing unit (Central Processing Unit, CPU), a graphics processing unit (Graphics Processing Unit, GPU), a modem, and the like.
  • CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • the CPU mainly handles the operating system, user interface and application programs, etc.
  • the GPU is used for rendering and drawing of the display content
  • the modem is used to handle wireless communication. It can be understood that, the above-mentioned modem may not be integrated into the processor 310, and is implemented by a communication chip alone.
  • the memory 320 may include random access memory (Random Access Memory, RAM), or may include read-only memory (Read-Only Memory). Memory 320 may be used to store instructions, programs, codes, sets of codes, or sets of instructions.
  • the memory 320 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playback function, an image playback function, etc.) , instructions for implementing the following method embodiments, and the like.
  • the storage data area may also store data (such as phone book, audio and video data, chat record data) created by the electronic device 300 during use.
  • the electronic device provided in the embodiment of the present application acquires a configuration command, where the configuration command is used to configure the state machine in the QSPI controller according to the QSPI protocol; according to the configuration command, the state machine is controlled to jump in various stages, And output the communication signal to the flash memory.
  • a QSPI controller is designed, the state machine in the QSPI controller is controlled to jump in various stages through configuration commands, and the access to the flash memory is realized by outputting communication signals. Based on the QSPI protocol, two-wire or four-wire access can be realized, improving the speed of data transfer in flash memory access.
  • the embodiments of the present application may be provided as a method, a system, or a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including, but not limited to, disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions
  • the apparatus implements the functions specified in the flow or flow of the flowcharts and/or the block or blocks of the block diagrams.

Abstract

一种在图像处理器中的QSPI控制器（10）及闪存访问方法，其中，QSPI控制器（10）包括片上总线接口（11），发送先进先出存储器（12），接收先进先出存储器（13），以及收发控制模块（14）；所述片上总线接口（11）用于和AHB总线连接，获取配置命令；所述发送先进先出储存器（12）用于存储发送数据；所述接收先进先出存储器（13）用于存储接收数据；所述收发控制模块（14），用于根据所述配置命令控制状态机在各个阶段跳转，并通过QSPI总线输出通信信号到闪存。设计了一种QSPI控制器（10），通过配置命令控制该QSPI控制器（10）中的状态机在各个阶段跳转，并输出通信信号实现了对闪存的访问，基于QSPI协议可以实现双线或四线访问，提升了闪存访问中数据传输速度。

Description

QSPI控制器，图像处理器及闪存访问方法 技术领域
本申请涉及计算机技术领域，具体地，涉及一种QSPI控制器，图像处理器及闪存访问方法。
背景技术
在计算机技术中，通常需要和闪存进行通信。而在对闪存访问中，通常采用串行外设接口(Serial Peripheral Interface，SPI)与闪存进行通信。然而，由于SPI是单线，在通过SPI进行闪存访问时，数据的传输速度较慢。
发明内容
本申请实施例中提供一种QSPI控制器及闪存访问方法，解决了在闪存访问中，数据传输速度不高的问题。
根据本申请实施例的第一个方面，提供了一种QSPI控制器，该QSPI控制器包括：片上总线接口，发送先进先出存储器，接收先进先出存储器，以及收发控制模块；所述片上总线接口用于和AHB总线连接，获取配置命令；所述发送先进先出储存器用于存储发送数据；所述接收先进先出存储器用于存储接收数据；所述收发控制模块，用于根据所述配置命令控制状态机在各个阶段跳转，并通过QSPI总线输出通信信号到闪存。
根据本申请实施例的第二个方面，提供了一种图像处理器，包括第一个方面提供的QSPI控制器，总线互联系统，以及中央处理器；所述总线互联系统通过AXI总线分别与所述中央处理连接，以及PCIe总线连接；所述总线互联系统通过AHB总线与所述QSPI控制器连接；所述QSPI控制器通过QSPI总线与闪存连接。
根据本申请实施例的第三个方面，提供了一种闪存访问方法，该方法包括： 获取配置命令，所述配置命令用于根据QSPI协议配置所述QSPI控制器中的状态机；根据所述配置命令，控制所述状态机在各个阶段跳转，并输出通信信号到所述闪存。
根据本申请实施例的第四个方面，提供了一种闪存访问装置，该装置包括：获取模块，用于获取配置命令，所述配置命令用于根据QSPI协议配置所述QSPI控制器中的状态机；访问模块，用于根据所述配置命令，控制所述状态机在各个阶段跳转，并输出通信信号到所述闪存。
根据本申请实施例的第五个方面，提供了一种电子设备，该电子设备包括一个或多个处理器；存储器；一个或多个应用程序，其中所述一个或多个应用程序被存储在所述存储器中并被配置为由所述一个或多个处理器执行，所述一个或多个程序配置用于执行如上述应用于电子设备的方法。
根据本申请实施例的第六个方面，本申请实施列提供一种计算机可读存储介质，所述计算机可读存储介质中存储有程序代码，其中，在所述程序代码运行时执行上述的方法。
采用本申请实施例中提供的QSPI控制器，图像处理器及闪存访问方法，获取配置命令，所述的配置命令用于根据QSPI协议配置所述QSPI控制器中的状态机；根据所述配置命令，控制所述状态机在各个阶段跳转，并输出通信信号到所述闪存。设计了一种QSPI控制器，通过配置命令控制该QSPI控制器中的状态机在各个阶段跳转，并输出通信信号实现了对闪存的访问，基于QSPI协议可以实现双线或四线访问，提升了闪存访问中数据传输速度。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1为本申请实施例提供的QSPI控制器的结构图；
图2为本申请一个实施例提供的QSPI控制器在图像处理器中的连接示意 图；
图3为本申请一个实施例提供的闪存访问方法的流程图；
图4为本申请一个实施例提供的状态机在空闲阶段的跳转示意图；
图5为本申请一个实施例提供的状态机在指令阶段的跳转示意图；
图6为本申请一个实施例提供的状态机在地址阶段的跳转示意图；
图7为本申请一个实施例提供的状态机在字节交替阶段的跳转示意图；
图8为本申请一个实施例提供的闪存访问装置的功能模块图；
图9为本申请实施例提出的用于执行根据本申请实施例的闪存访问方法的电子设备的结构框图。
具体实施方式
为了使本申请实施例中的技术方案及优点更加清楚明白，以下结合附图对本申请的示例性实施例进行进一步详细的说明，显然，所描述的实施例仅是本申请的一部分实施例，而不是所有实施例的穷举。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
在计算机技术中，通常需要和闪存进行通信。而在对闪存访问中，通常采用串行外设接口(Serial Peripheral Interface，SPI)与闪存进行通信。然而，由于SPI是单线，在通过SPI进行闪存访问时，数据的传输速度较慢。
发明人在研究中发现，QSPI是SPI接口的扩展，比SPI应用更加广泛，在SPI协议的基础上，QSPI的功能进行了增强，增加了队列传输机制，推出了队列串行外设接口协议。使用QSPI接口，用户传输数据的速度是SPI接口的4倍。而且QSPI一旦启动传输，直到传输结束，传输过程都不需要CPU干预，极大的提高了传输效率。
针对上述问题，本申请实施例中提供了一种QSPI控制器以及闪存访问方法，所述QSPI控制器包括片上总线接口，发送先进先出存储器，接收先进先出存储器，以及收发控制模块；所述片上总线接口用于和AHB总线连接，获取配置命令；所述发送先进先出储存器用于存储发送数据；所述接收先进先出 存储器用于存储接收数据；所述收发控制模块，用于根据所述配置命令控制状态机在各个阶段跳转，并通过QSPI总线输出通信信号到闪存。设计了一种QSPI控制器，通过配置命令控制该QSPI控制器中的状态机在各个阶段跳转，并输出通信信号实现了对闪存的访问，基于QSPI协议可以实现双线或四线访问，提升了闪存访问中数据传输速度。
本申请实施例中的方案可以采用计算机硬件描述语言实现，例如，Verilog语言。
为了使本申请实施例中的技术方案及优点更加清楚明白，以下结合附图对本申请的示例性实施例进行进一步详细的说明，显然，所描述的实施例仅是本申请的一部分实施例，而不是所有实施例的穷举。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
请参阅图1，示出了本申请一个实施例提供的QSPI控制器的结构框图。
所述QSPI控制器10包括片上总线接口11，发送先进先出(First Input First Output，FIFO)存储器12，接收先进先出(First Input First Output，FIFO)存储器13，以及收发控制模块14。所述片上总线接口11用于与AHB总线连接，获取配置命令，所述发送FIFO存储器12用于存储发送数据，所述接收FIFO存储器13用于存储接收数据，所述发送数据可以理解为读取数据，所述接收数据可以理解为写入数据，所述收发控制模块14，用于根据所述配置命令控制状态机在各个阶段跳转，并通过QSPI总线输出通信信号到闪存。也就是说，根据QSPI协议，通过AHB总线配置寄存器来控制所述收发控制模块14中的状态机，配置所述寄存器的形式可以是配置命令，在所述配置命令中可以对状态机的各个阶段赋值，因此，所述收发控制模块14可以根据配置命令中状态机的各个阶段的赋值访问闪存。
其中，所述收发控制模块14中包括状态机，所述状态机可以跳转到各个阶段，这些阶段可以是空闲阶段，指令阶段，地址阶段，交替字节阶段，空周期阶段以及数据阶段。通常，所述QSPI控制器可以通过命令与闪存通信，每 条命令包括指令阶段、地址阶段、交替字节阶段、空周期阶段和数据阶段这五个阶段，任一阶段均可跳过，但至少要包含指令阶段、地址阶段、交替字节阶段或数据阶段之一。
在指令阶段，可以将命令(8位指令)发送到闪存，允许发送任何值，指定待执行操作的类型，通过配置可以以1线，2线或者4线方式发送。在地址阶段，将地址发送到闪存，从指定的地址读取或者写入数据，允许发送1-4个字节的地址，通过配置可以以1线，2线或者4线方式发送。在字节交替阶段，将1-4字节发送到闪存，一般用于控制操作模式。在空周期阶段，给定的1-31个周期内不发送或接收任何数据，目的是当采用更高的时钟频率时，给闪存留出准备数据阶段的时间。在数据阶段，可从闪存接收或向其发送任意数量的字节。
其中，所述片上总线接口11与AHB总线连接，可以获取到配置命令，其中，AHB为高级高性能总线(Advanced High Performance Bus，AHB)的缩写，是一种总线接口。所述收发控制模块14通过QSPI总线与闪存连接，用于根据所述配置命令控制状态机在各个阶段跳转，并通过QSPI总线输出通信信号以实现对闪存的访问。
闪存是一种非易失性存储器，即断电的情况下依旧可以保存已经写入的数据，是以固定的区块为单位，而不是以单个的字节为单位。常见的闪存有U盘，闪存卡等。
在所述的QSPI控制器中，所述片上总线接口11，所述发送FIFO存储器12，所述接收FIFO存储器13，以及所述收发控制模块14通过控制信号形成软通道，可以通过AHB总线配置寄存器来访问闪存。而所述片上总线接口11和所述收发控制模块14之间可以直接传输数据流，形成硬通道，实现对闪存的直接访问。因此，所述QSPI控制器通过两种方式对闪存进行访问，可以兼容所有带SPI或QSPI接口的闪存，其中，软件配置的方式灵活且支持双线访问。
本申请实施例提供的QSPI控制器可以设计在芯片中使用，请参阅图2，示出了本申请实施例提供的QSPI控制器在图像处理器(Graphics Processing Unit，GPU)20中的连接示意图。
所述GPU 20中包括中央处理器(Central Processing Unit，CPU)21，总线互联系统22以及所述QSPI控制器10，其中，所述QSPI控制器通过AHB总线与所述总线互联系统22连接，所述总线互联系统22通过AXI总线与所述CPU 21连接，并通过AXI总线与PCIe总线连接。所述QSPI控制器10通过QSPI总线与闪存23连接，通过所述QSPI总线输出通信信号实现对所述闪存23的访问。从而，可以实现GPU 20与所述闪存23的通信。
本申请实施例提供的QSPI控制器，包括片上总线接口，发送FIFO存储器，接收FIFO存储器，以及收发控制模块；所述片上总线接口用于和AHB总线连接，获取配置命令；所述发送FIFO储存器用于存储发送数据；所述接收FIFO存储器用于存储接收数据；所述收发控制模块，用于根据所述配置命令控制状态机在各个阶段跳转，并通过QSPI总线输出通信信号到闪存。设计了一种QSPI控制器，通过配置命令控制该QSPI控制器中的状态机在各个阶段跳转，并输出通信信号实现了对闪存的访问，基于QSPI协议可以实现双线或四线访问，提升了闪存访问中数据传输速度。
图3为本申请一个实施例提供的闪存访问方法的流程图，请参阅图3，本申请实施例提供了一种闪存访问方法，可应用于前述实施例提供的QSPI控制器，具体的该方法可以包括以下步骤。
步骤110，获取配置命令，所述配置命令用于根据QSPI协议配置所述QSPI控制器中的状态机。
所述QSPI控制器可以通过AHB总线获取到配置命令，所述配置命令用于根据QSPI协议配置所述QSPI控制器中的状态机。其中，所述状态机在所述QSPI控制器中的所述收发控制模块中。根据所述QSPI协议，可以通过AHB总线配置寄存器来控制所述状态机。所述配置命令可以包括与所述闪存进行通 信的通信命令，每条命令包括指令阶段、地址阶段、交替字节阶段、空周期阶段和数据阶段共五个阶段，而这五个阶段任一阶段均可跳过，但至少要包含指令阶段、地址阶段、交替字节阶段或数据阶段中的任意一个，所述通信命令可以对各个阶段进行赋值以形成所述通信命令。
所述状态机包括空闲阶段，以及与所述通信命令中对应的五个阶段，因此，通过配置命令可以对所述状态机进行配置。
步骤120，根据所述配置命令，控制所述状态机在各个阶段跳转，并输出通信信号到所述闪存。
在所述配置命令中可以包括与所述闪存进行通信的通信命令，所述通信命令可以对状态机的五个阶段进行配置。从而所述状态机可以根据配置命令，在各个阶段跳转，并输出通信信号到闪存以实现对闪存的访问，即与闪存之间进行通信。具体的，可以是获取所述状态机当前处于的阶段；获取所述配置命令中对所述状态机的各个阶段的赋值；根据所述各个阶段的赋值，确定所述状态机跳转的另一阶段；在所述状态机跳转到另一阶段时，输出通信信号到所述闪存。
由于所述状态机有多个阶段，通过配置命令可以控制状态机在各个阶段中跳转，下面将对状态机在各个阶段的跳转进行详细说明。
若所述状态机当前处于所述空闲阶段，所述状态机可以跳转到指令阶段，地址阶段，以及数据阶段。若所述指令阶段的赋值不为0，所述状态机跳转到所述指令阶段；若所述指令阶段的赋值为0，所述状态机跳转到所述地址阶段；若只有所述数据阶段的赋值不为0，所述状态机跳转到所述数据阶段。
请参阅图4，示出了状态机在空闲阶段的跳转示意图。在所述状态机当前处于空闲阶段时，满足条件1可以从空闲阶段跳转到指令阶段，满足条件2可以从空闲阶段跳转到地址阶段，满足条件3可以从空闲阶段跳转到数据阶段。
其中，所述条件1为所述指令阶段的赋值不为0。条件2为所述指令阶段的赋值为0。条件3为只有数据阶段的赋值不为0。
若所述状态机当前处于所述指令阶段，且状态使能有效，所述状态机可以跳转到空闲阶段，地址阶段，交替字节阶段，空周期阶段以及数据阶段。若其他阶段的赋值均为0，所述状态机跳转到所述空闲阶段；若地址阶段的赋值不为0，所述状态机跳转到所述地址阶段；若地址阶段的赋值为0，所述状态机跳转到所述交替字节阶段；若所述地址阶段以及交替字节阶段的赋值为0，所述状态机跳转到所述空周期阶段；若只有所述数据阶段的赋值不为0，所述状态机跳转到所述数据阶段。
本领域技术人员可以理解的是，状态机在各个阶段跳转时，状态使能有效，才能在各个阶段中跳转。
请参阅图5，示出了状态机在指令阶段的跳转示意图。在所述状态机当前处于指令阶段时，且状态使能有效，满足条件4，可以从指令阶段跳转到空闲阶段；满足条件5可以从指令阶段跳转到地址阶段；满足条件6可以从指令阶段跳转到交替字节阶段；满足条件7可以从指令阶段跳转到空周期阶段；满足条件8可以从指令阶段跳转到数据阶段。
其中，条件4为其他阶段的赋值均为0，即地址阶段，交替字节阶段，空周期阶段以及数据阶段的赋值均为0。条件5为所述地址阶段的赋值不为0。条件6为所述地址阶段的赋值为0。条件7为所述地址阶段以及交替字节阶段的赋值均为0。条件8为只有数据阶段的赋值不为0，即地址阶段，交替字节阶段，空周期阶段的赋值均为0。
若所述状态机当前处于所述地址阶段，且状态使能有效，所述状态机可以跳转到交替字节阶段，空周期阶段以及数据阶段。若交替字节阶段的赋值不为0，所述状态机跳转到所述交替字节阶段；若交替字节阶段的赋值为0，所述状态机跳转到所述空周期阶段；若只有所述数据阶段的赋值不为0，所述状态机跳转到所述数据阶段。
请参阅图6，示出了状态机在地址阶段的跳转示意图。在所述状态机当前处于地址阶段时，且状态使能有效，满足条件9，可以从地址阶段跳转到交替 字节阶段；满足条件10可以从地址阶段跳转到空周期阶段；满足条件11可以从地址阶段跳转到数据阶段。
其中，所述条件9为交替字节阶段的赋值不为0。所述条件10为所述交替字节阶段的赋值为0。所述条件11为只有所述数据阶段的赋值不为0，即所述交替字节阶段以及所述空周期阶段的赋值均为0。
若所述状态机当前处于所述交替字节阶段，且状态使能有效，所述状态机可以跳转到空周期阶段以及数据阶段。若空周期阶段的赋值不为0，所述状态机跳转到所述空周期阶段；若空周期阶段的赋值为0，所述状态机跳转到所述数据阶段。
请参阅图7，示出了状态机在字节交替阶段的跳转示意图。在所述状态机当前处于字节交替阶段时，且状态使能有效，满足条件12，可以从交替字节阶段跳转到空周期阶段；满足条件13可以从字节交替阶段跳转到数据阶段。其中，所述条件12为所述空周期阶段的赋值不为0。所述条件13为所述空周期阶段的赋值为0。
若所述状态机当前处于所述空周期阶段，且状态使能有效，在数据阶段不为0时，所述状态机跳转到数据阶段。也就是说，在所述数据阶段的赋值为0时，状态机可以从空周期阶段跳转到数据阶段。
在所述状态机当前处于所述数据阶段时，在所述数据阶段可以进行数据的收发，因此，可以获取字节接收计数器的计数值，在所述计数值等于所述配置命令中的配置值时，表明数据收发完毕，所述状态机可以从数据阶段跳转到空闲阶段。当然，根据1个字节8位进行换算，在数据阶段的所述计数值也可以是位数。
可以理解的是，QSPI协议中的访问方式可以是单线访问，双线访问，以及四线访问，在状态机的指令阶段，地址阶段，交替字节阶段和数据阶段都可以通过寄存器配置访问方式。从而可以实现单线，双线，四线方式访问闪存。也就是说，通过配置命令，可以获取到状态机在各个阶段的访问方式。
在一些实施方式中，在所述状态机跳转到某一阶段前，需要完成该阶段的数据任务。在所述状态机跳转到某一阶段前，可以根据配置命令，确定所述状态机当前处于的阶段对应的访问方式；根据所述访问方式确定当前处于的阶段对应的预设计数值；获取当前处于的阶段对应的实际计数值；在所述实际计数值等于预设计数值时，根据所述各个阶段的赋值，确定所述状态机跳转的另一阶段。
在指令阶段，地址阶段，字节交替阶段中存在数据发送到闪存，因此，可以是先获取该阶段对应的访问方式，确定对应的预设计数值，在实际的计数值等于预设计数值时，按照上述条件跳转到下一阶段。例如，在地址阶段，确定访问方式为双线访问，闪存容量的两种地址位数可以是24位和32位，假设地址位数为24位，那么对应双线访问下的预设计数值为12，若确定访问方式为单线访问，对应单线访问下的预设计数值为24，在实际计数值等于预设计数值时，按照上述条件可跳转到另一阶段。
在空周期阶段中，给定1-31个周期内不发送或接收任何数据，给闪存留出准备数据阶段的时间，因此，在空周期阶段所述预设计数值为配置的周期数，实际计数值为实际的周期数。在配置命令中，可以预先配置周期数，配置的周期数即为预设计数值，在实际的周期数与配置的周期数相等时，按照上述条件跳转到另一阶段。
在一些实施方式中，可以通过配置命令控制在每个阶段的线的方向，在不同的阶段，通过配置命令可以确定是读还是写，在确定是读还是写后，可以控制线的方向。
状态机在跳转到任一阶段时，可以通过QSPI总线输出通信信号到闪存，实现与闪存的通信。
本申请实施例提供的闪存访问方法，获取配置命令，所述配置命令用于根据QSPI协议配置所述QSPI控制器中的状态机；根据所述配置命令，控制所述状态机在各个阶段跳转，并输出通信信号到所述闪存。设计了一种QSPI控 制器，通过配置命令控制该QSPI控制器中的状态机在各个阶段跳转，并输出通信信号实现了对闪存的访问。
图8为本申请一个实施例提供的闪存访问装置的功能模块图。请参阅图8，本申请实施例提供了一种闪存访问装置200，所述闪存访问装置200包括获取模块210，以及访问模块220。所述获取模块210，用于获取配置命令，所述配置命令用于根据QSPI协议配置所述QSPI控制器中的状态机；所述访问模块220，用于根据所述配置命令，控制所述状态机在各个阶段跳转，并输出通信信号到所述闪存。
进一步的，所述状态机包括空闲阶段，指令阶段，地址阶段，交替字节阶段，空周期阶段以及数据阶段，所述访问模块220还用于获取所述状态机当前处于的阶段；获取所述配置命令中对所述状态机的各个阶段的赋值；根据所述各个阶段的赋值，确定所述状态机跳转的另一阶段。
进一步的，若所述状态机当前处于所述空闲阶段，所述访问模块220还用于若所述指令阶段的赋值不为0，所述状态机跳转到所述指令阶段；若所述指令阶段的赋值为0，所述状态机跳转到所述地址阶段；若只有所述数据阶段的赋值不为0，所述状态机跳转到所述数据阶段。
进一步的，若所述状态机当前处于所述指令阶段，且状态使能有效，所述访问模块220还用于若其他阶段的赋值均为0，所述状态机跳转到所述空闲阶段；若所述地址阶段的赋值不为0，所述状态机跳转到所述地址阶段；若所述地址阶段的赋值为0，所述状态机跳转到所述交替字节阶段；若所述地址阶段以及交替字节阶段的赋值为0，所述状态机跳转到所述空周期阶段；若只有所述数据阶段的赋值不为0，所述状态机跳转到所述数据阶段。
进一步的，若所述状态机当前处于所述地址阶段，且状态使能有效，所述访问模块220还用于若所述交替字节阶段的赋值不为0，所述状态机跳转到所述交替字节阶段；若所述交替字节阶段的赋值为0，所述状态机跳转到所述空周期阶段；若只有所述数据阶段的赋值不为0，所述状态机跳转到所述数据阶 段。
进一步的，若所述状态机当前处于所述交替字节阶段，且状态使能有效，所述访问模块220还用于若所述空周期阶段的赋值不为0，所述状态机跳转到所述空周期阶段；若所述空周期阶段的赋值为0，所述状态机跳转到所述数据阶段。
进一步的，若所述状态机当前处于所述空周期阶段，且状态使能有效，所述访问模块220还用于若所述数据阶段的赋值不为0，所述状态机跳转到所述数据阶段。
进一步的，若所述状态机当前处于所述数据阶段，所述访问模块220还用于获取字节接收计数器的计数值；若所述计数值等于所述配置命令中的配置值，所述状态机跳转到所述空闲阶段。
进一步的，根据所述各个阶段的赋值，确定所述状态机跳转的另一阶段之前，所述访问模块220还用于根据配置命令，确定所述状态机当前处于的阶段对应的访问方式，所述访问方式包括单线，双线，以及四线；根据所述访问方式确定当前处于的阶段对应的预设计数值；获取当前处于的阶段对应的实际计数值；在所述实际计数值等于所述预设计数值时，根据所述各个阶段的赋值，确定所述状态机跳转的另一阶段。
本申请实施例提供的闪存访问装置，获取配置命令，所述配置命令用于根据QSPI协议配置所述QSPI控制器中的状态机；根据所述配置命令，控制所述状态机在各个阶段跳转，并输出通信信号到所述闪存。设计了一种QSPI控制器，通过配置命令控制该QSPI控制器中的状态机在各个阶段跳转，并输出通信信号实现了对闪存的访问，基于QSPI协议可以实现双线或四线访问，提升了闪存访问中数据传输速度。
要说明的是，所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
图9为本申请实施例提出的用于执行根据本申请实施例的闪存访问方法的电子设备的结构框图。请参阅图9，本申请实施例提供了一种电子设备的结构框图，该电子设备300包括处理器310以及存储器320以及一个或多个应用程序，其中所述一个或多个应用程序被存储在所述存储器320中并被配置为由所述一个或多个处理器310执行，所述一个或多个程序配置用于执行上述闪存访问的方法。
该电子设备300可以是智能手机、平板电脑、电子书等能够运行应用程序的终端设备，还可以是服务器。本申请中的电子设备300可以包括一个或多个如下部件：处理器310、存储器320、以及一个或多个应用程序，其中一个或多个应用程序可以被存储在存储器320中并被配置为由一个或多个处理器310执行，一个或多个程序配置用于执行如前述方法实施例所描述的方法。
处理器310可以包括一个或者多个处理核。处理器310利用各种接口和线路连接整个电子设备300内的各个部分，通过运行或执行存储在存储器320内的指令、程序、代码集或指令集，以及调用存储在存储器320内的数据，执行电子设备300的各种功能和处理数据。可选地，处理器310可以采用数字信号处理(Digital Signal Processing，DSP)、现场可编程门阵列(Field－Programmable Gate Array，FPGA)、可编程逻辑阵列(Programmable Logic Array，PLA)中的至少一种硬件形式来实现。处理器310可集成中央处理器(Central Processing Unit，CPU)、图像处理器(Graphics Processing Unit，GPU)和调制解调器等中的一种或几种的组合。其中，CPU主要处理操作系统、用户界面和应用程序等；GPU用于负责显示内容的渲染和绘制；调制解调器用于处理无线通信。可以理解的是，上述调制解调器也可以不集成到处理器310中，单独通过一块通信芯片进行实现。
存储器320可以包括随机存储器(Random Access Memory，RAM)，也可以包括只读存储器(Read-Only Memory)。存储器320可用于存储指令、程序、代码、代码集或指令集。存储器320可包括存储程序区和存储数据区，其中， 存储程序区可存储用于实现操作系统的指令、用于实现至少一个功能的指令(比如触控功能、声音播放功能、图像播放功能等)、用于实现下述各个方法实施例的指令等。存储数据区还可以存储电子设备300在使用中所创建的数据(比如电话本、音视频数据、聊天记录数据)等。
本申请实施例提供的电子设备，获取配置命令，所述配置命令用于根据QSPI协议配置所述QSPI控制器中的状态机；根据所述配置命令，控制所述状态机在各个阶段跳转，并输出通信信号到所述闪存。设计了一种QSPI控制器，通过配置命令控制该QSPI控制器中的状态机在各个阶段跳转，并输出通信信号实现了对闪存的访问，基于QSPI协议可以实现双线或四线访问，提升了闪存访问中数据传输速度。
本领域内的技术人员应明白，本申请的实施例可提供为方法、系统、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (16)

  1. 一种QSPI控制器，所述QSPI控制器包括片上总线接口，发送先进先出存储器，接收先进先出存储器，以及收发控制模块；
    所述片上总线接口用于和AHB总线连接，获取配置命令；
    所述发送先进先出储存器用于存储发送数据；
    所述接收先进先出存储器用于存储接收数据；
    所述收发控制模块，用于根据所述配置命令控制状态机在各个阶段跳转，并通过QSPI总线输出通信信号到闪存。
  2. 根据权利要求1所述的QSPI控制器，所述收发控制模块通过QSPI总线与闪存连接。
  3. 根据权利要求1所述的QSPI控制器，其特征在于，所述收发控制模块包括状态机，所述状态机的各个阶段包括空闲阶段，指令阶段，地址阶段，交替字节阶段，空周期阶段以及数据阶段。
  4. 一种图像处理器，所述图像处理器包括权利要求1-3任一项所述的QSPI控制器，总线互联系统，以及中央处理器；
    所述总线互联系统通过AXI总线分别与所述中央处理连接，以及PCIe总线连接；
    所述总线互联系统通过AHB总线与所述QSPI控制器连接；
    所述QSPI控制器通过QSPI总线与闪存连接。
  5. 一种闪存访问方法，其特征在于，应用于权利要求1-3任一项所述的QSPI控制器，所述方法包括：
    获取配置命令，所述配置命令用于根据QSPI协议配置所述QSPI控制器中的状态机；
    根据所述配置命令，控制所述状态机在各个阶段跳转，并输出通信信号到所述闪存。
  6. 根据权利要求5所述的方法，其特征在于，所述状态机包括空闲阶段， 指令阶段，地址阶段，交替字节阶段，空周期阶段以及数据阶段，所述根据所述配置命令，控制所述状态机在各个阶段跳转，并输出通信信号到所述闪存，包括：
    获取所述状态机当前处于的阶段；
    获取所述配置命令中对所述状态机的各个阶段的赋值；
    根据所述各个阶段的赋值，确定所述状态机跳转的另一阶段；
    在所述状态机跳转到另一阶段时，输出通信信号到所述闪存。
  7. 根据权利要求6所述的方法，其特征在于，若所述状态机当前处于所述空闲阶段，所述根据所述各个阶段的赋值，确定所述状态机跳转的另一阶段，包括：
    若所述指令阶段的赋值不为0，所述状态机跳转到所述指令阶段；
    若所述指令阶段的赋值为0，所述状态机跳转到所述地址阶段；
    若只有所述数据阶段的赋值不为0，所述状态机跳转到所述数据阶段。
  8. 根据权利要求6所述的方法，其特征在于，若所述状态机当前处于所述指令阶段，且状态使能有效，所述根据所述各个阶段的赋值，确定所述状态机跳转的另一阶段，包括：
    若其他阶段的赋值均为0，所述状态机跳转到所述空闲阶段；
    若所述地址阶段的赋值不为0，所述状态机跳转到所述地址阶段；
    若所述地址阶段的赋值为0，所述状态机跳转到所述交替字节阶段；
    若所述地址阶段以及交替字节阶段的赋值为0，所述状态机跳转到所述空周期阶段；
    若只有所述数据阶段的赋值不为0，所述状态机跳转到所述数据阶段。
  9. 根据权利要求6所述的方法，其特征在于，若所述状态机当前处于所述地址阶段，且状态使能有效，所述根据所述各个阶段的赋值，确定所述状态机跳转的另一阶段，包括：
    若所述交替字节阶段的赋值不为0，所述状态机跳转到所述交替字节阶段；
    若所述交替字节阶段的赋值为0，所述状态机跳转到所述空周期阶段；
    若只有所述数据阶段的赋值不为0，所述状态机跳转到所述数据阶段。
  10. 根据权利要求6所述的方法，其特征在于，若所述状态机当前处于所述交替字节阶段，且状态使能有效，所述根据所述各个阶段的赋值，确定所述状态机跳转的另一阶段，包括：
    若所述空周期阶段的赋值不为0，所述状态机跳转到所述空周期阶段；
    若所述空周期阶段的赋值为0，所述状态机跳转到所述数据阶段。
  11. 根据权利要求6所述的方法，其特征在于，若所述状态机当前处于所述空周期阶段，且状态使能有效，所述根据所述各个阶段的赋值，确定所述状态机跳转的另一阶段，包括：
    若所述数据阶段的赋值不为0，所述状态机跳转到所述数据阶段。
  12. 根据权利要求6所述的方法，其特征在于，若所述状态机当前处于所述数据阶段，所述根据所述各个阶段的赋值，确定所述状态机跳转的另一阶段，包括：
    获取字节接收计数器的计数值；
    若所述计数值等于所述配置命令中的配置值，所述状态机跳转到所述空闲阶段。
  13. 根据权利要求6-12任一项所述的方法，其特征在于，所述根据所述各个阶段的赋值，确定所述状态机跳转的另一阶段之前，还包括：
    根据配置命令，确定所述状态机当前处于的阶段对应的访问方式，所述访问方式包括单线，双线，以及四线；
    根据所述访问方式确定当前处于的阶段对应的预设计数值；
    获取当前处于的阶段对应的实际计数值；
    在所述实际计数值等于所述预设计数值时，根据所述各个阶段的赋值，确定所述状态机跳转的另一阶段。
  14. 一种闪存访问装置，其特征在于，应用于权利要求1-3任一项所述的 QSPI控制器，所述装置包括：
    获取模块，用于获取配置命令，所述配置命令用于根据QSPI协议配置所述QSPI控制器中的状态机；
    访问模块，用于根据所述配置命令，控制所述状态机在各个阶段跳转，并输出通信信号到所述闪存。
  15. 一种电子设备，其特征在于，所述电子设备包括：
    一个或多个处理器；
    存储器，与所述一个或多个处理器电连接；
    一个或多个应用程序，其中所述一个或多个应用程序被存储在所述存储器中并被配置为由所述一个或多个处理器执行，所述一个或多个应用程序配置用于执行如权利要求5至13任一项所述的方法。
  16. 一种计算机可读取存储介质，其特征在于，所述计算机可读取存储介质中存储有程序代码，所述程序代码可被处理器调用执行如权利要求5至13任一项所述的方法。
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