JP6143726B2 - 樹脂封止型半導体装置とその製造方法、リードフレーム - Google Patents
樹脂封止型半導体装置とその製造方法、リードフレーム Download PDFInfo
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- JP6143726B2 JP6143726B2 JP2014209702A JP2014209702A JP6143726B2 JP 6143726 B2 JP6143726 B2 JP 6143726B2 JP 2014209702 A JP2014209702 A JP 2014209702A JP 2014209702 A JP2014209702 A JP 2014209702A JP 6143726 B2 JP6143726 B2 JP 6143726B2
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- 239000004065 semiconductor Substances 0.000 title claims description 77
- 238000004519 manufacturing process Methods 0.000 title description 6
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- 229920005989 resin Polymers 0.000 claims description 75
- 239000000725 suspension Substances 0.000 claims description 42
- 238000007789 sealing Methods 0.000 claims description 23
- 239000003990 capacitor Substances 0.000 claims description 12
- 230000008878 coupling Effects 0.000 claims 1
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- 238000005859 coupling reaction Methods 0.000 claims 1
- 238000000034 method Methods 0.000 description 8
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
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- 229910052802 copper Inorganic materials 0.000 description 1
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- 239000010931 gold Substances 0.000 description 1
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- 238000002347 injection Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Lead Frames For Integrated Circuits (AREA)
Description
本発明の参考例について、以下に、図面に従って説明する。
本発明の実施形態についての説明に先立ち、樹脂封止工程及びリードフレーム1の外枠8の切断工程について、その内容と問題点について検討する。樹脂封止工程では図4に示すように、樹脂封止装置の上金型100と下金型101の間の空間に、Alワイヤ6a等でワイヤボンディングされた半導体チップ2等が搭載されたリードフレーム1を挟み込み、樹脂注入を行う。図4では、左側のタイバー11が上金型100と下金型101に挟まれ、ダムバーとしての役割を果たし、樹脂が左側から樹脂パッケージ12の外部に流出するのを阻止している。また、右側はリードフレーム1の外枠8が上金型100と下金型101に挟まれ、樹脂が右側から樹脂パッケージ12の外部に流出するのを阻止している。手前側、奥側も同様に外枠8により樹脂が樹脂パッケージ12の外部に流出するのを阻止している。
1a アウターリード
1b インナーリード
2 パワー系半導体チップ
3 コントローラ用半導体チップ
4 チップコンデンサ
5a,5b,5c 吊りリード
6a,6b Alワイヤ
7a,7b,7c Alワイヤ
8 リードフレーム外枠
9,10 連結リード
11 タイバー
12 樹脂パッケージ
13 アイランド
14a,14b,14c リードフレームのワイヤボンディング部
15,16 切欠き
17,18 樹脂バリ
100 上金型
101 下金型
Claims (2)
- 第1の半導体チップと、
第2の半導体チップと、
前記第1の半導体チップがダイボンドされた第1のアイランドと、前記第2の半導体チップがダイボンドされた第2のアイランドと、外枠と、前記第1のアイランドと前記外枠とを連結する第1の吊りリードと、前記第2のアイランドと前記外枠とを連結する第2の吊りリードと、タイバーと、前記第1の吊りリードと前記第2の吊りリードの間の前記外枠に形成された切欠きと、を有し、前記第2の半導体チップが電気的に接続されたリードフレームと、
前記リードフレーム及び前記第1及び第2の半導体チップを封止する樹脂パッケージと、を備え、
前記樹脂パッケージの外周に残存する前記リードフレームの外枠が前記切欠きを含む位置で切断されており、前記切欠き内に前記樹脂パッケージの一部が入り込んでいることを特徴とする樹脂封止型半導体装置。 - 半導体チップと、
第1及び第2の電極を有するチップコンデンサと、
前記半導体チップが搭載され、前記チップコンデンサの第1の電極が接着されたアイランドと、前記チップコンデンサの第2の電極が接着されたインナーリードと、外枠と、前記アイランドと前記外枠とを連結する第1の吊りリードと、前インナーリードと前記外枠とを連結する第2の吊りリードと、タイバーと、前記第1の吊りリードと前記第2の吊りリードの間の前記外枠に形成された切欠きと、を有し、前記半導体チップが電気的に接続されたリードフレームと、
前記リードフレーム、前記半導体チップ及び前記チップコンデンサを封止する樹脂パッケージと、を備え、
前記樹脂パッケージの外周に残存する前記リードフレームの外枠が前記切欠きを含む位置で切断されており、前記切欠き内に前記樹脂パッケージの一部が入り込んでいることを特徴とする樹脂封止型半導体装置。
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JP7134137B2 (ja) * | 2019-05-31 | 2022-09-09 | 三菱電機株式会社 | 半導体装置 |
CN114334671A (zh) * | 2021-12-31 | 2022-04-12 | 江苏芯德半导体科技有限公司 | 采用双刀切双排管脚的qfn封装方法 |
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JPS589348A (ja) * | 1981-07-09 | 1983-01-19 | Matsushita Electronics Corp | リ−ドフレ−ム |
JPS62119950A (ja) * | 1985-11-19 | 1987-06-01 | Nec Corp | 半導体装置用リ−ドフレ−ム |
JPS6361149U (ja) * | 1986-10-09 | 1988-04-22 | ||
JPH02310954A (ja) * | 1989-05-26 | 1990-12-26 | Hitachi Ltd | リードフレーム及びそれを用いた半導体装置 |
JP2551835Y2 (ja) * | 1991-11-22 | 1997-10-27 | 株式会社三井ハイテック | 半導体装置用リードフレーム |
JPH05275602A (ja) * | 1992-03-27 | 1993-10-22 | Omron Corp | 電子機器 |
JPH09199656A (ja) * | 1996-01-22 | 1997-07-31 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH1117100A (ja) * | 1997-06-19 | 1999-01-22 | Mitsubishi Electric Corp | 半導体装置 |
JP4414191B2 (ja) * | 2003-10-27 | 2010-02-10 | 株式会社三井ハイテック | 半導体装置用リードフレーム |
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