JP6109163B2 - 構成可能な多次元ドライバ及び受信器 - Google Patents

構成可能な多次元ドライバ及び受信器 Download PDF

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Publication number
JP6109163B2
JP6109163B2 JP2014518870A JP2014518870A JP6109163B2 JP 6109163 B2 JP6109163 B2 JP 6109163B2 JP 2014518870 A JP2014518870 A JP 2014518870A JP 2014518870 A JP2014518870 A JP 2014518870A JP 6109163 B2 JP6109163 B2 JP 6109163B2
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signal
driver circuit
circuit
driver
receiver
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Japanese (ja)
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JP2014523189A5 (https=
JP2014523189A (ja
Inventor
スリカンス ゴンディ
スリカンス ゴンディ
ロジャー アイザック
ロジャー アイザック
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Lattice Semiconductor Corp
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Lattice Semiconductor Corp
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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0292—Arrangements specific to the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03343—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0278—Arrangements for impedance matching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0298—Arrangement for terminating transmission lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Dc Digital Transmission (AREA)
  • Logic Circuits (AREA)
JP2014518870A 2011-06-30 2012-06-22 構成可能な多次元ドライバ及び受信器 Active JP6109163B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/174,616 2011-06-30
US13/174,616 US8760188B2 (en) 2011-06-30 2011-06-30 Configurable multi-dimensional driver and receiver
PCT/US2012/043767 WO2013003230A2 (en) 2011-06-30 2012-06-22 Configurable multi-dimensional driver and receiver

Publications (3)

Publication Number Publication Date
JP2014523189A JP2014523189A (ja) 2014-09-08
JP2014523189A5 JP2014523189A5 (https=) 2017-02-23
JP6109163B2 true JP6109163B2 (ja) 2017-04-05

Family

ID=47389989

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014518870A Active JP6109163B2 (ja) 2011-06-30 2012-06-22 構成可能な多次元ドライバ及び受信器

Country Status (7)

Country Link
US (2) US8760188B2 (https=)
EP (1) EP2726951A4 (https=)
JP (1) JP6109163B2 (https=)
KR (1) KR101954769B1 (https=)
CN (1) CN103547978B (https=)
TW (1) TWI533644B (https=)
WO (1) WO2013003230A2 (https=)

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EP2726951A4 (en) 2014-12-24
KR20140046002A (ko) 2014-04-17
CN103547978B (zh) 2017-05-03
US9281969B2 (en) 2016-03-08
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US20130002290A1 (en) 2013-01-03
US8760188B2 (en) 2014-06-24
US20140286388A1 (en) 2014-09-25
WO2013003230A2 (en) 2013-01-03
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WO2013003230A3 (en) 2013-04-04

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