JP6104407B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6104407B2 JP6104407B2 JP2015551328A JP2015551328A JP6104407B2 JP 6104407 B2 JP6104407 B2 JP 6104407B2 JP 2015551328 A JP2015551328 A JP 2015551328A JP 2015551328 A JP2015551328 A JP 2015551328A JP 6104407 B2 JP6104407 B2 JP 6104407B2
- Authority
- JP
- Japan
- Prior art keywords
- switching element
- power switching
- temperature
- collector
- gate voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
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Description
<装置構成>
本発明に係る半導体装置の実施の形態1について、図1〜図6を用いて説明する。図1は本発明に係る実施の形態1の半導体装置100の構成を示す断面図である。図1において、銅(Cu)材、アルミニウム(Al)材またはCuを主成分とする合金材で構成されるベース板16の主面上に、絶縁基板29が接合されている。
以上説明した可変ゲート電圧回路90を有した半導体装置100におけるはんだクラックの自己修復動作(はんだ溶融プロセス)について、図1および図5を参照しつつ図6に示すフローチャートを用いて説明する。
本発明に係る半導体装置の実施の形態2について、図7〜図11を用いて説明する。
図7は本発明に係る実施の形態2の半導体装置200の構成を示す断面図である。なお、図7においては、図1を用いて説明した半導体装置100と同一の構成については同一の符号を付し、重複する説明は省略する。
次に、はんだ溶融プロセスの要否の判断を行うための電力用半導体素子21下部の熱抵抗値の算出方法について図9〜図11を用いて説明する。なお、以下の説明では、ΔVCE(sat)法を用いて電力用半導体素子21下部の熱抵抗値を算出する。
以上説明した実施の形態2においては、はんだ溶融プロセスの要否の判断を行うための電力用半導体素子21下部の熱抵抗値の算出にΔVCE(sat)法を用いる例を示したが、以下に説明するΔVGE法を用いても良い。
以上説明した実施の形態2においては、はんだ溶融プロセスの要否の判断を行うために電力用半導体素子21下部の熱抵抗値を算出する構成について説明したが、より簡易的には、電力用半導体素子21の上面上に配設した温度検出ダイオードTD1による電力用半導体素子21の上面温度に基づいてはんだ溶融プロセスの要否を判断しても良い。
以上説明した本発明に係る半導体装置の実施の形態1および2においては、電力用半導体素子21の電流検出エミッタと接地線Nとの間に接続された電流検出抵抗4によりエミッタ電流を検出する例を示したが、図17に示す可変ゲート電圧回路90Bのように構成しても良い。なお、図17においては、図5を用いて説明した可変ゲート電圧回路90と同一の構成については同一の符号を付し、重複する説明は省略する。
以上説明した実施の形態1〜3においては、ゲート電圧を調整して半導体素子下はんだ層31を溶融させることで、半導体素子下はんだ層31のクラックを自己修復する方法を説明したが、半導体素子下はんだ層31の溶融の際に、溶融したはんだが絶縁基板29の導電板28から溢れ、絶縁基材26にまで達するはんだ垂れを防止するために、図18に示す構成を採っても良い。
以上説明した実施の形態1〜3においては、ゲート電圧を調整して半導体素子下はんだ層31を溶融させることで、半導体素子下はんだ層31のクラックを自己修復する方法を説明したが、半導体素子下はんだ層31の溶融の際に、溶融したはんだが絶縁基板29の導電板28から溢れ、絶縁基材26にまで達するはんだ垂れを防止するために、図20に示す構成を採っても良い。
以上説明した実施の形態1においては、ワイヤボンドモジュール型の半導体装置において、半導体素子下はんだ層31を溶融させる構成を説明したが、図22に示すようなDLB(Direct Lead Bonding)型の半導体装置においても適用可能である。
以上説明した実施の形態1〜6においては、電力用半導体素子21の半導体の種類を特に限定しなかったが、電力用半導体素子21は半導体基板としてシリコン(Si)基板を使用するシリコン半導体に限定されるものではなく、半導体基板として炭化珪素(SiC)基板を使用する炭化珪素半導体でも良いし、他のワイドバンドギャップを有する半導体、例えば、窒化ガリウム系材料や、ダイヤモンドで構成される基板を使用しても良い。
Claims (8)
- ベース板と、
前記ベース板上に搭載された絶縁基板と、
前記絶縁基板上にはんだ層により接合された電力用スイッチング素子と、を有し、
前記ベース板、前記絶縁基板および前記電力用スイッチング素子とでモジュールを構成し、前記モジュール上に制御基板を備えた半導体装置であって、
前記制御基板は、
前記電力用スイッチング素子のコレクタ−エミッタ間電圧を測定し、前記コレクタ−エミッタ間電圧とコレクタ電流との積で規定される任意の目標電力を前記電力用スイッチング素子に供給するようにゲート電圧を変更する可変ゲート電圧回路を有し、
前記可変ゲート電圧回路は、
前記任意の目標電力として、前記はんだ層を溶融させる電力が供給されるように前記ゲート電圧を調整する、半導体装置。 - 前記モジュールは、
前記電力用スイッチング素子の上面に配設された少なくとも1つの温度検出素子をさらに備え、
前記可変ゲート電圧回路は、
前記少なくとも1つの温度検出素子で検出された前記電力用スイッチング素子の通常動作時の上面温度と、予め定めた閾値との比較を行い、前記上面温度が前記閾値より大きい場合に、前記任意の目標電力が前記電力用スイッチング素子に供給されるように前記ゲート電圧を調整するマイクロコンピュータを有する、請求項1記載の半導体装置。 - 前記電力用スイッチング素子は、平面視形状が矩形であって、
前記少なくとも1つの温度検出素子は、
前記電力用スイッチング素子の上面の四隅にそれぞれ配設される、請求項2記載の半導体装置。 - 前記モジュールは、
前記電力用スイッチング素子の上面に配設された第1の温度検出素子と、
前記ベース板の前記モジュール内の主面上に配設された第2の温度検出素子と、をさらに備え、
前記可変ゲート電圧回路は、
電力用スイッチング素子に一定のコレクタ電流が流れるようにゲート電圧を調整しながら前記第1の温度検出素子で前記電力用スイッチング素子の上面温度を測定し、温度変化に対するコレクタ−エミッタ間電圧特性を取得すると共に、
第1のコレクタ電流を流す前の第1の期間と、前記一定のコレクタ電流を流した後の第2の期間とで、それぞれ前記第1のコレクタ電流のm分の1(mは整数)の第2の電流を流し、それぞれ第1および第2のコレクタ−エミッタ間電圧を取得し、
前記第1および第2のコレクタ−エミッタ間電圧にそれぞれ対応する前記電力用スイッチング素子の第1および第2の上面温度を前記コレクタ−エミッタ間電圧特性から算出し、
また、前記第2の温度検出素子を用いて、前記第1および第2の期間での前記ベース板の温度である第1および第2のベース板温度を取得し、
前記第1および第2の上面温度、前記第1および第2のベース板温度、前記第1のコレクタ電流、前記第1のコレクタ電流を流した場合のコレクタ−エミッタ間電圧と、前記第1のコレクタ電流を供給した第3の期間の情報に基づいて、数式(1)により前記電力用スイッチング素子の下部の熱抵抗を算出し、
- 前記モジュールは、
前記電力用スイッチング素子の上面に配設された第1の温度検出素子と、
前記ベース板の前記モジュール内の主面上に配設された第2の温度検出素子と、をさらに備え、
前記可変ゲート電圧回路は、
電力用スイッチング素子に一定のコレクタ電流が流れるようにゲート電圧を調整しながら前記第1の温度検出素子で前記電力用スイッチング素子の上面温度を測定し、温度変化に対するゲート−エミッタ間電圧特性を取得すると共に、
第1のコレクタ電流を流す前の第1の期間と、前記一定のコレクタ電流を流した後の第2の期間とで、それぞれ前記第1のコレクタ電流のm分の1(mは整数)の第2の電流を流し、それぞれ第1および第2のゲート−エミッタ間電圧を取得し、
前記第1および第2のゲート−エミッタ間電圧にそれぞれ対応する前記電力用スイッチング素子の第1および第2の上面温度を前記ゲート−エミッタ間電圧特性から算出し、
また、前記第2の温度検出素子を用いて、前記第1および第2の期間での前記ベース板の温度である第1および第2のベース板温度を取得し、
前記第1および第2の上面温度、前記第1および第2のベース板温度、前記第1のコレクタ電流、前記第1のコレクタ電流を流した場合のコレクタ−エミッタ間電圧と、前記第1のコレクタ電流を供給した第3の期間の情報に基づいて、数式(2)により前記電力用スイッチング素子の下部の熱抵抗を算出し、
- 前記絶縁基板は、
絶縁基材上に配設した導電板を有し、
前記電力用スイッチング素子は、前記導電板上に前記はんだ層により接合され、
前記導電板の主面内に、前記電力用スイッチング素子の周囲を囲むように設けられた、溝状のポケットをさらに備える、請求項1記載の半導体装置。 - 前記絶縁基板は、
絶縁基材上に配設した導電板を有し、
前記電力用スイッチング素子は、前記導電板上に前記はんだ層により接合され、
前記導電板の主面上に、前記電力用スイッチング素子の周囲を囲むように設けられた、壁状の突起をさらに備える、請求項1記載の半導体装置。 - 前記電力用スイッチング素子は、
ワイドバンドギャップ半導体基板上に形成されるワイドバンドギャップスイッチング素子である、請求項1記載の半導体装置。
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KR20170097421A (ko) * | 2016-02-18 | 2017-08-28 | 엘에스산전 주식회사 | 2차원 배열 전력변환장치용 냉각 시스템 |
JP6658441B2 (ja) * | 2016-10-06 | 2020-03-04 | 三菱電機株式会社 | 半導体装置 |
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