JP5953703B2 - リードフレームおよび半導体装置 - Google Patents

リードフレームおよび半導体装置 Download PDF

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Publication number
JP5953703B2
JP5953703B2 JP2011239444A JP2011239444A JP5953703B2 JP 5953703 B2 JP5953703 B2 JP 5953703B2 JP 2011239444 A JP2011239444 A JP 2011239444A JP 2011239444 A JP2011239444 A JP 2011239444A JP 5953703 B2 JP5953703 B2 JP 5953703B2
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Japan
Prior art keywords
lead
region
chip mounting
terminal
semiconductor device
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Expired - Fee Related
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JP2011239444A
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English (en)
Japanese (ja)
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JP2013098332A5 (enExample
JP2013098332A (ja
Inventor
渡辺　信二
信二 渡辺
昭久 栄森
昭久 栄森
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Sony Corp
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Sony Corp
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Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2011239444A priority Critical patent/JP5953703B2/ja
Priority to US13/659,557 priority patent/US8928136B2/en
Priority to CN201210423881.9A priority patent/CN103094238B/zh
Publication of JP2013098332A publication Critical patent/JP2013098332A/ja
Publication of JP2013098332A5 publication Critical patent/JP2013098332A5/ja
Application granted granted Critical
Publication of JP5953703B2 publication Critical patent/JP5953703B2/ja
Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/495—Lead-frames or other flat leads
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491—Disposition
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2011239444A 2011-10-31 2011-10-31 リードフレームおよび半導体装置 Expired - Fee Related JP5953703B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2011239444A JP5953703B2 (ja) 2011-10-31 2011-10-31 リードフレームおよび半導体装置
US13/659,557 US8928136B2 (en) 2011-10-31 2012-10-24 Lead frame semiconductor device
CN201210423881.9A CN103094238B (zh) 2011-10-31 2012-10-24 引线框架和半导体器件

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011239444A JP5953703B2 (ja) 2011-10-31 2011-10-31 リードフレームおよび半導体装置

Publications (3)

Publication Number Publication Date
JP2013098332A JP2013098332A (ja) 2013-05-20
JP2013098332A5 JP2013098332A5 (enExample) 2014-11-27
JP5953703B2 true JP5953703B2 (ja) 2016-07-20

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JP2011239444A Expired - Fee Related JP5953703B2 (ja) 2011-10-31 2011-10-31 リードフレームおよび半導体装置

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US (1) US8928136B2 (enExample)
JP (1) JP5953703B2 (enExample)
CN (1) CN103094238B (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6352009B2 (ja) * 2013-04-16 2018-07-04 ローム株式会社 半導体装置
CN103337488B (zh) * 2013-06-05 2016-09-14 吉林华微斯帕克电气有限公司 一种引线框架
JP6413709B2 (ja) * 2014-12-02 2018-10-31 富士電機株式会社 半導体装置およびその製造方法
US9966326B2 (en) * 2015-03-16 2018-05-08 Unisem (M) Berhad Lead frames with wettable flanks
JP6507779B2 (ja) * 2015-03-26 2019-05-08 セイコーエプソン株式会社 電気光学装置、電気光学装置の製造方法、および電子機器
JP6555927B2 (ja) * 2015-05-18 2019-08-07 大口マテリアル株式会社 半導体素子搭載用リードフレーム及び半導体装置の製造方法
JP6923299B2 (ja) * 2016-09-26 2021-08-18 株式会社アムコー・テクノロジー・ジャパン 半導体装置及び半導体装置の製造方法
JP6772087B2 (ja) * 2017-02-17 2020-10-21 新光電気工業株式会社 リードフレーム及びその製造方法
US10679929B2 (en) * 2017-07-28 2020-06-09 Advanced Semiconductor Engineering Korea, Inc. Semiconductor package device and method of manufacturing the same
US20190221502A1 (en) * 2018-01-17 2019-07-18 Microchip Technology Incorporated Down Bond in Semiconductor Devices
CN110828442A (zh) * 2019-11-04 2020-02-21 弘凯光电(深圳)有限公司 封装结构及其制作方法
CN115706071A (zh) * 2021-08-13 2023-02-17 江苏长电科技股份有限公司 Qfn封装结构及其制造方法
CN115706068A (zh) * 2021-08-13 2023-02-17 江苏长电科技股份有限公司 Qfn封装结构及其制造方法

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5084753A (en) * 1989-01-23 1992-01-28 Analog Devices, Inc. Packaging for multiple chips on a single leadframe
JPH0621319A (ja) * 1992-06-30 1994-01-28 Nec Corp 半導体装置用リードフレーム
JP2811170B2 (ja) * 1996-06-28 1998-10-15 株式会社後藤製作所 樹脂封止型半導体装置及びその製造方法
DE19808193B4 (de) * 1998-02-27 2007-11-08 Robert Bosch Gmbh Leadframevorrichtung und entsprechendes Herstellungsverfahren
JPH11340405A (ja) * 1998-05-22 1999-12-10 Fujitsu Quantum Devices Kk リードフレーム、半導体装置およびその製造方法
KR100526844B1 (ko) * 1999-10-15 2005-11-08 앰코 테크놀로지 코리아 주식회사 반도체패키지 및 그 제조방법
US6198171B1 (en) * 1999-12-30 2001-03-06 Siliconware Precision Industries Co., Ltd. Thermally enhanced quad flat non-lead package of semiconductor
TW447059B (en) * 2000-04-28 2001-07-21 Siliconware Precision Industries Co Ltd Multi-chip module integrated circuit package
JP2001313363A (ja) * 2000-05-01 2001-11-09 Rohm Co Ltd 樹脂封止型半導体装置
JP2002026190A (ja) * 2000-07-03 2002-01-25 Dainippon Printing Co Ltd 樹脂封止型半導体装置
US6661082B1 (en) * 2000-07-19 2003-12-09 Fairchild Semiconductor Corporation Flip chip substrate design
JP3895570B2 (ja) * 2000-12-28 2007-03-22 株式会社ルネサステクノロジ 半導体装置
US6720207B2 (en) * 2001-02-14 2004-04-13 Matsushita Electric Industrial Co., Ltd. Leadframe, resin-molded semiconductor device including the leadframe, method of making the leadframe and method for manufacturing the device
JP2003204027A (ja) * 2002-01-09 2003-07-18 Matsushita Electric Ind Co Ltd リードフレーム及びその製造方法、樹脂封止型半導体装置及びその製造方法
CN100380651C (zh) 2002-04-30 2008-04-09 株式会社瑞萨科技 半导体器件和电子设备
US7525184B2 (en) * 2002-07-01 2009-04-28 Renesas Technology Corp. Semiconductor device and its manufacturing method
JP2004071801A (ja) * 2002-08-06 2004-03-04 Shinko Electric Ind Co Ltd リードフレーム及びその製造方法
US20040124508A1 (en) * 2002-11-27 2004-07-01 United Test And Assembly Test Center Ltd. High performance chip scale leadframe package and method of manufacturing the package
JP2005057067A (ja) * 2003-08-05 2005-03-03 Renesas Technology Corp 半導体装置およびその製造方法
JP2005191342A (ja) * 2003-12-26 2005-07-14 Renesas Technology Corp 半導体装置およびその製造方法
US7247937B2 (en) * 2005-01-06 2007-07-24 Via Technologies, Inc. Mounting pad structure for wire-bonding type lead frame packages
JP2007012857A (ja) * 2005-06-30 2007-01-18 Renesas Technology Corp 半導体装置
US7301225B2 (en) * 2006-02-28 2007-11-27 Freescale Semiconductor, Inc. Multi-row lead frame
JP4652281B2 (ja) 2006-05-29 2011-03-16 パナソニック株式会社 樹脂封止型半導体装置
US7556987B2 (en) * 2006-06-30 2009-07-07 Stats Chippac Ltd. Method of fabricating an integrated circuit with etched ring and die paddle
WO2008057770A2 (en) * 2006-10-27 2008-05-15 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
CN101308832B (zh) * 2007-05-17 2010-06-16 南茂科技股份有限公司 用于无引线封装的引线框、其封装结构及其制造方法
JP5184558B2 (ja) * 2010-01-18 2013-04-17 ルネサスエレクトロニクス株式会社 半導体装置

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