CN103094238B - 引线框架和半导体器件 - Google Patents
引线框架和半导体器件 Download PDFInfo
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Abstract
本申请涉及引线框架和半导体器件。一种引线框架包括:设在前表面上的芯片安装区域;包括布置在所述芯片安装区域的平面内方向上的多个凹进和凸起部;以及布置在所述凹进部中的端子。所述引线区域从所述前表面起的厚度小于所述端子从所述前表面起的厚度。
Description
技术领域
本技术涉及诸如半导体芯片之类的芯片被安装到的引线框架,并且涉及包括该引线框架的半导体器件。
背景技术
近年来,为了解决电子单元的小型化和更高密度,已进行了对使用树脂来密封诸如半导体芯片之类的芯片的封装的小型化。前述封装的形式的示例包括使用引线框架的封装。使用引线框架的小型封装的示例包括QFN(四方扁平无引线封装)和SON(小外形无引线封装)。所谓的无引线封装已经引起了关注。
在封装型半导体器件中,半导体芯片被布置在引线框架的中心部分内的芯片安装区域中,半导体芯片的电极焊盘被连接到在芯片安装区域周围的外部端子,信号因此被发送(例如,日本未经审查的专利申请公开No.2009-278117和2006-222471)。此外,通过将半导体芯片接地(GND),稳定了电特性。
发明内容
然而,在半导体芯片被接地的情况下,如果如在日本未经审查的专利申请公开No.2009-278117中那样在管芯衬垫(芯片安装区域)中进行连接,那么在半导体芯片周围的连接区域(接合区域)是必需的。此外,在日本未经审查的专利申请公开No.2006-222471中,由于GND端子被布置在已安装的端子之间,所以在半导体芯片周围的外部端子的数目因接地端子的数目而增加。也就是说,在日本未经审查的专利申请公开No.2009-278117和2006-222471两者中,已存在半导体器件的封装尺寸被增大的缺点。
希望提供一种能够通过将芯片接地来稳定电特性并且减小封装尺寸的引线框架,以及一种包括该引线框架的半导体器件。
根据本技术的实施例,提供了一种引线框架,包括:设在前表面(front surface)上的芯片安装区域;包括布置在所述芯片安装区域的平面内方向上的多个凹进和凸起部的引线区域;以及布置在所述凹部中的端子。所述引线区域从所述前表面起的厚度小于所述端子从所述前表面起的厚度。
根据本技术的实施例,提供了一种半导体器件,包括:半导体芯片;以及引线框架。所述引线框架包括:设在前表面上的芯片安装区域;包括布置在所述芯片安装区域的平面内方向上的多个凹进和凸起部的引线区域;以及布置在所述凹进部中的端子。所述引线区域从所述前表面起的厚度小于所述端子从所述前表面起的厚度。所述半导体芯片被安装在所述芯片安装区域上,所述半导体芯片通过第一接线电连接到所述端子并且通过第二接线电连接到所述引线区域。
在根据本技术的实施例的引线框架和半导体器件中,由于所述引线区域从所述前表面起的厚度小于所述端子从所述前表面起的厚度,所以在对其进行封装时,所述引线区域的后表面(rear surface)被用密封树脂覆盖,并且不从所述密封树脂暴露。
根据根据本技术的实施例的引线框架和半导体器件,由于引线区域从前表面起的厚度小于端子从前表面起的厚度,所以在不增加芯片周围的外部端子的数目的情况下,半导体芯片被连接至电位不同于所述端子的电位的点,例如,被接地。此外,在芯片安装区域中不必设有接合区域。因此,芯片被接地,并且芯片的封装尺寸被小型化。
将会理解的是,前述的一般描述和下面的详细描述两者都是示例性的,并且旨在提供对所要求保护的技术的进一步的解释。
附图说明
附图被包括来提供对本公开的进一步理解,并且被并入及构成本说明书的一部分。附图示出了实施例并且与说明书一起用于解释本技术的原理。
图1是示出了根据本公开的实施例的半导体器件的配置的平面图。
图2示出了沿图1的直线II-II得到的截面图。
图3示出了沿图1的直线III-III得到的截面图。
图4示出了沿图1的直线IV-IV得到的截面图。
图5A和图5B是示出了图1中示出的引线框架的配置的平面图。
图6是示出了安装图1中示出的半导体器件的方法的示例的截面图。
图7A是示出了按步骤顺序制造图1中示出的半导体器件的方法的平面图,图7B是沿图7A的直线B-B得到的截面图。
图8A是示出了图7A的步骤之后的步骤的平面图,图8B是沿图8A的直线B-B得到的截面图。
图9A是示出了图8A的步骤之后的步骤的平面图,图9B是沿图9A的直线B-B得到的截面图,图9C是沿图9A的直线C-C得到的截面图。
图10A是示出了图9A的步骤之后的步骤的平面图,图10B是沿图10A的直线B-B得到的截面图。
图11A是示出了图10A的步骤之后的步骤的平面图,图11B是沿图11A的直线B-B得到的截面图。
图12A是示出了图11A的步骤之后的步骤的平面图,图12B是沿图12A的直线B-B得到的截面图。
图13A是示出了图12A的步骤之后的步骤的平面图,图13B是沿图13A的直线B-B得到的截面图。
图14是示出了根据比较示例1的半导体器件的配置的截面图。
图15A和图15B是示出了根据比较示例2的半导体器件的配置的视图。
图16是示出了根据修改例1的半导体器件的配置的截面图。
图17A是示出了根据修改例2的引线框架的配置的前表面的平面图,图17B是其后表面的平面图。
图18是示出了在半导体芯片被安装在图17A和图17B中示出的引线框架上的情况下的配置的截面图。
具体实施方式
将参照附图在下文中对本技术的实施例进行详细的描述。将以下列顺序给出描述。
1.第一实施例(其中包括了一个半导体芯片的示例)
2.修改例1(其中包括多个半导体芯片的示例)
3.修改例2(其中包括多个引线框架的示例)
【实施例】
图1示出了根据本公开的实施例的半导体器件(半导体器件1)的顶面的配置。图2示出了沿图1的直线II-II得到的截面图的配置。图3示出了沿图1的直线III-III得到的截面图的配置。图4示出了沿图1的直线IV-IV得到的截面图的配置。半导体器件1使用QFN来封装。在半导体器件1中,设在引线框架10的前表面上的半导体芯片21被用密封树脂41覆盖。
图5A示出了引线框架10的前表面的平面配置,图5B示出了其后表面的平面配置。图5A和图5B中的打点区域表示比其他部分较薄的部分。这些较薄的部分是通过从前表面(图5A)和后表面(图5B)刻掉一定量的厚度而创建的。
引线框架10例如由镀铜(Cu)制成,并且具有芯片安装区域11(管芯衬垫(diepad))、端子12(信号端子)、引线区域13A以及端子12与引线区域13A之间的间隙14。在间隙14与端子12之间,提供了支承端子12的外伸部(flared section)15(图2)。图5A的打点区域代表外伸部15,图5B的打点区域代表引线区域13A。
芯片安装区域11是以矩形形状设在引线框架10的中心部分中的。引线区域13A被设在芯片安装区域11周围。芯片安装区域11和引线区域13A被连结(link)并且集成。半导体芯片21被安装在芯片安装区域11上。引线区域13A在芯片安装区域11的平面内方向(in-plane direction)上在其外围上具有多个凹进和凸起部,并且各个多个凸起部为GND引线13。在这种情况下,引线区域13A(GND引线13)被设在包围芯片安装区域11的所有四个边上。
端子12被设在引线区域13A的各个凹进部中(其间具有间隙14)。引线区域13A与芯片安装区域11电分离。换句话说,端子12被布置在GND引线13(引线区域13A的凸起部)之间。此外,由于引线区域13A存在于端子12与芯片安装区域11之间,所以端子12的三面被引线区域13A所包围。端子12被从后表面上的密封树脂41暴露(图2),并且被通过导线31(第一接线)电连接至半导体芯片21的电极焊盘。同时,半导体芯片21的另一个电极焊盘被通过导线31(第二接线)电连接至GND引线13并且被接地。换句话说,将端子12电连接至半导体芯片21的导线31是信号线,将GND引线13电连接至半导体芯片21的导线31是GND线。通过提供如上所述的端子12和GND引线13,即使通过端子12发送的信号具有高频率,这些高频信号也被彼此分离,信号之间的干扰被抑制,并且半导体器件1的高频特性得以改善。此外,由于GND引线13存在于所有的各个端子12之间,所以导线31被允许连接至任何GND引线13,并且接线自由度得以提高。
如图4所示出的,端子12具有梯形形状(trapezoidal shape),其中在布置方向(端子12与GND引线13对齐的方向)上的截面形状中的侧壁(侧表面)具有曲线。注意该侧壁可以是直线的。通过将端子12的截面形状形成为梯形的形状,固定了端子12的后表面的尺寸,并且稳定了半导体器件1的电特性。
在根据此实施例的引线框架10中,引线区域13A从前表面起的厚度T2小于端子12从前表面起的厚度T1(图2至图4)。例如,在T1为0.125mm的情况下,T2在约0.04mm到约0.09mm之间(包括0.04和0.09)。如上所述通过将引线区域13A的厚度T2的值设置为小于端子12的厚度T1的值的值,引线区域13A的后表面被用密封树脂41覆盖(图3)。也就是说,由于各个GND引线13没有作为外部端子的功能,所以允许减小端子12之间的节距P1(图5A)。因此,允许减小在半导体芯片21周围的外部端子的数目以使半导体器件1小型化。节距P1例如是0.4mm,端子12与GND引线13之间的节距P2例如是0.2mm。
如上所述的包括引线区域13A的引线框架10被安装在安装衬底43上(中间具有焊料42),并且例如被如图6所示出地那样接地。也就是说,被作为一个整体而集成的芯片安装区域11和引线区域13A变成GND端子。在将半导体器件1安装在安装衬底43上时,从密封树脂41暴露的端子12之间的节距P1大于密封树脂41中的端子12与GND引线13之间的节距P2(图5A)。因此,半导体器件1被容易地连接到安装衬底43。
此外,在根据此实施例的引线框架10中,引线区域13A与芯片安装区域11集成。因此,改善了它的强度,并且防止扭曲和变形发生。在如上所述的、其中扭曲和变形被抑制的引线框架10中,其运送变得容易。因此,引线框架10被允许由薄铜箔制成以改善它的产率。此外,由于引线区域13A与芯片安装区域11集成,所以增大了热辐射面积,并且改善了半导体器件1的热辐射特性。此外,由于引线区域13A被连结到芯片安装区域11,所以可以容易地安装尺寸大于芯片安装区域11的尺寸的半导体芯片21。通过在引线框架10内设有外伸部15,即使安装了尺寸大于芯片安装区域11的尺寸的半导体芯片21,在防止半导体芯片21与端子12之间的接触的同时,小型化也是可实现的,并且端子12的尺寸被保留。
半导体芯片21被通过粘合剂22固定在芯片安装区域11上,并且它的电极焊盘被通过导线31接合到相应的端子12和GND引线13。半导体芯片21例如由诸如垂直NPN晶体管(V-NPN Trs)、垂直PNP晶体管(V-PNP Trs)、P沟道MOS晶体管(PMOS)、N沟道MOS晶体管(NMOS)、MOS电容以及电阻(多晶硅电阻)之类的多个半导体器件配置而成。导线31由诸如金(Au)线之类的导电金属制成。
密封树脂41将半导体芯片21密封在引线框架10上。密封树脂41覆盖半导体芯片21、导线31、引线框架10的前表面以及引线区域13A的后表面。密封树脂41由诸如环氧树脂之类的绝缘树脂制成。
例如,可以如下制造半导体器件1。
首先,如图7A和图7B所示出的,条带(tape)53被接合到包括芯片安装区域11、端子12、引线区域13A、间隙14以及外伸部15的引线框架10的后表面。框架10被引线框架片(leadframe sheet)上的支承部16支承。在随后的步骤中形成密封树脂41时,条带53防止在引线框架10的后表面上发生树脂毛刺,并且例如由聚酰亚胺条带等制成。引线框架10中的芯片安装区域11、端子12、引线区域13A、间隙14以及外伸部15的形成是通过例如利用诸如冲压工艺和蚀刻工艺之类的适当方法将金属板图案化预定的形状来执行的。
在条带53被接合到引线框架10之后,半导体芯片21被通过粘合剂22粘附到芯片安装区域11(图8A和图8B)。
接下来,半导体芯片21的电极焊盘被通过导线31电连接至相应的端子12和GND引线13(图9A至图9C)。
随后,在引线框架10的前表面、引线区域13A的后表面、半导体芯片21、以及导线31被用密封树脂41完全地覆盖(图10A和10B)之后,条带53被从引线框架10剥落(图11A和图11B)。
随后,在带有产品名称等等的标记54被雕刻在密封树脂41的表面上(图12A和图12B)之后,如图13A和图13B中所示出的,引线框架10被通过切割器等等从引线框架片沿切割面直线55切割。通过上述的处理,完成了图1至图4所示出的半导体器件1。
在根据此实施例的半导体器件1中,引线区域13A的厚度T2小于端子12的厚度T1。因此,即使半导体芯片21被接地,它的封装尺寸也被小型化。以下将通过使用比较示例1和2对这一点给出详细的描述。
图14示出了根据比较示例1的半导体器件100的截面配置。在半导体器件100中,半导体芯片21的电极焊盘被通过导线31电连接至芯片安装区域111(管芯衬垫),并且被接地。在这种情况下,由于在芯片安装区域111中连接区域111A(接合区域)是必需的,所以半导体器件100的封装尺寸变大。此外,不允许芯片安装区域111比半导体芯片21小。
图15A和图15B示出了根据比较示例2的半导体器件101的截面配置。图15A示出了其平面配置,图15B示出了沿图15A的直线B-B得到的截面的配置。在半导体器件101中,半导体芯片21通过与芯片安装区域121集成的GND引线123接地。然而,由于GND引线123的后表面被从密封树脂41暴露,所以GND引线123充当外部端子,并且增加了半导体芯片21周围的外部端子的数目。也就是说,不允许减小GND引线123与端子12之间的节距P100,并且半导体器件101的封装尺寸变大。
同时,在半导体器件1中,由于引线区域13A的厚度T2小于端子12的厚度T1,所以引线区域13A(GND引线13)的后表面被用密封树脂41覆盖。从而,被集成的芯片安装区域11和引线区域13A用作接地端子。因此,在不增加在半导体芯片21周围的外部端子的数目的情况下,半导体芯片21被接地。此外,在芯片安装区域11中不必设有连接区域。因此,半导体器件1被小型化了。
此外,由于端子12被布置在引线区域13A的凹进部中,并且端子12被GND引线13包围,所以改善了半导体器件1的高频特性。
此外,由于芯片安装区域11和引线区域13A被集成,所以改善了引线框架10的强度和热辐射特性。除此之外,容易安装尺寸大于芯片安装区域11的尺寸的半导体芯片21。
如上所述,在此实施例中,引线区域13A的厚度T2小于端子12的厚度T1。因此,在没有增加半导体芯片21周围的外部端子的数目的情况下或者在芯片安装区域11内不设有连接区域的情况下,半导体芯片21被接地。因此,半导体芯片21被接地并且半导体器件1被小型化了。
以下将给出对本技术的前述实施例的修改例的描述。对于和前述实施例的组件相同的组件,对其附加相同的标号,并且将适当省略其描述。
【修改例1】
图16示出了根据修改例1的半导体器件(半导体器件2)的截面配置。半导体器件2与根据前述实施例的半导体器件1的不同之处在于在一个芯片安装区域11内设置了多个半导体芯片(半导体芯片21A、21B以及21C)。除了这一点以外,半导体器件2具有与根据前述实施例的半导体器件1的配置相似的配置,并且它的功能和它的效果与根据前述实施例的半导体器件1的功能和效果相似。
半导体芯片21A、21B以及21C的电极焊盘被通过导线31彼此电连接,并且被安装在引线框架10(芯片安装区域11)上。也就是说,半导体器件2具有所谓的多芯片配置。
【修改例2】
根据修改例2的半导体器件(半导体器件3)具有设有多个芯片安装区域(芯片安装区域11A、11B以及11C)的引线框架50。除了这一点之外,半导体器件3具有与根据前述实施例的半导体器件1的配置相似的配置,并且它的功能和它的效果与根据前述实施例的半导体器件1的功能和效果相似。
如图17A、图17B以及图18中所示出的,引线框架50具有在其间用间隙分开的三个芯片安装区域11A、11B以及11C。与各个芯片安装区域11A、11B以及11C集成的引线框架13A被共同使用,并且其各个部分彼此连结。例如,在多个半导体芯片21A、21B以及21C被安装在半导体器件3上的情况下(图18),可以根据每个电源电位来分别提供芯片安装区域11A、11B以11C。在引线框架50中,集成了多个GND引线13(引线区域13A),即使芯片安装区域11A、11B以及11C被分别提供,也允许半导体芯片21A、21B以及21C通过一个引线框架50来保持。
虽然参照实施例和修改例对本技术进行了描述,但是本技术不限于前述实施例等等,并且可以进行各种修改。例如,在前述实施例中,已经给出了对引线区域13A被接地的情况的描述。然而,引线区域13A可以被连接至具有除GND以外的电位的点。
此外,虽然在前述实施例等等中,已经给出了对半导体器件1的封装为QFN类型的情况的描述,但是可以使用诸如SON类型之类的除QFN类型以外的封装类型。
此外,每个部分的材料、厚度、形成方法、形成条件等等不限于在前述实施例中描述的那些等等,而且可以采用其它材料、其它厚度、其它形成方法以及其它形成条件。
可以从上述的示例性实施例和本公开的修改例实现至少下面的配置。
(1)一种引线框架,包括:
设在前表面上的芯片安装区域;
包括布置在所述芯片安装区域的平面内方向上的多个凹进和凸起部的引线区域;以及
布置在所述凹进部中的端子,其中
所述引线区域从所述前表面起的厚度小于所述端子从所述前表面起的厚度。
(2)根据(1)所述的引线框架,其中,所述引线区域与所述芯片安装区域集成,并且所述引线区域与所述端子电分离。
(3)根据(1)或(2)所述的引线框架,其中,所述端子的截面的形状是梯形形状。
(4)根据(1)至(3)中任一项所述的引线框架,其中
所述芯片安装区域被设在中心部分中,并且所述引线区域被设在芯片安装区域周围,并且
所述端子被布置在所述引线区域中的所有的凹进部中的每一个中。
(5)一种半导体器件,包括:
半导体芯片;以及
引线框架,其中
所述引线框架包括:
设在前表面上的芯片安装区域,
包括布置在所述芯片安装区域的平面内方向上的多个凹进和凸起部的引线区域,以及
布置在所述凹进部中的端子,并且
所述引线区域从所述前表面起的厚度小于所述端子从所述前表面起的厚度,
所述半导体芯片被安装在所述芯片安装区域上,所述半导体芯片被通过第一接线电连接至所述端子,并且被通过第二接线电连接至所述引线区域。
(6)根据(5)所述的半导体器件,其中,所述半导体芯片大于所述芯片安装区域。
(7)根据(5)或(6)所述的半导体器件,其中
所述引线框架的前表面与所述引线区域的后表面以及所述半导体芯片被用密封树脂覆盖,并且
所述端子的后表面被从密封树脂暴露。
(8)根据(5)至(7)中任一项所述的半导体器件,其中,所述半导体芯片与所述引线框架使用QFN(四方扁平无引线封装)来封装。
(9)根据(5)至(8)中任一项所述的半导体器件,其中,所述引线区域与所述芯片安装区域集成,并且所述引线区域与所述端子电分离。
(10)根据(5)至(9)中任一项所述的半导体器件,其中,所述第一接线是信号线,而所述第二接线是接地(GND)线。
(11)根据(5)至(10)中任一项所述的半导体器件,在单个芯片安装区域上包括多个所述半导体芯片。
(12)根据(9)或(10)所述的半导体器件,其中
所述引线框架包括多个芯片安装区域,所述多个芯片安装区域被间隙分开,并且
引线区域为所述多个芯片安装区域所共用。
本公开包含与2011年10月31日在日本专利局提交的日本优先权专利申请JP2011-239444中公开的主题相关的主题,该申请的全部内容通过引用合并于此。
本领域的技术人员应该理解的是,取决于设计需求和其它因素可以发生各种修改、组合、子组合以及替换,只要它们在随附权利要求或其等同物的范围内。
Claims (12)
1.一种引线框架,包括:
设在前表面上的芯片安装区域;
包括布置在所述芯片安装区域的平面内方向上的多个凹进部和多个凸起部的引线区域;以及
布置在所述凹进部中的端子,其中
所述引线区域从所述前表面起的厚度小于所述端子从所述前表面起的厚度,
所述引线区域的后表面被密封树脂覆盖。
2.根据权利要求1所述的引线框架,其中,所述引线区域与所述芯片安装区域集成,所述引线区域与所述端子之间具有间隙,并且所述引线区域与所述端子电分离。
3.根据权利要求1所述的引线框架,其中,所述端子的截面的形状是梯形形状。
4.根据权利要求1所述的引线框架,其中
所述芯片安装区域被设在中心部分中,所述引线区域被设在所述芯片安装区域周围,并且
所述端子被布置在所述引线区域内的所有凹进部中的每一个中。
5.一种半导体器件,包括:
半导体芯片;以及
引线框架,其中
所述引线框架包括
设在前表面上的芯片安装区域,
包括布置在所述芯片安装区域的平面内方向上的多个凹进部和多个凸起部的引线区域,以及
布置在所述凹进部中的端子,并且
所述引线区域从所述前表面起的厚度小于所述端子从所述前表面起的厚度,
所述半导体芯片被安装在所述芯片安装区域上,所述半导体芯片被通过第一接线电连接到所述端子,并且被通过第二接线电连接到所述引线区域,
所述引线区域的后表面被密封树脂覆盖。
6.根据权利要求5所述的半导体器件,其中,所述半导体芯片大于所述芯片安装区域。
7.根据权利要求5所述的半导体器件,其中
所述引线框架的前表面以及所述半导体芯片被用密封树脂覆盖,并且
所述端子的后表面被从所述密封树脂暴露。
8.根据权利要求7所述的半导体器件,其中,所述半导体芯片和所述引线框架使用QFN(四方扁平无引线封装)来封装。
9.根据权利要求5所述的半导体器件,其中,所述引线区域与所述芯片安装区域集成,所述引线区域与所述端子之间具有间隙,并且所述引线区域与所述端子电分离。
10.根据权利要求5所述的半导体器件,其中,所述第一接线是信号线,所述第二接线是接地(GND)线。
11.根据权利要求5所述的半导体器件,包括在单个芯片安装区域上的多个半导体芯片。
12.根据权利要求9所述的半导体器件,其中
所述引线框架包括多个芯片安装区域,所述多个芯片安装区域被间隙分开,并且
一引线区域为所述多个芯片安装区域所共用。
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JP2011239444A JP5953703B2 (ja) | 2011-10-31 | 2011-10-31 | リードフレームおよび半導体装置 |
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JP6352009B2 (ja) * | 2013-04-16 | 2018-07-04 | ローム株式会社 | 半導体装置 |
CN103337488B (zh) * | 2013-06-05 | 2016-09-14 | 吉林华微斯帕克电气有限公司 | 一种引线框架 |
JP6413709B2 (ja) * | 2014-12-02 | 2018-10-31 | 富士電機株式会社 | 半導体装置およびその製造方法 |
US9966326B2 (en) * | 2015-03-16 | 2018-05-08 | Unisem (M) Berhad | Lead frames with wettable flanks |
JP6507779B2 (ja) * | 2015-03-26 | 2019-05-08 | セイコーエプソン株式会社 | 電気光学装置、電気光学装置の製造方法、および電子機器 |
JP6555927B2 (ja) * | 2015-05-18 | 2019-08-07 | 大口マテリアル株式会社 | 半導体素子搭載用リードフレーム及び半導体装置の製造方法 |
JP6772087B2 (ja) * | 2017-02-17 | 2020-10-21 | 新光電気工業株式会社 | リードフレーム及びその製造方法 |
US10679929B2 (en) * | 2017-07-28 | 2020-06-09 | Advanced Semiconductor Engineering Korea, Inc. | Semiconductor package device and method of manufacturing the same |
US20190221502A1 (en) * | 2018-01-17 | 2019-07-18 | Microchip Technology Incorporated | Down Bond in Semiconductor Devices |
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CN103094238A (zh) | 2013-05-08 |
US8928136B2 (en) | 2015-01-06 |
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