JP2013098332A - リードフレームおよび半導体装置 - Google Patents
リードフレームおよび半導体装置 Download PDFInfo
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Abstract
【解決手段】表面に設けられたチップ搭載領域11と、前記チップ搭載領域と同一面内方向の複数の凹凸部を含むリード領域13Aと、前記凹部に配置された端子12とを備え、前記リード領域の表面からの厚みは、前記端子の表面からの厚みよりも小さいリードフレーム10。
【選択図】図5
Description
1.実施の形態(一の半導体チップを有する例)
2.変形例1(複数の半導体チップを有する例)
3.変形例2(リードフレームを複数有する例)
図1は本開示の一実施の形態に係る半導体装置(半導体装置1)の上面構成を表したものである。図2は図1のII−II線に沿った断面構成、図3は図1のIII−III線に沿った断面構成、図4は図1のIV−IV線に沿った断面構成をそれぞれ表している。半導体装置1はQFNパッケージされたものであり、リードフレーム10の表面に設けられた半導体チップ21が封止樹脂41で覆われている。
以下、比較例1,2を用いてこれについて詳細に説明する。
図16は、変形例1に係る半導体装置(半導体装置2)の断面構成を表したものである。この半導体装置2は、一のチップ搭載領域11に半導体チップ(半導体チップ21A,21B,21C)を複数有している点で、上記実施の形態の半導体装置1と異なる。この点を除き、この半導体装置2は上記実施の形態の半導体装置1と同様の構成を有し、その作用および効果も同様である。
変形例2に係る半導体装置(半導体装置3)は、チップ搭載領域(チップ搭載領域11A,11B,11C)が複数設けられたリードフレーム50を有するものである。この点を除き、この半導体装置3は上記実施の形態の半導体装置1と同様の構成を有し、その作用および効果も同様である。
(1)表面に設けられたチップ搭載領域と、前記チップ搭載領域と同一面内方向の複数の凹凸部を含むリード領域と、前記凹部に配置された端子とを備え、前記リード領域の表面からの厚みは、前記端子の表面からの厚みよりも小さいリードフレーム。
(2)前記リード領域は前記チップ搭載領域と一体化し、前記リード領域と前記端子とは電気的に分離されている前記(1)記載のリードフレーム。
(3)前記端子の断面形状は台形状である前記(1)または(2)記載のリードフレーム。
(4)中央部に前記チップ搭載領域、前記チップ搭載領域の周囲に前記リード領域が設けられ、
前記リード領域の凹部全てに前記端子が配置されている前記(1)乃至(3)のうちいずれか1つに記載のリードフレーム。
(5)半導体チップおよびリードフレームを備え、前記リードフレームは、表面に設けられたチップ搭載領域と、前記チップ搭載領域と同一面内方向の複数の凹凸部を含むリード領域と、前記凹部に配置された端子とを有すると共に、前記リード領域の表面からの厚みが、前記端子の表面からの厚みよりも小さく、前記半導体チップは、前記チップ搭載領域に搭載されると共に、第1配線により前記端子に、第2配線により前記リード領域にそれぞれ電気的に接続されている半導体装置。
(6)前記半導体チップは前記チップ搭載領域よりも大きい前記(5)記載の半導体装置。
(7)前記半導体チップと共に前記リードフレームの表面と前記リード領域の裏面とが封止樹脂に覆われ、前記端子の裏面は前記封止樹脂から露出されている前記(5)または(6)記載の半導体装置。
(8)前記半導体チップおよび前リードフレームはQFN(Quad Flat Non-leaded Package)パッケージされている前記(5)乃至(7)のうちいずれか1つに記載の半導体装置。
(9)前記リード領域は前記チップ搭載領域と一体化し、前記リード領域と前記端子とは電気的に分離されている前記(5)乃至(8)のうちいずれか1つに記載の半導体装置。
(10)前記第1配線は信号線、前記第2配線はグラウンド(GND)線である前記(5)乃至(9)のうちいずれか1つに記載の半導体装置。
(11)一の前記チップ搭載領域に前記半導体チップを複数有する前記(5)乃至(10)のうちいずれか1つに記載の半導体装置。
(12)前記リードフレームは間隙により分離された複数のチップ搭載領域を有し、前記複数のチップ搭載領域それぞれのリード領域は共通である前記(9)または(10)記載の半導体装置。
Claims (12)
- 表面に設けられたチップ搭載領域と、
前記チップ搭載領域と同一面内方向の複数の凹凸部を含むリード領域と、
前記凹部に配置された端子とを備え、
前記リード領域の表面からの厚みは、前記端子の表面からの厚みよりも小さい
リードフレーム。 - 前記リード領域は前記チップ搭載領域と一体化し、前記リード領域と前記端子とは電気的に分離されている
請求項1記載のリードフレーム。 - 前記端子の断面形状は台形状である
請求項1記載のリードフレーム。 - 中央部に前記チップ搭載領域、前記チップ搭載領域の周囲に前記リード領域が設けられ、
前記リード領域の凹部全てに前記端子が配置されている
請求項1記載のリードフレーム。 - 半導体チップおよびリードフレームを備え、
前記リードフレームは、
表面に設けられたチップ搭載領域と、
前記チップ搭載領域と同一面内方向の複数の凹凸部を含むリード領域と、
前記凹部に配置された端子とを有すると共に、前記リード領域の表面からの厚みが、前記端子の表面からの厚みよりも小さく、
前記半導体チップは、前記チップ搭載領域に搭載されると共に、第1配線により前記端子に、第2配線により前記リード領域にそれぞれ電気的に接続されている
半導体装置。 - 前記半導体チップは前記チップ搭載領域よりも大きい
請求項5記載の半導体装置。 - 前記半導体チップと共に前記リードフレームの表面と前記リード領域の裏面とが封止樹脂に覆われ、
前記端子の裏面は前記封止樹脂から露出されている
請求項5記載の半導体装置。 - 前記半導体チップおよび前リードフレームはQFN(Quad Flat Non-leaded Package)パッケージされている
請求項7記載の半導体装置。 - 前記リード領域は前記チップ搭載領域と一体化し、前記リード領域と前記端子とは電気的に分離されている
請求項5記載の半導体装置。 - 前記第1配線は信号線、前記第2配線はグラウンド(GND)線である
請求項5記載の半導体装置。 - 一の前記チップ搭載領域に前記半導体チップを複数有する
請求項5記載の半導体装置。 - 前記リードフレームは間隙により分離された複数のチップ搭載領域を有し、
前記複数のチップ搭載領域それぞれのリード領域は共通である
請求項9記載の半導体装置。
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JP6352009B2 (ja) * | 2013-04-16 | 2018-07-04 | ローム株式会社 | 半導体装置 |
CN103337488B (zh) * | 2013-06-05 | 2016-09-14 | 吉林华微斯帕克电气有限公司 | 一种引线框架 |
JP6413709B2 (ja) * | 2014-12-02 | 2018-10-31 | 富士電機株式会社 | 半導体装置およびその製造方法 |
US9966326B2 (en) * | 2015-03-16 | 2018-05-08 | Unisem (M) Berhad | Lead frames with wettable flanks |
JP6507779B2 (ja) * | 2015-03-26 | 2019-05-08 | セイコーエプソン株式会社 | 電気光学装置、電気光学装置の製造方法、および電子機器 |
JP6555927B2 (ja) * | 2015-05-18 | 2019-08-07 | 大口マテリアル株式会社 | 半導体素子搭載用リードフレーム及び半導体装置の製造方法 |
JP6772087B2 (ja) * | 2017-02-17 | 2020-10-21 | 新光電気工業株式会社 | リードフレーム及びその製造方法 |
US10679929B2 (en) * | 2017-07-28 | 2020-06-09 | Advanced Semiconductor Engineering Korea, Inc. | Semiconductor package device and method of manufacturing the same |
US20190221502A1 (en) * | 2018-01-17 | 2019-07-18 | Microchip Technology Incorporated | Down Bond in Semiconductor Devices |
CN110828442A (zh) * | 2019-11-04 | 2020-02-21 | 弘凯光电(深圳)有限公司 | 封装结构及其制作方法 |
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