CN101308832B - 用于无引线封装的引线框、其封装结构及其制造方法 - Google Patents

用于无引线封装的引线框、其封装结构及其制造方法 Download PDF

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CN101308832B
CN101308832B CN2007101070355A CN200710107035A CN101308832B CN 101308832 B CN101308832 B CN 101308832B CN 2007101070355 A CN2007101070355 A CN 2007101070355A CN 200710107035 A CN200710107035 A CN 200710107035A CN 101308832 B CN101308832 B CN 101308832B
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林峻莹
沈更新
潘玉堂
周世文
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Chipmos Technologies Inc
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Abstract

本发明揭示一种用于无引线封装的引线框，其包含多个封装单元及一胶带。各所述封装单元包括一具有多个通孔的芯片座及分别设于所述多个通孔中的多个接脚。所述胶带粘贴于所述多个封装单元的表面，并固定所述芯片座及所述多个接脚。

Description

用于无引线封装的引线框、其封装结构及其制造方法
技术领域
本发明涉及一种用于无引线封装的引线框、其封装结构及其制造方法，尤其涉及四方扁平无引线封装(Quad Flat Non-leaded Package；QFN)的结构、所使用的引线框及制造方法。
背景技术
为顺应消费性电子产品强调轻薄短小的趋势，QFN封装目前已经超越传统的引线封装，用来取代成本较高的晶片级芯片尺寸封装(wafer level CSP)，而芯片尺寸封装(CSP)虽然将封装外形缩减成芯片大小，却必须使用间距很近的锡球阵列作为元件接脚，使得产品制造难度提高。相对QFN封装不但体积小、成本低、生产合格率高，还能为高速和电源管理电路提供更好的共面性以及散热能力等优点，此外，QFN封装不必从两侧引出接脚，因此电性能优于引线封装必须从侧面引出多只接脚的传统封装。举例而言，SO系列或QFP等引线封装都必须从侧面引出多只接脚，这些接脚有时就像天线一样会给高频应用带来许多噪声。
除此之外，QFN封装的外露式引线框焊垫(lead frame pad)还能做为直接散热路径，使封装拥有更好的散热能力。导热垫(thermal pad)通常是直接焊接在电路板上，电路板内的导热孔(thermal via)则会将过多热量传至铜箔接地面，而不需要另外安装散热片。
图1是常规QFN封装结构的剖面示意图。QFN封装元件80包含引线框81、电路小片82、粘着剂83、多个金属引线84及一封胶材料85，其中电路小片82通过粘着剂83而固定于引线框81的芯片固定垫811上，另外，多个金属引线84分别电连接电路小片82及引线框81的多个接脚812。封胶材料85覆盖于电路小片82、金属引线84及引线框81上，但芯片固定垫811及接脚812的下表面需要露出于封胶材料85外。接脚812的露出下表面部分作为表面粘着时的外部接点，另外，芯片固定垫811的露出下表面部分可直接将热逸散至外界，因此可完全取代常规封装技术中增加外露散热片的功效。然而所述芯片固定垫811位于接脚812的中央，且必须和环设的各接脚812保持适当的距离，因此面积受到限制。由于散热效率和面积密切相关，如果能增加芯片固定垫811的露出下表面的面积则有助于解决多功能电路小片日益严重的散热问题。
发明内容
本发明的目的在于提供一种用于无引线封装的引线框、其封装结构及其制造方法，通过改变引线框中芯片座及接脚的布局方式而增加封装结构的散热效率。
本发明的另一目的在于提供一种接脚稳固的无引线封装结构，由于接脚四个端面均由封胶材料固定并保护，而不易受到外力碰撞而产生缺陷。
本发明的再一目的在于提供一种接脚稳固的无引线封装结构，由于各接脚具有凹陷部以及凸起部，增加与封胶材料的结合面积，因此可以降低封胶材料剥离的问题，而提升工艺合格率。
为达到上述目的，本发明揭示一种无引线封装的引线框，其包含多个封装单元及一胶带。各所述封装单元包括一具有多个通孔的芯片座，及分别设于所述多个通孔中的多个接脚。所述胶带粘贴于所述多个封装单元的表面，并固定所述芯片座及所述多个接脚。
本发明另外揭示一种无引线封装的封装结构，其包含一引线框、一电路小片及多个金属引线。所述引线框具有多个通孔的芯片座，及分别设于所述多个通孔中的多个接脚。电路小片固定于所述芯片座，并通过所述多个金属引线电连接至所述电路小片。
本发明另外揭示一种无引线封装结构的制造方法，其先提供表面披覆胶带的金属板材。然后图案化所述金属板材以产生多个封装单元，其中各所述封装单元包括一具有多个通孔的芯片座及分别设于所述多个通孔中的多个接脚。再将多个电路小片固定于各所述芯片座，并在各所述电路小片、各所述封装单元及所述多个金属引线上覆盖封胶材料。
附图说明
图1是常规QFN封装结构的剖面示意图；
图2(a)～2(e)是本发明无引线封装结构的各制造步骤示意图；
图3是本发明无引线封装元件的俯视图；
图4是本发明无引线封装的引线框的俯视图；以及
图5(a)～5(c)是本发明另一实施例无引线封装结构的制造步骤示意图。
具体实施方式
图2(a)～2(e)是本发明无引线封装结构的各制造步骤示意图。先提供表面披覆胶带12的金属板材11，所述金属板材11可以选自铜、铝、铜铝合金、铝合金及其混合物所组成的群组。如图2(b)所示，在金属板材11的上表面以冲压方式形成多个凹陷部132，相对于金属板材11与胶带12粘合的下表面就会产生多个凸起部131。然后利用光刻法将金属板材11形成多个相连接的芯片座14及多个分离的接脚13，所述多个接脚13分别设于各芯片座14周围的多个通孔141内，如图2(c)所示。各芯片座14及周围的接脚13视为引线框18上一个封装单元181。
如图2(d)所示，再将电路小片15固定于各芯片座14中央的芯片固定区142(参看图3)，并以焊线技术将多个金属引线17由电路小片15分别连接至周围的各接脚13，优选地，金属引线17连接到凹陷部132之外的其它接脚区域。为能保护电路小片15及金属引线17不受外力及环境的影响，还在各电路小片15、各封装单元181及多个金属引线17上覆盖封胶材料16，如图2(d)所示。在封胶材料16固化后可将胶带12去除，最后利用切割技术沿各封装单元181的边界将各无引线封装元件20分离，如图2(e)所示。
图3是本发明无引线封装元件的俯视图。电路小片15固定于各芯片座14中央的芯片固定区142，另外多个独立的接脚13分别设于芯片座14周围的多个通孔141内。与图1中QFN封装体80相比较，很显然本发明的芯片座14延伸至无引线封装元件20的四个周界。除了通孔141部分外，整个芯片座14的面积都可以进行散热，但常规QFN封装体80的芯片固定垫811的面积约与图3中芯片固定区142的面积相等，因此两者的散热效率因为芯片座14的面积差异而有显著不同。另外，本发明的接脚13的四个端面均由封胶材料16固定并保护，所以不易受到外力碰撞而产生缺陷。
图4是本发明无引线封装的引线框的俯视图。为顺应产量的需求，可将引线框18上的多个封装单元181呈M×N的阵列状排列。例如图4中两列封装单元181并排，当然也可更多列并排以增加压模工艺的单位时间产出(unit per hour；UPH)。
无引线封装元件20中各接脚13的凸起部131可增加与焊锡的接触面积，有助于强化表面粘着的可焊接性(solderability)，此外各接脚的凹陷部132增加与封胶材料16的结合面积，因此可以降低封胶材料16剥离的问题，从而提升工艺良率。如图5(a)所示，先在金属板材11表面形成多个凹陷部132′，及相对于凹陷部132′的另一表面就同时产生凸起部131′。再将金属板材11具有多个凹陷部132′的表面与胶带12密合，如图5(b)所示。接着可采用前述图2(c)至2(d)步骤中相同手段完成大部分工艺，优选的实施例，所述金属引线17连接到凸起部131′之外的其它接脚区域。最后利用切割技术沿各封装单元181的边界将各无引线封装元件20′分离，如图5(c)所示。无引线封装元件20′的中各接脚13的凹陷部132′可增加与焊锡的接触面积，同样有助于强化表面粘着的可焊接性，此外凸起部131′增加与封胶材料16的结合面积，因此可以降低封胶材料16剥离的问题。
本发明的技术内容及技术特点已揭示如上，然而所属领域的技术人员仍可能基于本发明的教示及揭示而做种种不脱离本发明精神的替换及修改。因此，本发明的保护范围应不限于实施例所揭示的内容，而应包括各种不脱离本发明的替换及修改，并为所附的权利要求书所涵盖。

Claims (16)

1.一种用于无引线封装的引线框，其特征在于包含：
多个封装单元，各所述封装单元包括：
芯片座，其具有多个通孔；
多个接脚，所述多个接脚的每一个分别设于所述多个通孔的每一通孔中，且所述多个接脚的所述每一个与其所在的所述通孔的孔壁是相互分离；以及
胶带，其固定所述多个封装单元。
2.根据权利要求1所述的用于无引线封装的引线框，其特征在于所述芯片座中间有芯片固定区，且各所述封装单元中所述多个通孔配置于所述芯片固定区的四周。
3.根据权利要求1所述的用于无引线封装的引线框，其特征在于各所述接脚具有凸出部，所述凸出部位于所述接脚上邻接于所述胶带的表面。
4.根据权利要求3所述的用于无引线封装的引线框，其特征在于各所述接脚具有凹陷部，所述凹陷部位于所述接脚上相对于所述凸出部的表面。
5.根据权利要求1所述的用于无引线封装的引线框，其特征在于各所述接脚具有凹陷部，所述凹陷部位于所述接脚上邻接于所述胶带的表面。
6.根据权利要求5所述的用于无引线封装的引线框，其特征在于各所述接脚具有凸出部，所述凸出部位于所述接脚上相对于所述凹陷部的表面。
7.根据权利要求1所述的用于无引线封装的引线框，其特征在于各所述通孔与设于所述通孔中的所述接脚之间有间隙。
8.一种无引线封装结构，其特征在于包含：
引线框，其包括：
芯片座，其具有多个通孔；及
多个接脚，所述多个接脚的每一个分别设于所述多个通孔的每一通孔中，且所述多个接脚的所述每一个与其所在的所述通孔的孔壁是相互分离；
电路小片，其固定于所述芯片座；以及
多个金属引线，其电连接所述电路小片及所述多个接脚。
9.根据权利要求8所述的无引线封装结构，其特征在于所述电路小片固定于所述芯片座中间的芯片固定区。
10.根据权利要求9所述的无引线封装结构，其特征在于所述多个通孔配置于所述芯片固定区的四周。
11.根据权利要求8所述的无引线封装结构，其特征在于另外包含覆盖于所述电路小片、所述引线框及所述多个金属引线的封胶材料，其中所述芯片座及所述多个接脚相对于所述电路小片的下表面未覆盖所述封胶材料。
12.根据权利要求8所述的无引线封装结构，其特征在于所述多个接脚相对于所述电路小片的下表面分别具有凸出部或凹陷部。
13.一种无引线封装结构的制造方法，其特征在于包含下列步骤：
提供表面披覆胶带的金属板材；
图案化所述金属板材以产生多个封装单元，其特征在于各所述封装单元包括具有多个通孔的芯片座及分别设于所述多个通孔中的多个接脚；
将多个电路小片固定于各所述芯片座；
将各所述电路小片电连接至相邻所述多个接脚；以及
在各所述电路小片、各所述封装单元及所述多个金属引线上覆盖封胶材料。
14.根据权利要求13所述的无引线封装结构的制造方法，其特征在于另外包含在所述金属板材与所述胶带贴合的表面形成多个凸出部的步骤，其中所述凸出部位于所述多个接脚的位置。
15.根据权利要求13所述的无引线封装结构的制造方法，其特征在于另外包含在披覆所述胶带之前在所述金属板材上形成多个凹陷部的步骤，其特征在于所述金属板材具有所述凹陷部的表面贴合于所述胶带且所述凹陷部位于所述多个接脚的位置。
16.根据权利要求13所述的无引线封装结构的制造方法，其特征在于另外包含于覆盖所述封胶材料后移除所述胶带的步骤。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6400004B1 (en) * 2000-08-17 2002-06-04 Advanced Semiconductor Engineering, Inc. Leadless semiconductor package
CN1914719A (zh) * 2004-01-07 2007-02-14 飞思卡尔半导体公司 倒装晶片四方扁平无引脚封装及其方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开2003-347494A 2003.12.15

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