JP5879367B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
JP5879367B2
JP5879367B2 JP2013551167A JP2013551167A JP5879367B2 JP 5879367 B2 JP5879367 B2 JP 5879367B2 JP 2013551167 A JP2013551167 A JP 2013551167A JP 2013551167 A JP2013551167 A JP 2013551167A JP 5879367 B2 JP5879367 B2 JP 5879367B2
Authority
JP
Japan
Prior art keywords
delay
circuit
delay amount
adjustment circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2013551167A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO2013099035A1 (ja
Inventor
飯島　正章
正章 飯島
出口　光宏
光宏 出口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of JPWO2013099035A1 publication Critical patent/JPWO2013099035A1/ja
Application granted granted Critical
Publication of JP5879367B2 publication Critical patent/JP5879367B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/159—Applications of delay lines not covered by the preceding subgroups

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Pulse Circuits (AREA)
JP2013551167A 2011-12-29 2011-12-29 半導体装置 Expired - Fee Related JP5879367B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2011/080532 WO2013099035A1 (ja) 2011-12-29 2011-12-29 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2016015494A Division JP6058835B2 (ja) 2016-01-29 2016-01-29 半導体装置

Publications (2)

Publication Number Publication Date
JPWO2013099035A1 JPWO2013099035A1 (ja) 2015-04-30
JP5879367B2 true JP5879367B2 (ja) 2016-03-08

Family

ID=48696593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013551167A Expired - Fee Related JP5879367B2 (ja) 2011-12-29 2011-12-29 半導体装置

Country Status (6)

Country Link
US (2) US9536579B2 (ko)
JP (1) JP5879367B2 (ko)
KR (2) KR101837239B1 (ko)
CN (2) CN104012002B (ko)
TW (2) TWI575879B (ko)
WO (1) WO2013099035A1 (ko)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013099035A1 (ja) * 2011-12-29 2013-07-04 ルネサスエレクトロニクス株式会社 半導体装置
US9209961B1 (en) * 2014-09-29 2015-12-08 Apple Inc. Method and apparatus for delay compensation in data transmission
CN104375426B (zh) * 2014-10-15 2017-05-10 成都振芯科技股份有限公司 一种片内信号间的相位信息处理和延迟控制电路
CN104280613B (zh) * 2014-10-15 2017-03-08 成都振芯科技股份有限公司 一种片内信号间的相位检测与同步电路及其同步方法
US10331526B2 (en) * 2015-07-31 2019-06-25 Qualcomm Incorporated Systems, methods, and apparatus for frequency reset of a memory
JP2017073700A (ja) * 2015-10-08 2017-04-13 富士通株式会社 クロック再生回路、光モジュール及びクロック再生方法
JP6906911B2 (ja) * 2016-08-18 2021-07-21 シナプティクス・ジャパン合同会社 半導体装置、データ伝送システム及び半導体装置の動作方法
US11962313B2 (en) * 2016-12-23 2024-04-16 Advanced Micro Devices, Inc. Adaptive DCO VF curve slope control
US9990973B1 (en) * 2017-02-17 2018-06-05 Apple Inc. Systems and methods using neighboring sample points in memory subsystem calibration
KR102365110B1 (ko) * 2017-09-13 2022-02-18 삼성전자주식회사 복수의 메모리 장치들에 대한 트레이닝 동작을 지원하는 버퍼 장치를 포함하는 메모리 모듈 및 이를 포함하는 메모리 시스템
KR20190068301A (ko) * 2017-12-08 2019-06-18 삼성전자주식회사 지연 고정 루프를 포함하는 메모리 장치 및 메모리 장치의 동작 방법
KR102499037B1 (ko) 2018-01-10 2023-02-13 삼성전자주식회사 메모리 장치 및 이를 포함하는 메모리 시스템
US10573272B2 (en) * 2018-06-28 2020-02-25 Intel Corporation Device, method and system for providing a delayed clock signal to a circuit for latching data
KR20200008842A (ko) * 2018-07-17 2020-01-29 삼성전자주식회사 반도체 메모리 장치 및 반도체 메모리 장치의 동작 방법
TWI685200B (zh) 2018-08-10 2020-02-11 華邦電子股份有限公司 同步鏡延遲電路和同步鏡延遲操作方法
KR102570959B1 (ko) * 2018-09-18 2023-08-28 에스케이하이닉스 주식회사 집적 회로
US10643685B1 (en) * 2018-11-01 2020-05-05 Realtek Semiconductor Corporation Control circuit, sampling circuit for synchronous dynamic random-access memory, method of reading procedure and calibration thereof
CN110531712B (zh) * 2019-02-18 2021-07-13 北京北方华创微电子装备有限公司 用于半导体设备的上下位机信息同步系统及方法
JP2021043536A (ja) * 2019-09-06 2021-03-18 キオクシア株式会社 半導体装置、及び半導体装置の制御方法
TWI730523B (zh) * 2019-12-03 2021-06-11 智成電子股份有限公司 自我校正式系統單晶片
WO2021102480A2 (en) * 2020-03-10 2021-05-27 Zeku, Inc. Delay-line based transceiver calibration
CN111641404B (zh) * 2020-05-12 2022-06-03 成都华微电子科技股份有限公司 时钟展频方法和时钟展频电路
CN111539182B (zh) * 2020-07-08 2020-10-09 成都奥卡思微电科技有限公司 一种对组合逻辑电路等价验证的分级方法
US11726721B2 (en) * 2020-09-09 2023-08-15 Samsung Electronics Co., Ltd. Memory device for adjusting delay on data clock path, memory system including the memory device, and operating method of the memory system
JP2022146532A (ja) * 2021-03-22 2022-10-05 キオクシア株式会社 メモリシステム及び遅延制御方法
WO2024009384A1 (ja) * 2022-07-05 2024-01-11 ウルトラメモリ株式会社 半導体装置

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5373508A (en) * 1992-07-31 1994-12-13 Intel Corporation Detecting valid data from a twisted pair medium
GB2356090B (en) * 1996-09-17 2001-06-20 Fujitsu Ltd Clock synchronisation with timing adjust mode
JP2000311028A (ja) 1999-04-28 2000-11-07 Hitachi Ltd 位相制御回路、半導体装置及び半導体メモリ
JP3702126B2 (ja) 1999-05-13 2005-10-05 株式会社東芝 ディジタルｐｌｌ装置及びそのディレイラインの制御方法
US6671211B2 (en) * 2001-04-17 2003-12-30 International Business Machines Corporation Data strobe gating for source synchronous communications interface
US6798259B2 (en) * 2001-08-03 2004-09-28 Micron Technology, Inc. System and method to improve the efficiency of synchronous mirror delays and delay locked loops
TW563132B (en) * 2001-10-09 2003-11-21 Via Tech Inc Common DRAM controller supports double-data-rate and quad-data-rate memory
JP2005010958A (ja) * 2003-06-17 2005-01-13 Matsushita Electric Ind Co Ltd 半導体装置
JP4450586B2 (ja) 2003-09-03 2010-04-14 株式会社ルネサステクノロジ 半導体集積回路
US6975557B2 (en) * 2003-10-02 2005-12-13 Broadcom Corporation Phase controlled high speed interfaces
US7126399B1 (en) * 2004-05-27 2006-10-24 Altera Corporation Memory interface phase-shift circuitry to support multiple frequency ranges
JP2006099244A (ja) * 2004-09-28 2006-04-13 Seiko Epson Corp データ信号取得装置
US7119596B2 (en) * 2004-12-22 2006-10-10 Lsi Logic Corporation Wide-range programmable delay line
JP5005928B2 (ja) * 2006-02-21 2012-08-22 株式会社リコー インタフェース回路及びそのインタフェース回路を備えた記憶制御装置
TWI302320B (en) * 2006-09-07 2008-10-21 Nanya Technology Corp Phase detection method, memory control method, and related device
US7403056B2 (en) * 2006-11-22 2008-07-22 Via Technologies, Inc. Delay apparatus and method thereof
JP2008311999A (ja) * 2007-06-15 2008-12-25 Panasonic Corp 遅延調整回路、およびメモリコントローラ
JP2009021706A (ja) 2007-07-10 2009-01-29 Elpida Memory Inc Ｄｌｌ回路及びこれを用いた半導体記憶装置、並びに、データ処理システム
CN101500094B (zh) * 2008-01-29 2011-06-29 华晶科技股份有限公司 标准移动影像架构规范下用于调整相位的延迟装置
JP2009212735A (ja) 2008-03-04 2009-09-17 Fujitsu Microelectronics Ltd データ位相調整回路及びデータ位相調整方法
US20110026385A1 (en) * 2008-06-12 2011-02-03 Nobuyuki Nakai Semiconductor storage device, semiconductor device and optical disc reproducing device
JP2011188042A (ja) 2010-03-05 2011-09-22 Nec Corp デジタル信号処理回路、デジタル信号処理方法、及び、プログラム
US8453096B2 (en) * 2011-01-28 2013-05-28 Lsi Corporation Non-linear common coarse delay system and method for delaying data strobe
WO2013099035A1 (ja) * 2011-12-29 2013-07-04 ルネサスエレクトロニクス株式会社 半導体装置

Also Published As

Publication number Publication date
TWI617137B (zh) 2018-03-01
TW201714405A (en) 2017-04-16
WO2013099035A1 (ja) 2013-07-04
US9536579B2 (en) 2017-01-03
KR20140117385A (ko) 2014-10-07
JPWO2013099035A1 (ja) 2015-04-30
KR101837239B1 (ko) 2018-03-09
US9761299B2 (en) 2017-09-12
KR101933362B1 (ko) 2018-12-27
KR20180026560A (ko) 2018-03-12
US20150029800A1 (en) 2015-01-29
CN104012002A (zh) 2014-08-27
CN104012002B (zh) 2017-04-12
TW201342807A (zh) 2013-10-16
US20170076777A1 (en) 2017-03-16
CN106936421A (zh) 2017-07-07
CN106936421B (zh) 2020-09-01
TWI575879B (zh) 2017-03-21

Similar Documents

Publication Publication Date Title
JP5879367B2 (ja) 半導体装置
US6819151B2 (en) Method and circuit for adjusting the timing of output data based on an operational mode of output drivers
US7111185B2 (en) Synchronization device with delay line control circuit to control amount of delay added to input signal and tuning elements to receive signal form delay circuit
US7501866B2 (en) Delay locked loop circuit
US7139345B2 (en) Method and circuit for adjusting the timing of output data based on the current and future states of the output data
US7423461B2 (en) Phase synchronous circuit
JP2010088108A (ja) Ｄｌｌ回路及びその制御方法
JP2002124873A (ja) 半導体装置
US8643416B2 (en) Semiconductor device including a delay locked loop circuit
US10403340B2 (en) Techniques for command synchronization in a memory device
JP2013069360A (ja) 半導体装置及びデータ処理システム
US20020021152A1 (en) DLL circuit and method of generating timing signals
KR100486922B1 (ko) 반도체 기억 장치
US20210313974A1 (en) Apparatuses and methods for adjusting a phase mixer circuit
JP6058835B2 (ja) 半導体装置
US11626867B2 (en) Variable delay circuit and semiconductor integrated circuit
JP2014212365A (ja) 半導体装置

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150929

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20151125

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20160105

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20160201

R150 Certificate of patent or registration of utility model

Ref document number: 5879367

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees