JP5869057B2 - 半導体記憶装置 - Google Patents
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- JP5869057B2 JP5869057B2 JP2014133580A JP2014133580A JP5869057B2 JP 5869057 B2 JP5869057 B2 JP 5869057B2 JP 2014133580 A JP2014133580 A JP 2014133580A JP 2014133580 A JP2014133580 A JP 2014133580A JP 5869057 B2 JP5869057 B2 JP 5869057B2
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- 239000004065 semiconductor Substances 0.000 title claims description 14
- 125000006850 spacer group Chemical group 0.000 claims description 28
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- 238000009792 diffusion process Methods 0.000 description 15
- 238000000059 patterning Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000004380 ashing Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000009191 jumping Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/75—Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
110:メモリアレイ
120:入出力バッファ
130:アドレスレジスタ
140:データレジスタ
150:コントローラ
160:ワード線選択回路
170:ページバッファ/センス回路
180:列選択回路
200:被加工層
210:ハードマスク
220:下地膜
PR:レジストパターン
Claims (9)
- 複数のNAND型のストリングが形成されたメモリアレイを有し、
1つのストリングは、直列に接続された複数のメモリセルと、前記複数のメモリセルの一方の端部に接続されたビット線選択トランジスタと、前記複数のメモリセルの他方の端部に接続されたソース線選択トランジスタとを有し、
複数のストリングの行方向の複数のメモリセルのゲートが各ワード線に共通に接続され、
複数のストリングの行方向の複数のソース線選択トランジスタのゲートが第1の選択ゲート線に共通に接続され、
複数のストリングの行方向の複数のビット線選択トランジスタのゲートが第2の選択ゲート線に共通に接続され、
ソース線選択トランジスタのゲートとこれに隣接するワード線のメモリセルのゲートとの第1の間隔は、ビット線選択トランジスタのゲートとこれに隣接するワード線のメモリセルのゲートとの第2の間隔よりも大きく、
プログラム動作時に、第2の選択ゲート線に隣接するワード線が選択されたページであるか否かを判定し、選択されたページであると判定された場合に、ビット線選択トランジスタを導通させるために第2の選択ゲート線に第1の電圧を印加し、選択されたページでないと判定された場合に、ビット線選択トランジスタを導通させるために第2の選択ゲート線に第2の電圧を印加し、第1の電圧は第2の電圧よりも大きい、半導体記憶装置。 - 前記第1の間隔は、ストリングを構成するメモリセルのゲート間の第3の間隔よりも大きい、請求項1に記載の半導体記憶装置。
- 前記第1の間隔は、第2の間隔の2倍であり、前記第2の間隔と前記第3の間隔は等しい、請求項1または2に記載の半導体記憶装置。
- プログラム動作時に、第1の選択ゲート線には、ソース線選択トランジスタを非導通にする電圧が印加される、請求項1ないし3いずれか1つに記載の半導体記憶装置。
- メモリアレイのブロック内に配置される複数のストリングのレイアウトは非対称である、請求項1ないし4いずれか1つに記載の半導体記憶装置。
- 直列に接続された複数のメモリセルと、前記複数のメモリセルの一方の端部に接続されたビット線選択トランジスタと、前記複数のメモリセルの他方の端部に接続されたソース線選択トランジスタとを有するストリングが形成されたメモリアレイを有する、フラッシュメモリのプログラム方法であって、
プログラム動作時に、第2の選択ゲート線に隣接するワード線が選択されたページであるか否かを判定し、選択されたページであると判定された場合に、ビット線選択トランジスタを導通させるために第2の選択ゲート線に第1の電圧を印加し、選択されたページでないと判定された場合に、ビット線選択トランジスタを導通させるために第2の選択ゲート線に第2の電圧を印加し、第1の電圧は第2の電圧よりも大きい、プログラム方法。 - NAND型のメモリアレイを有する半導体記憶装置の製造方法であって、
メモリセルのゲートを構成する被加工膜上にハードマスクを形成する工程と、
前記ハードマスク上に複数のレジストパターンを形成する工程と、
前記複数のレジストパターンの側壁にスペーサ層を形成する工程と、
前記複数のレジストパターンおよびスペーサ層をマスクに前記ハードマスクをエッチングする工程と、
前記複数のレジストパターンおよびスペーサ層を除去した後、別の複数のレジストパターンを前記ハードマスク上に形成する工程と、
前記別の複数のレジストパターンの側壁にスペーサ層を形成する工程と、
前記別の複数のレジストパターンを除去する工程と、
残存したスペーサ層をマスクに用いて前記ハードマスクをエッチングする工程と、
前記ハードマスクをマスクに用いて前記被加工膜をエッチングしメモリセルのゲートを形成する工程とを含み、
メモリアレイは、ソース線選択トランジスタのゲートとこれに隣接するメモリセルのゲートとの第1の間隔がビット線選択トランジスタのゲートとこれに隣接するメモリセルのゲートとの第2の間隔よりも大きい非対称構造を有する、製造方法。 - NAND型のメモリアレイを有する半導体記憶装置の製造方法であって、
メモリセルのゲートを構成する被加工膜上に複数のレジストパターンを形成する工程と、
前記複数のレジストパターンを含む全面に絶縁層を形成する工程と、
前記絶縁層上にレジスト層を形成する工程と、
前記絶縁層の両側の側壁に前記レジスト層が残存するように前記レジスト層をエッチングする工程と、
前記絶縁層を除去する工程と、
前記レジストパターンおよび残存したレジスト層をマスクに用いて前記被加工膜をエッチングし、複数のゲートを形成する工程と、
前記レジストパターンおよび残存したレジスト層を除去する工程とを有し、
メモリアレイは、ソース線選択トランジスタのゲートとこれに隣接するメモリセルのゲートとの第1の間隔がビット線選択トランジスタのゲートとこれに隣接するメモリセルのゲートとの第2の間隔よりも大きい非対称構造を有する、製造方法。 - 製造方法はさらに、複数のゲートの一部を除去する工程を含む、請求項7または8いずれか1つに記載の製造方法。
Priority Applications (5)
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JP2014133580A JP5869057B2 (ja) | 2014-06-30 | 2014-06-30 | 半導体記憶装置 |
KR1020140195284A KR101694389B1 (ko) | 2014-06-30 | 2014-12-31 | 반도체 메모리 장치 및 그 제조방법 |
US14/621,344 US9449697B2 (en) | 2014-06-30 | 2015-02-12 | Semiconductor memory device and manufacturing method thereof |
US15/237,640 US9768184B2 (en) | 2014-06-30 | 2016-08-16 | Manufacturing method of semiconductor memory device |
US15/672,298 US9935116B2 (en) | 2014-06-30 | 2017-08-09 | Manufacturing method of semiconductor memory device |
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JP2014133580A JP5869057B2 (ja) | 2014-06-30 | 2014-06-30 | 半導体記憶装置 |
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JP2016012661A JP2016012661A (ja) | 2016-01-21 |
JP5869057B2 true JP5869057B2 (ja) | 2016-02-24 |
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JP5869057B2 (ja) * | 2014-06-30 | 2016-02-24 | ウィンボンド エレクトロニクス コーポレーション | 半導体記憶装置 |
US11551761B1 (en) * | 2021-08-30 | 2023-01-10 | Sandisk Technologies Llc | Non-volatile memory with program skip for edge word line |
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