JP5845143B2 - エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ - Google Patents

エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ Download PDF

Info

Publication number
JP5845143B2
JP5845143B2 JP2012146636A JP2012146636A JP5845143B2 JP 5845143 B2 JP5845143 B2 JP 5845143B2 JP 2012146636 A JP2012146636 A JP 2012146636A JP 2012146636 A JP2012146636 A JP 2012146636A JP 5845143 B2 JP5845143 B2 JP 5845143B2
Authority
JP
Japan
Prior art keywords
silicon wafer
epitaxial
manufacturing
single crystal
crystal ingot
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2012146636A
Other languages
English (en)
Japanese (ja)
Other versions
JP2014011293A (ja
JP2014011293A5 (https=
Inventor
正 川島
正 川島
直哉 野中
直哉 野中
正行 品川
正行 品川
剛 上園
剛 上園
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Techxiv Corp
Original Assignee
Sumco Techxiv Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Techxiv Corp filed Critical Sumco Techxiv Corp
Priority to JP2012146636A priority Critical patent/JP5845143B2/ja
Priority to US13/925,267 priority patent/US9425264B2/en
Priority to KR1020130072869A priority patent/KR101473784B1/ko
Publication of JP2014011293A publication Critical patent/JP2014011293A/ja
Publication of JP2014011293A5 publication Critical patent/JP2014011293A5/ja
Priority to US14/850,194 priority patent/US9755022B2/en
Application granted granted Critical
Publication of JP5845143B2 publication Critical patent/JP5845143B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3438—Doping during depositing
    • H10P14/3441—Conductivity type
    • H10P14/3442—N-type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/36—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done before the formation of the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/40—Treatments of semiconductor bodies to modify their internal properties, e.g. to produce internal imperfections
    • H10P95/402—Treatments of semiconductor bodies to modify their internal properties, e.g. to produce internal imperfections of silicon bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
JP2012146636A 2012-06-29 2012-06-29 エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ Active JP5845143B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2012146636A JP5845143B2 (ja) 2012-06-29 2012-06-29 エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ
US13/925,267 US9425264B2 (en) 2012-06-29 2013-06-24 Method for growing an epitaxial film on a phosphorous-doped silicon wafer
KR1020130072869A KR101473784B1 (ko) 2012-06-29 2013-06-25 에피택셜 실리콘 웨이퍼의 제조 방법 및, 에피택셜 실리콘 웨이퍼
US14/850,194 US9755022B2 (en) 2012-06-29 2015-09-10 Epitaxial silicon wafer having reduced stacking faults

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012146636A JP5845143B2 (ja) 2012-06-29 2012-06-29 エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ

Publications (3)

Publication Number Publication Date
JP2014011293A JP2014011293A (ja) 2014-01-20
JP2014011293A5 JP2014011293A5 (https=) 2015-04-23
JP5845143B2 true JP5845143B2 (ja) 2016-01-20

Family

ID=49777243

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012146636A Active JP5845143B2 (ja) 2012-06-29 2012-06-29 エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ

Country Status (3)

Country Link
US (2) US9425264B2 (https=)
JP (1) JP5845143B2 (https=)
KR (1) KR101473784B1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12046469B2 (en) 2020-02-19 2024-07-23 Globalwafers Japan Co., Ltd. Manufacturing method for semiconductor silicon wafer
US12308228B2 (en) 2020-02-19 2025-05-20 Globalwafers Japan Co., Ltd. Manufacturing method for semiconductor silicon wafer

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10233562B2 (en) 2013-04-24 2019-03-19 Sumco Techxiv Corporation Method for producing single crystal, and method for producing silicon wafer
CN106797207B (zh) * 2014-12-17 2021-04-20 株式会社村田制作所 压电振子以及压电振动装置
JP6477210B2 (ja) 2015-04-30 2019-03-06 株式会社Sumco エピタキシャルシリコンウェーハの製造方法
JP6369388B2 (ja) * 2015-05-13 2018-08-08 信越半導体株式会社 シリコン単結晶基板の評価方法
JP6432879B2 (ja) * 2015-11-13 2018-12-05 信越半導体株式会社 エピタキシャルウェーハの製造方法
JP6447960B2 (ja) * 2016-04-01 2019-01-09 信越半導体株式会社 シリコンエピタキシャルウェーハの製造方法
JP6372709B2 (ja) * 2016-04-20 2018-08-15 信越半導体株式会社 エピタキシャルウェーハの製造方法
JP6598140B2 (ja) * 2016-05-19 2019-10-30 信越半導体株式会社 エピタキシャルウェーハの製造方法
JP6973475B2 (ja) 2017-04-06 2021-12-01 株式会社Sumco エピタキシャルシリコンウェーハの製造方法およびエピタキシャルシリコンウェーハ
WO2018198797A1 (ja) 2017-04-25 2018-11-01 株式会社Sumco シリコン単結晶の製造方法、エピタキシャルシリコンウェーハの製造方法、シリコン単結晶、および、エピタキシャルシリコンウェーハ
CN108878310B (zh) * 2017-05-12 2022-01-25 无锡华润安盛科技有限公司 芯片切割系统及其控制电路
CN109509704B (zh) * 2017-09-15 2024-08-09 胜高股份有限公司 外延硅晶片的制备方法
JP6835006B2 (ja) * 2018-02-16 2021-02-24 株式会社Sumco エピタキシャルシリコンウェーハにおける積層欠陥の発生予測方法及びエピタキシャルシリコンウェーハの製造方法
JP6713493B2 (ja) * 2018-02-26 2020-06-24 株式会社Sumco エピタキシャルシリコンウェーハの製造方法及びエピタキシャルシリコンウェーハ
JP7491705B2 (ja) * 2020-02-19 2024-05-28 グローバルウェーハズ・ジャパン株式会社 半導体シリコンウェーハの製造方法
WO2022006396A1 (en) * 2020-07-02 2022-01-06 Atomera Incorporated Method for making a semiconductor device using superlattices with different non-semiconductor thermal stabilities
CN112426527B (zh) * 2020-11-30 2021-09-28 南京大学 一种具有抗肿瘤功能的二维红磷纳米材料
JP7658332B2 (ja) 2021-11-04 2025-04-08 株式会社Sumco シリコンウェーハおよびエピタキシャルシリコンウェーハ
JP7757917B2 (ja) * 2021-11-04 2025-10-22 株式会社Sumco シリコンウェーハおよびエピタキシャルシリコンウェーハ
JP7757916B2 (ja) * 2021-11-04 2025-10-22 株式会社Sumco シリコンウェーハおよびエピタキシャルシリコンウェーハ
JP7775800B2 (ja) * 2022-09-08 2025-11-26 株式会社Sumco シリコンウェーハおよびエピタキシャルシリコンウェーハ

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2790009B2 (ja) 1992-12-11 1998-08-27 信越半導体株式会社 シリコンエピタキシャル層の成長方法および成長装置
JP3824675B2 (ja) 1995-03-03 2006-09-20 有限会社デジタル・ウェーブ 結晶製造装置
EP0798765A3 (en) * 1996-03-28 1998-08-05 Shin-Etsu Handotai Company Limited Method of manufacturing a semiconductor wafer comprising a dopant evaporation preventive film on one main surface and an epitaxial layer on the other main surface
JP3407629B2 (ja) * 1997-12-17 2003-05-19 信越半導体株式会社 シリコン単結晶ウエーハの熱処理方法ならびにシリコン単結晶ウエーハ
JP4470231B2 (ja) 1999-03-31 2010-06-02 株式会社Ｓｕｍｃｏ 半導体シリコンウェーハの製造方法
US6444027B1 (en) * 2000-05-08 2002-09-03 Memc Electronic Materials, Inc. Modified susceptor for use in chemical vapor deposition process
US6663709B2 (en) * 2001-06-26 2003-12-16 Memc Electronic Materials, Inc. Crystal puller and method for growing monocrystalline silicon ingots
JP4089809B2 (ja) 2002-03-13 2008-05-28 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 半導体ウェーハのエッジ部の酸化膜除去装置
EP1576207A2 (en) 2002-05-07 2005-09-21 Microfabrica Inc. Methods of and apparatus for molding structures
KR100603588B1 (ko) 2004-06-09 2006-07-24 주식회사 하이닉스반도체 낮은 콘택 저항을 갖는 반도체 소자 및 그 제조 방법
JP4815801B2 (ja) * 2004-12-28 2011-11-16 信越半導体株式会社 シリコンウエーハの研磨方法および製造方法および円板状ワークの研磨装置ならびにシリコンウエーハ
KR100827038B1 (ko) 2006-12-21 2008-05-02 주식회사 실트론 헤이즈가 없는 실리콘 에피택셜 웨이퍼의 제조 방법
JP5012554B2 (ja) 2008-02-19 2012-08-29 株式会社Ｓｕｍｃｏ エピタキシャルウェーハの製造方法
US8101508B2 (en) 2008-03-05 2012-01-24 Sumco Corporation Silicon substrate and manufacturing method thereof
JP5347288B2 (ja) * 2008-03-17 2013-11-20 信越半導体株式会社 シリコンエピタキシャルウェーハの製造方法
JP2010153631A (ja) * 2008-12-25 2010-07-08 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 エピタキシャルシリコンウェーハとその製造方法
DE102009010556B4 (de) 2009-02-25 2013-11-07 Siltronic Ag Verfahren zur Herstellung von epitaxierten Siliciumscheiben
JP5463693B2 (ja) 2009-03-03 2014-04-09 信越半導体株式会社 シリコンエピタキシャルウェーハの製造方法
JP5246065B2 (ja) * 2009-06-29 2013-07-24 株式会社Ｓｕｍｃｏ エピタキシャルシリコンウェーハとその製造方法
JP5609025B2 (ja) 2009-06-29 2014-10-22 株式会社Sumco エピタキシャルシリコンウェーハの製造方法
JP2011029440A (ja) 2009-07-27 2011-02-10 Renesas Electronics Corp 半導体装置の製造方法および条件出力システム
JP5445075B2 (ja) 2009-11-27 2014-03-19 株式会社Ｓｕｍｃｏ エピタキシャルウェーハの製造方法
JP6009237B2 (ja) 2012-06-18 2016-10-19 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12046469B2 (en) 2020-02-19 2024-07-23 Globalwafers Japan Co., Ltd. Manufacturing method for semiconductor silicon wafer
US12308228B2 (en) 2020-02-19 2025-05-20 Globalwafers Japan Co., Ltd. Manufacturing method for semiconductor silicon wafer

Also Published As

Publication number Publication date
US20140001605A1 (en) 2014-01-02
KR20140002509A (ko) 2014-01-08
US9755022B2 (en) 2017-09-05
KR101473784B1 (ko) 2014-12-17
US9425264B2 (en) 2016-08-23
US20150380493A1 (en) 2015-12-31
JP2014011293A (ja) 2014-01-20

Similar Documents

Publication Publication Date Title
JP5845143B2 (ja) エピタキシャルシリコンウェーハの製造方法、および、エピタキシャルシリコンウェーハ
CN107533959B (zh) 外延硅晶片的制造方法
JP5890587B2 (ja) 単結晶の製造方法およびシリコンウェーハの製造方法
JP5892232B1 (ja) 単結晶の製造方法およびシリコンウェーハの製造方法
JP2014011293A5 (https=)
JP5533869B2 (ja) エピタキシャルシリコンウェーハとその製造方法
JP2025157587A (ja) シリコンウェーハおよびエピタキシャルシリコンウェーハ
JP2025146998A (ja) シリコンウェーハおよびエピタキシャルシリコンウェーハ
WO2021166895A1 (ja) 半導体シリコンウェーハの製造方法
JP4510997B2 (ja) シリコン半導体基板およびその製造方法
JP7757917B2 (ja) シリコンウェーハおよびエピタキシャルシリコンウェーハ
CN109509704B (zh) 外延硅晶片的制备方法
JP7775800B2 (ja) シリコンウェーハおよびエピタキシャルシリコンウェーハ
CN116072515B (zh) 硅晶片和外延硅晶片
JP2023070019A (ja) シリコンウェーハおよびエピタキシャルシリコンウェーハ

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150305

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20150305

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20150305

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20150501

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150609

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150729

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20151027

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20151120

R150 Certificate of patent or registration of utility model

Ref document number: 5845143

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250