JP5692379B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5692379B2 JP5692379B2 JP2013522808A JP2013522808A JP5692379B2 JP 5692379 B2 JP5692379 B2 JP 5692379B2 JP 2013522808 A JP2013522808 A JP 2013522808A JP 2013522808 A JP2013522808 A JP 2013522808A JP 5692379 B2 JP5692379 B2 JP 5692379B2
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Description
前記選択酸化膜形成工程において、前記選択酸化膜を形成する際に、前記第2導電型不純物を熱拡散させて前記第2導電型半導体領域を形成してもよい。
前記制御用ゲート電極形成工程の後に、前記選択酸化膜形成工程において形成された第2半導体領域表面に前記第2の第1導電型半導体領域を形成する第2の第1導電型半導体領域形成工程を行ってもよい。
本発明の実施の形態1にかかる半導体装置の製造方法により作製(製造)された縦型トレンチゲートパワーICの構成について、図7,12を参照して説明する。図12は、本発明の実施の形態1にかかる半導体装置の製造方法により製造された縦型トレンチゲートパワーICの要部を示す断面図である。図7に示すように、本発明の実施の形態1にかかる半導体装置の製造方法により製造された縦型トレンチゲートパワーIC101は、出力段MOSFET(出力段MOS型半導体素子)102と制御回路部103とからなる。制御回路部103は、プルダウン用MOSFET(制御用MOS型半導体素子)107と、その駆動回路108とを含んでいる。
図13は、本発明の実施の形態2にかかる半導体装置の製造方法により製造された縦型トレンチゲートパワーICの要部を示す断面図である。実施の形態2にかかる半導体装置が実施の形態1にかかる半導体装置と異なる点は、n+型半導体基板2とドレイン電極膜1との間にp+コレクタ領域となるp+型半導体層41を追加し、縦型トレンチゲートMOSFET領域21の出力段MOS型半導体素子を縦型トレンチゲートIGBT(絶縁ゲート型バイポーラトランジスタ)とした点である。すなわち、図13では、符号9,12e,1はそれぞれn+型エミッタ領域、エミッタ電極、コレクタ電極となる。
実施の形態3にかかる縦型トレンチゲートパワーICの製造方法が実施の形態1にかかる縦型トレンチゲートパワーICの製造方法と異なる点は、LOCOS酸化膜11を形成する前に、出力段MOSFETのゲート構造を形成する点である。この実施の形態3においては、出力段MOS型半導体素子を縦型トレンチゲートMOSFETとし、制御用MOS型半導体素子をCMOSとした構成の縦型トレンチゲートパワーICを例に説明する。図1は、本発明の実施の形態3にかかる半導体装置の製造方法により製造された縦型トレンチゲートパワーICの要部を示す断面図である。縦型トレンチゲートMOSFET領域21および接合終端領域23の構成は、実施の形態1と同様である。
2 n+型半導体基板またはn+型エピタキシャル半導体層
3 n-型エピタキシャル半導体層
4 p-ウェル領域
5 p型チャネル拡散領域
6 ゲート電極
6a,6b ポリシリコン膜
6c ポリシリコン配線
7a 第1ゲート酸化膜
7b 第2ゲート酸化膜
8 p+型領域(p+型ソース領域またはp+型ドレイン領域)
9 n+型領域(n+型ソース領域またはn+型ドレイン領域)
10 p+型コンタクト領域
11 LOCOS酸化膜
12a〜12d 電極膜(ドレイン電極膜、ソース電極膜)
12e ソース電極膜
12f メタル配線
13、14 ソース電極膜またはドレイン電極膜
18 層間絶縁膜
19 n-型オフセットドレイン領域
21 縦型トレンチゲートMOSFET領域
22 横型プレーナゲートMOSFET領域
22a 横型プレーナゲートnチャネルMOSFET領域
22b 横型プレーナゲートpチャネルMOSFET領域
23 接合終端領域
31 マスク酸化膜
32 レジスト
33 トレンチ
34 バッファ酸化膜
35 シリコン窒化膜
36 n-拡散領域
37 p-拡散領域
41 p+型半導体層
101 縦型トレンチゲートパワーIC
102 出力段MOSFET
103 制御回路部
104 ゲート入力端子
105 ドレイン端子
106 ソース端子
107 プルダウン用MOSFET
108 駆動回路
Claims (10)
- 第1導電型半導体基板の第1の主面側に形成された第1の第1導電型半導体領域と、前記第1導電型半導体基板の第2の主面側の表面層にて選択的に形成された第2導電型半導体領域と、前記第2導電型半導体領域の表面層に選択的に形成された第2の第1導電型半導体領域と、前記第2導電型半導体領域の表面から前記第2導電型半導体領域と前記第2の第1導電型半導体領域とを貫通して前記第1導電型半導体基板に到達するトレンチと、前記トレンチの内壁に沿って形成された第1ゲート酸化膜と、前記トレンチの内部に前記第1ゲート酸化膜を介して形成されたゲート電極と、を有する主半導体素子部と、前記第1導電型半導体基板の第2の主面側の表面に選択的に形成された、前記第1ゲート酸化膜よりも厚さの厚い選択酸化膜を有する素子分離部と、前記第1導電型半導体基板の第2の主面側の、前記素子分離部によって前記主半導体素子部と分離された部分の表面層に形成された第2導電型ウェル拡散領域と、前記第2導電型ウェル拡散領域の表面に第2ゲート酸化膜を介して形成された制御用ゲート電極と、前記第2導電型ウェル拡散領域の表面層に選択的に形成された第1導電型制御ソース領域と、前記第2導電型ウェル拡散領域の表面層に、前記第2導電型ウェル拡散領域の、前記制御用ゲート電極に対向する部分を挟んで、前記第1導電型制御ソース領域と離れて形成された第1導電型制御ドレイン領域と、を有し、前記主半導体素子部を制御する制御用半導体素子部と、を備えた半導体装置の製造方法であって、
前記第1導電型半導体基板の第2の主面に前記トレンチを形成するトレンチ形成工程と、
前記トレンチの内壁に沿って前記第1ゲート酸化膜を形成する第1ゲート酸化膜形成工程と、
前記トレンチの内部に、前記第1ゲート酸化膜を介して前記ゲート電極を形成するゲート電極形成工程と、
前記第1導電型半導体基板の第2の主面に、前記選択酸化膜を選択的に形成する選択酸化膜形成工程と、
前記第1導電型半導体基板の第2の主面に、前記第1ゲート酸化膜よりも厚さの薄い前記第2ゲート酸化膜を形成する第2ゲート酸化膜形成工程と、
前記第2ゲート酸化膜上に前記制御用ゲート電極を形成する制御用ゲート電極形成工程と、
を含み、
前記トレンチ形成工程よりも前に、前記第2導電型半導体領域の形成箇所に第2導電型不純物をイオン注入するチャネルイオン注入工程をさらに含み、
前記選択酸化膜形成工程が、前記トレンチ形成工程よりも後の工程にて行われることを特徴とする半導体装置の製造方法。 - 前記選択酸化膜形成工程において、前記選択酸化膜を形成する際に、前記第2導電型不純物を熱拡散させて前記第2導電型半導体領域を形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記制御用ゲート電極形成工程の後に、前記選択酸化膜形成工程において形成された第2半導体領域表面に前記第2の第1導電型半導体領域を形成する第2の第1導電型半導体領域形成工程を含むことを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 前記選択酸化膜形成工程が、前記ゲート電極形成工程よりも後の工程にて行われることを特徴とする請求項1〜3のいずれか一つに記載の半導体装置の製造方法。
- 前記トレンチ形成工程、前記第1ゲート酸化膜形成工程、前記ゲート電極形成工程、前記選択酸化膜形成工程、前記第2ゲート酸化膜形成工程および前記制御用ゲート電極形成工程の順に行われることを特徴とする請求項1〜4のいずれか一つに記載の半導体装置の製造方法。
- 前記選択酸化膜がLOCOS酸化膜であることを特徴とする請求項1〜5のいずれか一つに記載の半導体装置の製造方法。
- 前記ゲート電極形成工程では、前記トレンチの内部にポリシリコンを充填することにより前記ゲート電極を形成し、
前記制御用ゲート電極形成工程では、前記第2ゲート酸化膜上にポリシリコンを堆積することにより前記制御用ゲート電極を形成し、
前記ゲート電極形成工程と前記制御用ゲート電極形成工程とが同一工程であることを特徴とする請求項1〜6のいずれか一つに記載の半導体装置の製造方法。 - 前記主半導体素子部に、縦型または横型のトレンチゲート型の絶縁ゲート型電界効果トランジスタを備えることを特徴とする請求項1〜7のいずれか一つに記載の半導体装置の製造方法。
- 前記主半導体素子部に、縦型または横型のトレンチゲート型の絶縁ゲート型バイポーラトランジスタを備えることを特徴とする請求項1〜7のいずれか一つに記載の半導体装置の製造方法。
- 前記制御用半導体素子部に、横型のプレーナゲート型の絶縁ゲート型電界効果トランジスタまたは横型のトレンチゲート型の絶縁ゲート型電界効果トランジスタを備えることを特徴とする請求項1〜9のいずれか一つに記載の半導体装置の製造方法。
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