JP5680401B2 - 配線基板及び半導体パッケージ - Google Patents

配線基板及び半導体パッケージ Download PDF

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Publication number
JP5680401B2
JP5680401B2 JP2010286677A JP2010286677A JP5680401B2 JP 5680401 B2 JP5680401 B2 JP 5680401B2 JP 2010286677 A JP2010286677 A JP 2010286677A JP 2010286677 A JP2010286677 A JP 2010286677A JP 5680401 B2 JP5680401 B2 JP 5680401B2
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JP
Japan
Prior art keywords
layer
wiring
solder resist
exposed
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010286677A
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English (en)
Japanese (ja)
Other versions
JP2012134396A (ja
JP2012134396A5 (OSRAM
Inventor
文久 宮坂
文久 宮坂
淳史 佐藤
淳史 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2010286677A priority Critical patent/JP5680401B2/ja
Priority to US13/330,944 priority patent/US8587104B2/en
Publication of JP2012134396A publication Critical patent/JP2012134396A/ja
Publication of JP2012134396A5 publication Critical patent/JP2012134396A5/ja
Application granted granted Critical
Publication of JP5680401B2 publication Critical patent/JP5680401B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
JP2010286677A 2010-12-22 2010-12-22 配線基板及び半導体パッケージ Active JP5680401B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2010286677A JP5680401B2 (ja) 2010-12-22 2010-12-22 配線基板及び半導体パッケージ
US13/330,944 US8587104B2 (en) 2010-12-22 2011-12-20 Wiring board and semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010286677A JP5680401B2 (ja) 2010-12-22 2010-12-22 配線基板及び半導体パッケージ

Publications (3)

Publication Number Publication Date
JP2012134396A JP2012134396A (ja) 2012-07-12
JP2012134396A5 JP2012134396A5 (OSRAM) 2013-10-31
JP5680401B2 true JP5680401B2 (ja) 2015-03-04

Family

ID=46315636

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010286677A Active JP5680401B2 (ja) 2010-12-22 2010-12-22 配線基板及び半導体パッケージ

Country Status (2)

Country Link
US (1) US8587104B2 (OSRAM)
JP (1) JP5680401B2 (OSRAM)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI473551B (zh) * 2011-07-08 2015-02-11 欣興電子股份有限公司 封裝基板及其製法
JP6179097B2 (ja) * 2012-12-25 2017-08-16 株式会社村田製作所 多層電子部品及び集合基板
JP6081875B2 (ja) * 2013-04-28 2017-02-15 京セラ株式会社 配線基板の製造方法
JP6158676B2 (ja) * 2013-10-15 2017-07-05 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
KR20150083278A (ko) * 2014-01-09 2015-07-17 삼성전기주식회사 다층기판 및 다층기판의 제조방법
JP6208054B2 (ja) * 2014-03-10 2017-10-04 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
KR101672641B1 (ko) * 2015-07-01 2016-11-03 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
TWI689996B (zh) * 2016-04-28 2020-04-01 李志雄 半導體裝置之中介層製造方法
KR102099750B1 (ko) 2017-11-01 2020-04-10 삼성전자주식회사 반도체 패키지
US12205877B2 (en) 2019-02-21 2025-01-21 AT&S(Chongqing) Company Limited Ultra-thin component carrier having high stiffness and method of manufacturing the same
CN111599687B (zh) * 2019-02-21 2022-11-15 奥特斯科技(重庆)有限公司 具有高刚度的超薄部件承载件及其制造方法
US11540396B2 (en) * 2020-08-28 2022-12-27 Unimicron Technology Corp. Circuit board structure and manufacturing method thereof
US11991824B2 (en) * 2020-08-28 2024-05-21 Unimicron Technology Corp. Circuit board structure and manufacturing method thereof
CN114531787A (zh) * 2020-11-23 2022-05-24 碁鼎科技秦皇岛有限公司 电路板防焊层的制备方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06101616B2 (ja) * 1986-02-21 1994-12-12 名幸電子工業株式会社 導体回路板の製造方法
US5106454A (en) * 1990-11-01 1992-04-21 Shipley Company Inc. Process for multilayer printed circuit board manufacture
JP3361903B2 (ja) * 1994-01-06 2003-01-07 凸版印刷株式会社 プリント配線板の製造方法
JP4038845B2 (ja) * 1997-04-28 2008-01-30 住友化学株式会社 カラーフィルター用緑色組成物およびカラーフィルター
JP3821993B2 (ja) * 1999-05-31 2006-09-13 日本特殊陶業株式会社 プリント配線基板
JP2006114859A (ja) * 2004-01-21 2006-04-27 Seiko Epson Corp アライメント方法、薄膜形成基板の製造方法、半導体装置の製造方法、及び電子機器の製造方法
US8502398B2 (en) * 2007-10-05 2013-08-06 Shinko Electric Industries Co., Ltd. Wiring board, semiconductor apparatus and method of manufacturing them

Also Published As

Publication number Publication date
US20120161311A1 (en) 2012-06-28
US8587104B2 (en) 2013-11-19
JP2012134396A (ja) 2012-07-12

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