JP5669251B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

Info

Publication number
JP5669251B2
JP5669251B2 JP2010010085A JP2010010085A JP5669251B2 JP 5669251 B2 JP5669251 B2 JP 5669251B2 JP 2010010085 A JP2010010085 A JP 2010010085A JP 2010010085 A JP2010010085 A JP 2010010085A JP 5669251 B2 JP5669251 B2 JP 5669251B2
Authority
JP
Japan
Prior art keywords
insulating film
groove
dtr
trench dtr
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2010010085A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011151121A (ja
JP2011151121A5 (enExample
Inventor
勝巳 森井
勝巳 森井
良孝 大津
良孝 大津
一真 大西
一真 大西
新田　哲也
哲也 新田
竜也 城本
竜也 城本
成太 徳光
成太 徳光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2010010085A priority Critical patent/JP5669251B2/ja
Priority to CN201110025275.7A priority patent/CN102157431B/zh
Priority to US13/010,417 priority patent/US8569839B2/en
Publication of JP2011151121A publication Critical patent/JP2011151121A/ja
Publication of JP2011151121A5 publication Critical patent/JP2011151121A5/ja
Application granted granted Critical
Publication of JP5669251B2 publication Critical patent/JP5669251B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers

Landscapes

  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
JP2010010085A 2010-01-20 2010-01-20 半導体装置の製造方法 Expired - Fee Related JP5669251B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2010010085A JP5669251B2 (ja) 2010-01-20 2010-01-20 半導体装置の製造方法
CN201110025275.7A CN102157431B (zh) 2010-01-20 2011-01-19 半导体器件及其制造方法
US13/010,417 US8569839B2 (en) 2010-01-20 2011-01-20 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010010085A JP5669251B2 (ja) 2010-01-20 2010-01-20 半導体装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2014249980A Division JP6097269B2 (ja) 2014-12-10 2014-12-10 半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
JP2011151121A JP2011151121A (ja) 2011-08-04
JP2011151121A5 JP2011151121A5 (enExample) 2012-09-20
JP5669251B2 true JP5669251B2 (ja) 2015-02-12

Family

ID=44276976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010010085A Expired - Fee Related JP5669251B2 (ja) 2010-01-20 2010-01-20 半導体装置の製造方法

Country Status (3)

Country Link
US (1) US8569839B2 (enExample)
JP (1) JP5669251B2 (enExample)
CN (1) CN102157431B (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5729745B2 (ja) * 2009-09-15 2015-06-03 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8692318B2 (en) * 2011-05-10 2014-04-08 Nanya Technology Corp. Trench MOS structure and method for making the same
JP5955064B2 (ja) * 2012-04-17 2016-07-20 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US9269609B2 (en) * 2012-06-01 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor isolation structure with air gaps in deep trenches
KR102057340B1 (ko) * 2013-03-29 2019-12-19 매그나칩 반도체 유한회사 반도체 소자 및 그 제조방법
JP6278608B2 (ja) * 2013-04-08 2018-02-14 キヤノン株式会社 半導体装置およびその製造方法
JP6266418B2 (ja) 2014-04-14 2018-01-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN104362172B (zh) * 2014-10-15 2018-09-11 杰华特微电子（杭州）有限公司 具有终端环的半导体芯片结构及其制造方法
JP6330674B2 (ja) * 2015-01-27 2018-05-30 トヨタ自動車株式会社 半導体装置
JP6559499B2 (ja) * 2015-08-10 2019-08-14 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2017191858A (ja) * 2016-04-14 2017-10-19 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2018010985A (ja) * 2016-07-14 2018-01-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
WO2018020713A1 (ja) * 2016-07-28 2018-02-01 パナソニックＩｐマネジメント株式会社 半導体装置およびその製造方法
JP2018078215A (ja) * 2016-11-10 2018-05-17 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
WO2018110141A1 (ja) 2016-12-14 2018-06-21 日立オートモティブシステムズ株式会社 負荷駆動装置
US20180226292A1 (en) * 2017-02-06 2018-08-09 Globalfoundries Inc. Trench isolation formation from the substrate back side using layer transfer
JP6936027B2 (ja) 2017-03-09 2021-09-15 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10224396B1 (en) 2017-11-20 2019-03-05 Globalfoundries Inc. Deep trench isolation structures
US10886165B2 (en) * 2018-06-15 2021-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming negatively sloped isolation structures
US11302734B2 (en) * 2018-06-29 2022-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Deep trench isolation structures resistant to cracking
JP2020057639A (ja) * 2018-09-28 2020-04-09 ソニーセミコンダクタソリューションズ株式会社 半導体装置及び半導体装置の製造方法
KR102259601B1 (ko) 2019-04-26 2021-06-02 주식회사 키 파운드리 깊은 트렌치 구조를 갖는 반도체 소자 및 그 제조방법
US11502036B2 (en) * 2020-02-07 2022-11-15 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
WO2022160113A1 (zh) * 2021-01-27 2022-08-04 中芯北方集成电路制造(北京)有限公司 半导体结构及其形成方法
US11798836B2 (en) * 2021-06-17 2023-10-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor isolation structure and method of making the same
KR102881905B1 (ko) * 2021-12-15 2025-11-05 주식회사 디비하이텍 반도체 소자 및 제조방법
US20240105504A1 (en) * 2022-09-23 2024-03-28 Vanguard International Semiconductor Corporation Semiconductor device and method of manufacturing the same
KR20240114006A (ko) * 2023-01-16 2024-07-23 주식회사 디비하이텍 반도체 소자 및 제조방법

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59172246A (ja) * 1983-03-18 1984-09-28 Seiko Instr & Electronics Ltd 凹部分離半導体装置とその製造方法
JPH04290246A (ja) 1991-03-19 1992-10-14 Kawasaki Steel Corp 集積回路の素子分離法
JPH0766282A (ja) * 1993-08-25 1995-03-10 Sony Corp 半導体装置
JP2002083866A (ja) 2000-09-07 2002-03-22 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP4285899B2 (ja) 2000-10-10 2009-06-24 三菱電機株式会社 溝を有する半導体装置
JP2002184854A (ja) * 2000-12-12 2002-06-28 Sony Corp 半導体装置の製造方法
JP2002280447A (ja) * 2001-03-21 2002-09-27 Sony Corp 半導体装置の製造方法
JP4273782B2 (ja) 2003-02-13 2009-06-03 セイコーエプソン株式会社 半導体装置の製造方法及び半導体基板の製造方法
JP2006049828A (ja) * 2004-07-05 2006-02-16 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US20070235783A9 (en) * 2005-07-19 2007-10-11 Micron Technology, Inc. Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions
JP2007142276A (ja) 2005-11-21 2007-06-07 Toshiba Corp 半導体装置及びその製造方法
JP2007189110A (ja) * 2006-01-13 2007-07-26 Sharp Corp 半導体装置及びその製造方法
JP2008021675A (ja) 2006-07-10 2008-01-31 Renesas Technology Corp 半導体装置およびその製造方法
JP5132928B2 (ja) * 2006-12-25 2013-01-30 パナソニック株式会社 半導体装置
JP2009032967A (ja) * 2007-07-27 2009-02-12 Toshiba Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
JP2011151121A (ja) 2011-08-04
US20110175205A1 (en) 2011-07-21
CN102157431B (zh) 2015-04-08
CN102157431A (zh) 2011-08-17
US8569839B2 (en) 2013-10-29

Similar Documents

Publication Publication Date Title
JP2011151121A (ja) 半導体装置およびその製造方法
CN113611705B (zh) 半导体存储器元件及其制备方法
US12363994B2 (en) Residue-free metal gate cutting for fin-like field effect transistor
JP5729745B2 (ja) 半導体装置およびその製造方法
US10062581B2 (en) Methods of forming an isolation structure and methods of manufacturing a semiconductor device including the same
KR101639483B1 (ko) 반도체 디바이스의 ｆｉｎ 구조물 및 그 제조 방법
JP6097269B2 (ja) 半導体装置およびその製造方法
US7705417B2 (en) Semiconductor device and method of fabricating isolation region
US20140291767A1 (en) Semiconductor device and manufacturing method thereof
JP6559499B2 (ja) 半導体装置の製造方法
JP5691074B2 (ja) 半導体装置の製造方法
JP5955064B2 (ja) 半導体装置およびその製造方法
TWI690025B (zh) 絕緣體上半導體基底、其形成方法以及積體電路
JP6382288B2 (ja) 半導体装置およびその製造方法
JP2015122543A (ja) 半導体装置およびその製造方法
TWI511187B (zh) 製作具有本地接點之半導體裝置之方法
JP2014075402A (ja) 半導体装置及び半導体装置の形成方法
JP2006147800A (ja) Ｓｏｉ−ｍｏｓトランジスタ及びその製造方法
JP2007103417A (ja) 半導体装置及びその製造方法
KR20070042322A (ko) 분리 트렌치와 리세스 채널 어레이 트렌치가 동시에형성되는 반도체 소자 및 그 제조방법
JP2010287774A (ja) 半導体装置の製造方法
JP2007059784A (ja) 半導体装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120806

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120806

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20131010

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20131022

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131220

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140624

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140821

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20141118

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20141212

R150 Certificate of patent or registration of utility model

Ref document number: 5669251

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees