JP5640272B2 - 回路層転写により多層構造体を製作する方法 - Google Patents
回路層転写により多層構造体を製作する方法 Download PDFInfo
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- JP5640272B2 JP5640272B2 JP2011553398A JP2011553398A JP5640272B2 JP 5640272 B2 JP5640272 B2 JP 5640272B2 JP 2011553398 A JP2011553398 A JP 2011553398A JP 2011553398 A JP2011553398 A JP 2011553398A JP 5640272 B2 JP5640272 B2 JP 5640272B2
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- 238000000034 method Methods 0.000 title claims description 32
- 239000000758 substrate Substances 0.000 claims description 213
- 230000015572 biosynthetic process Effects 0.000 claims description 26
- 239000002131 composite material Substances 0.000 claims description 10
- 239000010410 layer Substances 0.000 description 74
- 235000012431 wafers Nutrition 0.000 description 30
- 238000010586 diagram Methods 0.000 description 12
- 238000000206 photolithography Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000005201 scrubbing Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000005411 Van der Waals force Methods 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000013590 bulk material Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000012809 cooling fluid Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000004579 marble Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Laminated Bodies (AREA)
- Micromachines (AREA)
Description
Claims (13)
- マイクロコンポーネント(110)の第1の層を第1の基板(100)の1つの面に形成するステップであって、前記第1の基板が、前記マイクロコンポーネント(110)を形成する間第1の支持体(121)の保持表面(121a)に対して平坦に保持される、ステップと、前記マイクロコンポーネント(110)の前記層を含む前記第1の基板(100)の前記面を第2の基板(200)上に接合するステップとを含む、複合構造体(300)を形成する方法において、接合する前記ステップの間、前記第1の基板又は前記第2の基板が第2の支持体(221)に対して平坦に保持され、前記第2の支持体(221)の保持表面(221a)が、前記マイクロコンポーネント(110)の前記第1の層を形成する間使用された前記第1の支持体(120)の平坦度以下である平坦度を有し、
前記第1の基板と前記第2の基板との間の接合は、分子接合である、ことを特徴とする方法。 - 前記第1の支持体(121)の前記保持表面(121a)の前記平坦度が2μm以下であることを特徴とする請求項1に記載の方法。
- 接合する前記ステップの間、前記第1の基板(100)が前記第2の支持体(221)に対して平坦に保持されることを特徴とする請求項1又は請求項2に記載の方法。
- 接合する前記ステップの間、前記第1の基板(100)及び前記第2の基板(200)が実質的に同等な温度に維持されることを特徴とする請求項1〜3のいずれか一項に記載の方法。
- 接合する前記ステップの間、少なくとも前記第1の基板(100)が、前記マイクロコンポーネント(110)の前記第1の層を形成する前記ステップの間の前記第1の基板の温度と実質的に同等な温度に維持されることを特徴とする請求項1〜3のいずれか一項に記載の方法。
- 接合する前記ステップの間、前記第1の基板(100)と前記第2の基板(200)との間の温度差が±0.5℃以下であることを特徴とする請求項4又は請求項5に記載の方法。
- 前記接合するステップの後に前記第1の基板(100)を薄化するステップを含むことを特徴とする請求項1〜6のいずれか一項に記載の方法。
- 前記第2の基板(200)がマイクロコンポーネントを含むことを特徴とする請求項1〜7のいずれか一項に記載の方法。
- 前記マイクロコンポーネント(110)の第1の層を含む前記面とは反対側の前記第1の基板(100)の面にマイクロコンポーネント(140)の第2の層を形成するステップをさらに含むことを特徴とする請求項1〜8のいずれか一項に記載の方法。
- 接合する前記ステップの前に、前記マイクロコンポーネント(110)の第1の層を含む前記第1の基板(100)の前記面に酸化物の層(104)を形成するステップを含むことを特徴とする請求項1〜9のいずれか一項に記載の方法。
- 前記第1の基板(100)がSOI型構造体によって構成されることを特徴とする請求項1〜10のいずれか一項に記載の方法。
- 前記マイクロコンポーネント(110)の前記第1の層を形成するステップ及び前記接合するステップの間、支持プラテン(221)を備える基板搬送デバイス(220)が使用され、前記基板搬送デバイスが前記支持プラテン(221)の前記保持表面(221a)上に前記第1の基板(100)を保持することができることを特徴とする請求項1〜11のいずれか一項に記載の方法。
- 前記第1の基板(100)が、吸引によって、毛管引力によって、又は静電力によって前記支持プラテン(221)に対して平坦に保持されることを特徴とする請求項12に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0951543A FR2943177B1 (fr) | 2009-03-12 | 2009-03-12 | Procede de fabrication d'une structure multicouche avec report de couche circuit |
FR0951543 | 2009-03-12 | ||
PCT/EP2010/052765 WO2010102943A1 (en) | 2009-03-12 | 2010-03-04 | A method of fabricating a multilayer structure with circuit layer transfer |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012520556A JP2012520556A (ja) | 2012-09-06 |
JP5640272B2 true JP5640272B2 (ja) | 2014-12-17 |
Family
ID=41110979
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011553398A Expired - Fee Related JP5640272B2 (ja) | 2009-03-12 | 2010-03-04 | 回路層転写により多層構造体を製作する方法 |
Country Status (9)
Country | Link |
---|---|
US (1) | US8932938B2 (ja) |
EP (1) | EP2406820A1 (ja) |
JP (1) | JP5640272B2 (ja) |
KR (1) | KR101379887B1 (ja) |
CN (1) | CN102349149B (ja) |
FR (1) | FR2943177B1 (ja) |
SG (1) | SG173813A1 (ja) |
TW (1) | TWI475640B (ja) |
WO (1) | WO2010102943A1 (ja) |
Families Citing this family (12)
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FR2943177B1 (fr) | 2009-03-12 | 2011-05-06 | Soitec Silicon On Insulator | Procede de fabrication d'une structure multicouche avec report de couche circuit |
FR2947380B1 (fr) | 2009-06-26 | 2012-12-14 | Soitec Silicon Insulator Technologies | Procede de collage par adhesion moleculaire. |
US9190269B2 (en) * | 2010-03-10 | 2015-11-17 | Purdue Research Foundation | Silicon-on-insulator high power amplifiers |
FR2965398B1 (fr) * | 2010-09-23 | 2012-10-12 | Soitec Silicon On Insulator | Procédé de collage par adhésion moléculaire avec réduction de desalignement de type overlay |
FR2978864B1 (fr) * | 2011-08-02 | 2014-02-07 | Soitec Silicon On Insulator | Procede de correction de desalignement de positions sur une premiere plaque collee sur une deuxieme plaque |
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-
2009
- 2009-03-12 FR FR0951543A patent/FR2943177B1/fr not_active Expired - Fee Related
-
2010
- 2010-03-04 JP JP2011553398A patent/JP5640272B2/ja not_active Expired - Fee Related
- 2010-03-04 KR KR1020117021845A patent/KR101379887B1/ko active IP Right Grant
- 2010-03-04 US US13/255,670 patent/US8932938B2/en not_active Expired - Fee Related
- 2010-03-04 WO PCT/EP2010/052765 patent/WO2010102943A1/en active Application Filing
- 2010-03-04 SG SG2011060613A patent/SG173813A1/en unknown
- 2010-03-04 EP EP10706264A patent/EP2406820A1/en not_active Withdrawn
- 2010-03-04 CN CN201080011159.3A patent/CN102349149B/zh not_active Expired - Fee Related
- 2010-03-12 TW TW099107357A patent/TWI475640B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN102349149B (zh) | 2014-12-17 |
FR2943177B1 (fr) | 2011-05-06 |
KR101379887B1 (ko) | 2014-04-01 |
WO2010102943A1 (en) | 2010-09-16 |
SG173813A1 (en) | 2011-09-29 |
JP2012520556A (ja) | 2012-09-06 |
KR20110120328A (ko) | 2011-11-03 |
TW201041085A (en) | 2010-11-16 |
US8932938B2 (en) | 2015-01-13 |
TWI475640B (zh) | 2015-03-01 |
FR2943177A1 (fr) | 2010-09-17 |
CN102349149A (zh) | 2012-02-08 |
EP2406820A1 (en) | 2012-01-18 |
US20120028440A1 (en) | 2012-02-02 |
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